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Sorry, there was a problem with my last message. I send it once more.
Hi Everybody.
I want to design a FPGA (virtex E) with the following features:
I've got 2 data sources DataA and DataB, they are synchronous and they
toggle at 50 MHz.
I want to process them with the same component. Therefore, i use a DLL to
generate a 100 MHz Clock with the 50 MHz data Clock.
Now, i have to switch between DataA and DataB to generate the input data of
the component. Therefore, I use the output CLK90 (or CLK270) of the DLL.
DLL_Inst: CLKDLL port map(
CLKIN => Clk50MHz, -- Input Clk
CLKFB => ClkSimple, -- 50 MHz Clk
RST => Rst,
CLK0 => CLK0, -- 50 MHz Clk
CLK90 => CLK90,
CLK180 => CLK180,
CLK270 => CLK270,
CLK2X => CLK2X, -- 100 MHz Clk
CLKDV => CLKDV,
Locked => Locked
);
BufGSimple: BUFG port map ( -- 50 MHz Clk
I => CLK0,
O => CLKSimple
);
BufGDouble: BUFG port map ( -- 100 MHz Clk
I => CLK2X,
O => CLKDouble
);
GenClkSimpleR : process (ClkDouble, Rst)
begin -- process GenClkSimpleR
if Rst = '1' then
ClkSimpleR <= '0';
elsif ClkDouble'event and ClkDouble = '1' then
ClkSimpleR <= CLK270;
end if;
end process GenClkSimpleR;
SwitchData : process (ClkDouble, Rst)
begin -- process SwitchData
if Rst = '1' then
DataCompIn <= (others => '0');
elsif ClkDouble'event and ClkDouble = '1' then
if ClkSimpleR = '1' then
DataCompIn <= DataA;
else
DataCompIn <= DataB;
end if;
end if;
end process SwitchData
Component_Inst : Comp port map(
Clk => ClkDouble,
DataIn => DataCompIn ,
DataOut => DataCompOut
);
Now, my problem is I want to put a timing constraint on the net CLK270 and i
don't know how to do this.
This constraint can't neither be FF to FF nor Pad to FF.
Does anybody know how to specify it ? (I Use Foundation)
Second question : what about the skew between ClkSimple and ClkDouble
has anybody got any problem with this ?
J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
Fax : (33) 4 76 18 52 01
E-mail : goglio@getris.com
Article: 20376
Sorry, second problem, this is the end of my message
GenClkSimpleR : process (ClkDouble, Rst)
begin -- process GenClkSimpleR
if Rst = '1' then
ClkSimpleR <= '0';
elsif ClkDouble'event and ClkDouble = '1' then
ClkSimpleR <= CLK270;
end if;
end process GenClkSimpleR;
SwitchData : process (ClkDouble, Rst)
begin -- process SwitchData
if Rst = '1' then
DataCompIn <= (others => '0');
elsif ClkDouble'event and ClkDouble = '1' then
if ClkSimpleR = '1' then
DataCompIn <= DataA;
else
DataCompIn <= DataB;
end if;
end if;
end process SwitchData
Component_Inst : Comp port map(
Clk => ClkDouble,
DataIn => DataCompIn ,
DataOut => DataCompOut
);
Now, my problem is I want to put a timing constraint on the net CLK270 and i
don't know how to do this.
This constraint can't neither be FF to FF nor Pad to FF.
Does anybody know how to specify it ? (I Use Foundation)
Second question : what about the skew between ClkSimple and ClkDouble
has anybody got any problem with this ?
J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
Fax : (33) 4 76 18 52 01
E-mail : goglio@getris.com
Article: 20377funky jim wrote: > > Just found out that RS have a good range also. > The ones RS have aren't the in circuit programmable ones and are VERY expensive. The EPM7128SLC84-15 I got from Farnell was the same price a distributor quoted. BTW, the output levels of these devices are only TTL levels, so you'll need pull ups if you're driving CMOS devices. Nial.Article: 20378
Let me try once more (it's the last one), I apologize if it doesn't work.
Hi Everybody.
I want to design a FPGA (virtex E) with the following features:
I've got 2 data sources DataA and DataB, they are synchronous and they
toggle at 50 MHz.
I want to process them with the same component. Therefore, i use a DLL to
generate a 100 MHz Clock with the 50 MHz data Clock.
Now, i have to switch between DataA and DataB to generate the input data of
the component. Therefore, I use the output CLK90 (or CLK270) of the DLL.
DLL_Inst: CLKDLL port map(
CLKIN => Clk50MHz, -- Input Clk
CLKFB => ClkSimple, -- 50 MHz Clk
RST => Rst,
CLK0 => CLK0, -- 50 MHz Clk
CLK90 => CLK90,
CLK180 => CLK180,
CLK270 => CLK270,
CLK2X => CLK2X, -- 100 MHz Clk
CLKDV => CLKDV,
Locked => Locked
);
BufGSimple: BUFG port map ( -- 50 MHz Clk
I => CLK0,
O => CLKSimple
);
BufGDouble: BUFG port map ( -- 100 MHz Clk
I => CLK2X,
O => CLKDouble
);
GenClkSimpleR : proces (ClkDouble, Rst)
begn -- proces GenClkSimpleR
if Rst = '1' then
ClkSimpleR <= '0';
elsif ClkDouble'event and ClkDouble = '1' then
ClkSimpleR <= CLK270;
end if;
end proces GenClkSimpleR;
SwitchData : proces (ClkDouble, Rst)
begn -- proces SwitchData
if Rst = '1' then
DataCompIn <= (others => '0');
elsif ClkDouble'event and ClkDouble = '1' then
if ClkSimpleR = '1' then
DataCompIn <= DataA;
else
DataCompIn <= DataB;
end if;
end if;
end proces SwitchData
Component_Inst : Comp port map(
Clk => ClkDouble,
DataIn => DataCompIn ,
DataOut => DataCompOut
);
Now, my problem is I want to put a timing constraint on the net CLK270 and i
don't know how to do this.
This constraint can't neither be FF to FF nor Pad to FF.
Does anybody know how to specify it ? (I Use Foundation)
Second question : what about the skew between ClkSimple and ClkDouble
has anybody got any problem with this ?
J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
Fax : (33) 4 76 18 52 01
E-mail : goglio@getris.com
Article: 20379I don't want FPGA express to use a clock buffer for the reset signal. How can I assign, within the fpga express shell, a 'no_clockbuf' attribute to the reset signal. The device I'm synthesizing for is a Xilinx Virtex. Kai -- ----- Dipl. Ing. Kai Troester ------------------------------------- IMMS - Institut fuer Mikroelektronik- und Mechatronik-Systeme gGmbH Langewiesener Strasse 22, 98693 Ilmenau, Germany Tel: +49(3677)6783-42 Fax: +49(3677)6783-38 mailto:kai.troester@imms.de http://www.imms.de/~troester -------------------------------------------------------------------Article: 20380
Hello Paul,
Paul Mondello wrote:
> Basically I would like to be able to download a new FPGA configuration file
> to the Host over the network, re-program the Flash PROM, and then
> re-configure the FPGA with the new code. The FPGA will be connected to an
> embedded processor which will handle the task of interfacing to the Host via
> the PCI bus and passing the configuration bits to the FPGA, which will then
> have the task of re-programming the Flash, I'm guessing through the JTAG
> port. At that point the embedded processor will force the FPGA to
> reconfigure.
It is indeed quite possible to do this. What you need is an on-board JTAG
controller which would connect (on one JTAG chain) both the FPGA and the XC1800.
You can then either design that controller yourself to implement it on the
embedded processor, or you can use a commercially available controller (such as
TI's 8980 or National's PSC100) and interface it to the same processor.
For example, the PSC100 could be interfaced to the embedded processor. It's
basically a 8-bit parallel-to-1149.1 controller; using low-level routines given
by National, you could export configuration data (for the XC1800) from
JTAGprogrammer. That data (which is in SVF or Serial Vector Format) would then
simply need to be executed by the embedded JTAG controller.
There is just one problem for the above solution: JTAGprogrammer does not *yet*
allow SVF export for XC1800s. I've been told it will soon, but in the meantime,
you have no choice but either to use the appropriate cable (such as the parallel
cable, etc.), or design a software/hardware layer which makes the whole
interface look like a parallel cable to JTAGprogrammer, or you could configure
directly by JTAG the FPGA.
In addition (assuming you know about JTAG and SVF), there is a small bug which
affects SIR sequences in the SVF file. That should also be fixed shortly (well,
hopefully).
Regards,
Etienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 20381Use the following, set_pad_buffer "DONT USE" chip/reset That should work. I know FE is crap at reporting the available options for the different families, but I tend to put in dummy options, example set_pad_buffer CRAP chip/reset and hope the tool will report what options are available. It appears to work for most commands. Pete. Kai Troester wrote: > > I don't want FPGA express to use a clock buffer for the reset signal. > How can I assign, within the fpga express shell, a 'no_clockbuf' > attribute to the reset signal. The device I'm synthesizing for is a > Xilinx Virtex. > > Kai > -- > ----- Dipl. Ing. Kai Troester ------------------------------------- > IMMS - Institut fuer Mikroelektronik- und Mechatronik-Systeme gGmbH > Langewiesener Strasse 22, 98693 Ilmenau, Germany > Tel: +49(3677)6783-42 > Fax: +49(3677)6783-38 > mailto:kai.troester@imms.de > http://www.imms.de/~troester > -------------------------------------------------------------------Article: 20382
Hi Mikhail, A generate statement requires a label. Try: L1: if enableP2=TRUE generate or as Mike Treseler pointed out: L1: if enableP2 generate and it should work. Regards, Catalin Mikhail Matusov wrote: > <mench@mench.com> wrote in message news:87ms3h$nns$1@mench.mench.com... > > On Fri, 04 Feb 2000 19:42:13 GMT, in comp.lang.vhdl Mikhail Matusov > > > if ... generate works OUTSIDE of processes. > > I am probably doing something dumb but I can't get this thing through the > syntax check. Here is the idea (not the actual code as I don't want to post > several pages) of what I am doing: > > ..... > > Any suggestions why I am getting syntax error on if enableP2 line? I tried > constants, signals, variables of different types but it seems to be > something else. If I use simple "if" it passes. I am using latest rev of the > Xilinx Foundation tools. > > Thanks, > Mikhail MatusovArticle: 20383
rk <stellare@nospam.erols.com> wrote in message news:389FA8ED.775E5513@nospam.erols.com... > Another case that I've seen, when analyzing a failed design, is when a piece of > CAE code took a flip-flop and an inverter and converted it into two flip-flops, > one with a complemented output. The two flip-flops wound up in an "inconsistent > state" and since the outputs were controlling some high current switches in a > motor, well, BOOM! While originally mis-diagnosed as a failed FPGA - how can a > flip-flop output and it's inversion be the same value? - it turned out the > designer was not aware of how the CAE software helped him out. Yikes! Can you tell us more? What CAE software did this? If the synthesizer duplicates a synchronizing FF, any FSM controlled by that synchronizer could occasionally sense conflicting signals from those FFs and end up in a bad state. If you can advise the rest of us on how to avoid that problem, we'd appreciate it. Paul ButlerArticle: 20384
Rickman wrote: > I will go back to and HDL someday, but it won't be on any design where I > need to optimize for speed or size. It will have to be a project where I > need to meet a tight deadline with no constraints on chip size or > recurring costs. ...Or when you use a device that is not fully supported by schematic entry (Virtex comes to mind), or when a customer (US Gov't for example) requires VHDL? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20385
Rickman <spamgoeshere4@yahoo.com> wrote in message news:389F9EB6.64EF6B07@yahoo.com... > First I would like to point out that FPGA Express is perfectly capable > of removing FFs. I tried to do a one hot FSM and found that I only got > 15 FFs in a 16 state design. The IDLE state was being coded as no FFs > set. To detect being in the IDLE state, there must have been logic to detect that the FSM is not in any other state. That doesn't sound like a one-hot state machine to me. I guess that was related to your other problem: > > Again in > the one hot FSM, I found it very difficult to find the exact coding > style that would prevent the synthesizer from decoding all 15 FSM > variables (FF outputs) as the inputs to all 15 variables. Kinda defeated > the purpose of one hot encoding. In general I always had to play with > the code to get a good implementation of any logic. Could you tell us what coding style didn't work and what you finally settled on? FPGA Express has a setting to control the interpretation of "others" in one-hot state machines. How did that switch affect your result? My usual template for a FSM is one process containing nothing but a case statement that switches on the current state and drives the "next state" signal. A second process infers registers on the "current state" signal. That seems to work pretty well and I haven't experimented much with other styles. Paul ButlerArticle: 20386
Hi Catalin, <a@z.com> wrote in message news:38A01A5B.8B21528D@z.com... > Hi Mikhail, > > A generate statement requires a label. Try: > > L1: if enableP2=TRUE generate That was it, the label! I 'd probably better not say what I think on where VHDL stands comparing to modern SW stuff... Thank you. Mikhail P.S. Sorry folks for starting this whole thing in the comp.arch.fpga BTW.Article: 20387
Pete Little wrote: > > Use the following, > > set_pad_buffer "DONT USE" chip/reset > it seems that this not work. fpga express accepts the command and the description to the set_pad_buffer reports that this is the command i'm looking for. but nonetheless fpga express creates rst_BUFGPed for the rst signal. If i use fpga express in the gui, it does not assign a clock buffer to rst. Kai -- ----- Dipl. Ing. Kai Troester ------------------------------------- IMMS - Institut fuer Mikroelektronik- und Mechatronik-Systeme gGmbH Langewiesener Strasse 22, 98693 Ilmenau, Germany Tel: +49(3677)6783-42 Fax: +49(3677)6783-38 mailto:kai.troester@imms.de http://www.imms.de/~troester -------------------------------------------------------------------Article: 20388
Hi, wld. appeciate if anyone cld. point out to MP3 and Wavelet codec implemented on a FPGA...if any ? Thanks...... AK Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20389
I am using FPGA Compiler II, which is the same as FPGA Express (I believe). There does appear to be problems when using the shell mode. For example, when you assign a constraint (like set_input_delay), reassign it with a different value, and do a report_chip, the report will indicate the first value you assigned and use that first value for optimisation, completely ignoring the second. Pretty crap. I assume this is what is happening in your case. Perhaps the "AUTOMATIC" switch is applied to the set_pad_buffer command first, and when you use the "DONT USE" switch, the tool ignores it. The Synopsys online documentation and man pages for FE are rather useless also. Does anyone know where I can find decent documentation for FPGA Express? Pete. Kai Troester wrote: > > Pete Little wrote: > > > > Use the following, > > > > set_pad_buffer "DONT USE" chip/reset > > > > it seems that this not work. fpga express accepts the command and the > description to the set_pad_buffer reports that this is the command i'm > looking for. but nonetheless fpga express creates rst_BUFGPed for the > rst signal. > If i use fpga express in the gui, it does not assign a clock buffer to > rst. > > Kai > -- > ----- Dipl. Ing. Kai Troester ------------------------------------- > IMMS - Institut fuer Mikroelektronik- und Mechatronik-Systeme gGmbH > Langewiesener Strasse 22, 98693 Ilmenau, Germany > Tel: +49(3677)6783-42 > Fax: +49(3677)6783-38 > mailto:kai.troester@imms.de > http://www.imms.de/~troester > -------------------------------------------------------------------Article: 20390
If you do not need any reprogrammability, the Clear Logic CL81188A is functionally compatible with Altera's EPF81188A, at as little as half the price. You can visit our website at www.clear-logic.com for information on getting a price quote and for submitting your bitstream in order to obtain prototypes. Good luck, --Scott Chase Senior Applications Engineer, Clear Logic whitmoreg@my-deja.com wrote: > Does anyone know of a cheaper alternate that is functionally compatible > with the altera epf81188 series of fpga's. > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 20391
I'm about to start a design which will be my first PC Card (PCMCIA) design. I have a hunch that most laptops currently in use have 3.3v logic for thier PC Carc interface. Is this an incorrect assumption? I'd like to use an APEX part but since they are not 5v tolerant I'd have to use low voltage keying on the PC Card frame to prevent it from being used with a 5v system. I'm afraid I'd be designing myself of some systems if I do so. I'm guessing that 5v logic has pretty much vanished vanished from the world of laptops but I'm not sure. Anyone have any opinions? Thanks, John Schulte * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 20392
Larry Doolittle (ldoolitt@recycle) wrote:
: Tom Burgess (tom.burgess@hia.nrc.ca) wrote:
: : EDN mag, Jan 6th issue, p. 24 had some unattributed
: : Spartan-2 price projections:
: ^^^^^^^^^^^
: : XC2S15 3.95, XC2S30 4.95, XC2S50 7.95, XC2S100 9.95, XC2S150 12.95
: : The fine print states that this pricing is for 250,000 units, lowest
: : speed and cheapest package, end of 2000.
: I put up a web page to make searches for _real_ P&A easier:
: http://recycle.lbl.gov/xc2search.html
Avnet has had "Engineering Samples" of the XC2S100 and XC2S50
listed for a while, now they have prices for those.
For small quantities (less than 25), we have:
Avnet [1] Guess [2] Projection [3]
XC2S50 $58.55 $33 $7.95
XC2S100 $71.05 $46 $9.95
[1] Avnet Electronics Marketing on 8 February, http://www.em.avnet.com/
[2] My 28 January guess for minimum quantity
[3] Quoted in 6 January EDN for end of 2000, quantity 250,000,
slowest speed and cheapest package
In quantities greater than 98 (these are _samples_?), Avnet
lists $49.55 and $60.15. Avnet does not claim either of these
chips are in stock.
These prices are not very different from the Virtex line: onesies
of the XCV50 and XCV100 run $55.40 and $104.00, respectively.
It would be nice if we saw production chips on the shelves on or
before the end of the quarter (March 31), at prices that have
_some_ connection to those price projections quoted in EDN.
- Larry Doolittle <LRDoolittle@lbl.gov>
Article: 20393Hello all... I've been working with the Foundation Student Edition for a while now, and it's pretty good for what I want to do. However, I have an old design I did on paper a couple of years ago for an XC3030 device that I'd like to actually implement. The problem is that the Student Edition software doesn't appear to contain support for the older devices. Is there any way to implement my design in this older family without purchasing the entire full-blown Foundation package? Did Xilinx deliberately leave out support for the older families from the Student Edition in order to discourage their use? I could implement it in an XC4003, but last I checked, that part was not offered in the 44pin PLCC package. In fact, none of the XC4000 series parts were. Would there be any chance of an older version of XACT being available somewhere? (Assuming the dongle would still work after all these years...) Thanks in advance for any replies. -EwanArticle: 20394
"Tanthanuch.SAWIT" wrote: > Dear all > If we found these errors in XC4020E, how can I do? > I have already install .BSDL file of XC4020E. > > ERROR:basut - Boundary-scan chain test failed at bit position '1' on > instance 'mult_c(Device1)'. > Check that the cable, system and device JTAG TAP connections are > correct, > that the target system power supply is set to the correct level, > that the system grounds are connected and that the parts are properly > decoupled. > ERROR:basut - Boundary scan chain has been improperly specified. Please > check your configuration and re-enter the boundary-scan chain > information. > Boundary-scan chain validated unsuccessfully. > ERROR:basut - : The boundary-scan chain has not been declared correctly. > > Verify the syntax and correctness of the device BSDL files, correct the > files, > reset the cable and retry this command. > > Please suggest me. > Best Regard > Wannarat Dear All , I put attemption again and it' still out of order with following : ----------------------------------------------- JTAG Programmer Started 2000/02/09 03:18:10 Loading Boundary-Scan Description Language (BSDL) file 'C:/fndtn/data/xc4020e_hq208.bsd'.....completed successfully. Checking boundary-scan chain integrity...ERROR:basut - Boundary-scan chain test failed at bit position '2' on instance 'mult_c(Device1)'. Check that the cable, system and device JTAG TAP connections are correct, that the boundary-scan chain configuration specified matches the actual hardware, that the target system power supply is set to the correct level, that the system grounds are connected and that the parts are properly decoupled. ERROR:basut - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:basut - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. Have you any suggestions ? BST regradsArticle: 20395
Larry Doolittle wrote: > Larry Doolittle (ldoolitt@recycle) wrote: > :It would be nice if we saw production chips on the shelves on or > before the end of the quarter (March 31), at prices that have > _some_ connection to those price projections quoted in EDN. > > Spartan family devices are meant for the high-volume consumer-like market, and thus they are priced very low for purchases in very high volume, typical for consumer products. That may explain the large ratio between today's <100-piece prices and the projected very-high volume prices at the end of 2000. The high-volume consumer market is inherently different from our traditional modest-volume industrial and telecom market. That's why we created two different FPGA families, Virtex and Spartan, each meant to serve its market. Peter AlfkeArticle: 20396
Paul Butler wrote: > > Rickman <spamgoeshere4@yahoo.com> wrote in message > news:389F9EB6.64EF6B07@yahoo.com... > > First I would like to point out that FPGA Express is perfectly capable > > of removing FFs. I tried to do a one hot FSM and found that I only got > > 15 FFs in a 16 state design. The IDLE state was being coded as no FFs > > set. > > To detect being in the IDLE state, there must have been logic to detect that > the FSM is not in any other state. That doesn't sound like a one-hot state > machine to me. I guess that was related to your other problem: No, even when I got the state decoding to work efficiently, the FSM was still removing one FF from the one hot FSM. I don't remember the details now since it was over a year ago. But I do remember that I could not get the synthesizer to give me all 16 FFs. > > Again in > > the one hot FSM, I found it very difficult to find the exact coding > > style that would prevent the synthesizer from decoding all 15 FSM > > variables (FF outputs) as the inputs to all 15 variables. Kinda defeated > > the purpose of one hot encoding. In general I always had to play with > > the code to get a good implementation of any logic. > > Could you tell us what coding style didn't work and what you finally settled > on? FPGA Express has a setting to control the interpretation of "others" in > one-hot state machines. How did that switch affect your result? At the time I was having these problems I made many posts to this newsgroup. I also bugged the heck out of the Xilinx hot line. I got to be on a first name basis with several of the engineers. At this point I am not looking for help with this. I am just relating my experience with HDL tools. I don't have a problem using schematics, although I do miss using testbenches. The simulation tools for schematic entry are not nearly as useful. When I get more free time and fewer deadlines, I plan to explore using testbenches with schematics under the Viewlogic toolset. > My usual template for a FSM is one process containing nothing but a case > statement that switches on the current state and drives the "next state" > signal. A second process infers registers on the "current state" signal. > That seems to work pretty well and I haven't experimented much with other > styles. That is what I had to end up with as well. But you also have to be very carful about how you structure your code within each case. I did not save any of the bad code other than in the zip files I sent to Xilinx. I don't really feel like pulling this stuff out of the attic at this point. My main point is that because you have to tailor the code to your synthesis engine, the code is not easily written or ported to other tools. It is not like C code where a program written by a second year software engineer runs as well on a PC as it does on a Sun. Of course others with more experience than I have may well know how to write very portable code. But I don't have the time to learn from the school of hard knocks. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 20397
In article <87pp2c$guf3@overload.lbl.gov>, ldoolitt@recycle (Larry Doolittle) wrote: > Larry Doolittle (ldoolitt@recycle) wrote: > : Tom Burgess (tom.burgess@hia.nrc.ca) wrote: > : : EDN mag, Jan 6th issue, p. 24 had some unattributed > : : Spartan-2 price projections: > : ^^^^^^^^^^^ > : : XC2S15 3.95, XC2S30 4.95, XC2S50 7.95, XC2S100 9.95, XC2S150 12.95 > : : The fine print states that this pricing is for 250,000 units, lowest > : : speed and cheapest package, end of 2000. > > : I put up a web page to make searches for _real_ P&A easier: > : http://recycle.lbl.gov/xc2search.html > > Avnet has had "Engineering Samples" of the XC2S100 and XC2S50 > listed for a while, now they have prices for those. > > For small quantities (less than 25), we have: > Avnet [1] Guess [2] Projection [3] > XC2S50 $58.55 $33 $7.95 > XC2S100 $71.05 $46 $9.95 > > [1] Avnet Electronics Marketing on 8 February, http://www.em.avnet.com/ > [2] My 28 January guess for minimum quantity > [3] Quoted in 6 January EDN for end of 2000, quantity 250,000, > slowest speed and cheapest package > > In quantities greater than 98 (these are _samples_?), Avnet > lists $49.55 and $60.15. Avnet does not claim either of these > chips are in stock. > > These prices are not very different from the Virtex line: onesies > of the XCV50 and XCV100 run $55.40 and $104.00, respectively. > It would be nice if we saw production chips on the shelves on or > before the end of the quarter (March 31), at prices that have > _some_ connection to those price projections quoted in EDN. > > - Larry Doolittle <LRDoolittle@lbl.gov> > BTW folks, It seems to me that the cost of the configuration memory has to be part of the equation. For example, FPGA prices are plummeting, but serial PROM prices are coasting along nicely. Pretty soon we'll be paying more for the PROM than the FPGA. If you happen to be using parallel memory (FLASH or EPROM) to store configuration data, then you will be in for a very nasty surprise the next time you try to buy some. Manufacturers and distributors are throwing negotiated prices out the window, and are taking advantage of the memory shortage situation. Food for thought... -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20398
Peter Alfke (peter@xilinx.com) wrote:
: Larry Doolittle wrote:
: > Larry Doolittle (ldoolitt@recycle) wrote:
: > :It would be nice if we saw production chips on the shelves on or
: > before the end of the quarter (March 31), at prices that have
: > _some_ connection to those price projections quoted in EDN.
: Spartan family devices are meant for the high-volume consumer-like market,
: and thus they are priced very low for purchases in very high volume,
: typical for consumer products.
: That may explain the large ratio between today's <100-piece prices and the
: projected very-high volume prices at the end of 2000.
: The high-volume consumer market is inherently different from our
: traditional modest-volume industrial and telecom market. That's why we
: created two different FPGA families, Virtex and Spartan, each meant to
: serve its market.
I'm not sure you can define and differentiate "consumer", "industrial",
and "telecom" in a way that holds water in the age of networked markets.
Especially since "consumer" technologies have to be developed and tested
in small quantities on a real life workbench, just like everything else.
See http://www.cluetrain.com/ . Peter, take special note of #84. :-)
- Larry Doolittle <LRDoolittle@lbl.gov>
Article: 20399
Greg Neff (gregneff@my-deja.com) wrote:
: BTW folks, It seems to me that the cost of the configuration memory has
: to be part of the equation. For example, FPGA prices are plummeting,
: but serial PROM prices are coasting along nicely. Pretty soon we'll be
: paying more for the PROM than the FPGA.
I have ignored that part of the equation, mostly because my
applications involve configuring the FPGA from a computer.
The configuration comes from a hard disk via Ethernet.
: If you happen to be using parallel memory (FLASH or EPROM) to store
: configuration data, then you will be in for a very nasty surprise the
: next time you try to buy some. Manufacturers and distributors are
: throwing negotiated prices out the window, and are taking advantage of
: the memory shortage situation.
I have heard similar remarks from others. Too many people are
buying digital cameras. :*)
- Larry Doolittle <LRDoolittle@lbl.gov>
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