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Messages from 22525

Article: 22525
Subject: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
From: Ray Andraka <ray@andraka.com>
Date: Thu, 11 May 2000 01:23:26 GMT
Links: << >>  << T >>  << A >>
I'm not sure the Quartus fitter will use the cliques.  The "Quartus" fitter in
Maxplus 9.5 ignores cliques and requires timing constraints to get a good P&R.

The clock skew should not be that bad unless you are not using the global clock
pins.

Don McCarley wrote:

> It is not on extra effort; I don't know about assigning a clique? to a block?;
> my setup and clock->out's are constrained; I will look into the Assignment
> Dis-Organizer settings; I specified the clock (not global).  I did find one
> thing, if I do a context help on the error, it tells me I need to add lcells to
> increase data delay to the 7 problem paths, so next I will try to figure out how
> to do this.  Thanks.
>
> Don
>
> Xanatos wrote:
>
> > > I am a novice user of the Altera software and I am stuck with a design
> > that
> > > I run through Quartus 2000.03 and I get an error during compilation: clock
> > > skew is greater then data delay, ciruit will not function.  If this is
> >
> > Is this on extra effort? Did you try to assign a clique to a block? Are your
> > setup/hold times set? Check to ensure that the settings in the Assignment
> > Dis-Organizer are configured properly for your design.
> > Also, did you specify a global clock, or did you "specify" the clock?
> >
> > Check that, and if it still gives you grief, let me know.
> >
> > Cheers,
> > Xanatos

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22526
Subject: Re: EETools Topmax
From: krw@ibm.net (Keith R. Williams)
Date: 11 May 2000 03:46:46 GMT
Links: << >>  << T >>  << A >>
On Tue, 9 May 2000 21:41:50, Long <lbhoang@yahoo.com> wrote:

> Anyone have any experience with the EETools Topmax universal device 
> programmer? 

I have the cheaper EETools ChipMax, so my experience may not be 
directly transferrable to the TopMax.  My needs arn't complicated, but
I'm not impressed at all!  The software is impossible to use and so 
buggy that I'm about to throw the thing away.  If I push the wrong 
Win-buttons it will hang with the system speaker screaming.  The thing
also seems to fail diagnostics, but it programs devices anyway.  It's 
cheap, but I believe there is a reason. Anyway, Yuck!

> BP Micro BP-1400 $8995, very good device support, pin driver (doesn't 
> require family modules), supports devices down to 2.7V, frequent and 
> recent software updates, nearly fell out of my chair when they replied to 
> my email with the price quote (yes, that's $8995), local company

That must be a production tool.  BP Micro also has a $1500 programmer.
 I had one of theirs in a previous assignment and it was first-rate. 
If I can convince management to spend the $1500 the ChipMax is going 
in the garbage.

Again, my experience with the cheaper ChipMax may, or may not, be 
revelant to the TopMax.

Also look at DataIO. I believe they have some reasonably priced lab 
programmers, though they are more expensive than BPMicro.

----
  Keith
Article: 22527
Subject: Re: Xilinx Student Edition 1.5 License.dat
From: "R. T. Finch" <robfinch@cyg.net>
Date: Thu, 11 May 2000 01:58:29 -0400
Links: << >>  << T >>  << A >>
Thanks for all the help.

I think I figured it out. The install adds "C:\fndtn\bin\nt" to the PATH.
This caused my path to exceed 128 chars, causing the path setting to be
ignored. So i guess the license checker didn't work properly.
I shortened the PATH and things *seem* to work now. (Of course now the other
stuff on my machine that needs to be in the PATH doesn't work.)
You'd think they'd have figured out not to use the PATH by now to get
working applications.

Rob

"R. T. Finch" <robfinch@cyg.net> wrote in message
news:NQ3S4.67488$VR.1345263@news5.giganews.com...
> I have the following problem trying to run synthesis:
>
> FPGA Express Macro Compiler
> Version 3.1.1.0w
>
> Initialize DPM...
>
> Checking license...
>
> Checking license for Synopsys failed.
>
>
> I received and set up a license.dat file according to the supplied
> instructions, but apparantly it doesn't work. I am using the license.dat
> file (verbatium) as e-mailed to me by the online registration. For some
> reason they emailed me two attachments, one with linefeeds and one
without.
> neither works.
>
> Since Xilinx does not offer live support I am unable to contact them, and
I
> am unable to make use of their software. This is very aggravating. None of
> the problems in their FAQ or database provide a resolution to this
problem.
>
> Please help.
>
> Thanx
> Rob
>
>
>


Article: 22528
Subject: alexander decoder
From: Emil Blaschek <emil.blaschek@siemens.at>
Date: Thu, 11 May 2000 08:03:12 +0200
Links: << >>  << T >>  << A >>
Because of the manny requests , abriefe description of the alexander
decoder: 
A alexander decoder takes 3 samples of an incomming bit.
in the best situation the samples are taken at phi(60) ,phi(180) and
phi(300) degree,
while the bit changes at 0 degree.
In the locked condition the bit would change between phi(300) and
phi(60).
So all three samples of a bit are ident.
if the bit changes eg. at phi(90) then Sample phi(60) and phi(300) are
different and the recieving clock is too late -> so the VCO has to be
tuned up.
if the bit changes eg. at phi(290) then Sample phi(300) and phi(180) are
different and the recieving clock is too early -> so the VCO has to be
tuned down.
The sample at phi(180) is always taken for the data.

If you have no VCO so you should have a fixed frequency and you must 
shift the samples to get the correct pload by a functional block 
called alligner.

with best regards 
DI(TU) E.Blaschek  
Program and System Engeneering PROdukts 
Logik and Modelling of Systems 2
PSE PRO LMS2
Siemens AG Austria 



( Angle goes from 0 to 306 degree)
Article: 22529
Subject: Re: Xilinx Foundation PAR hangs
From: Cory <>
Date: Wed, 10 May 2000 23:06:10 -0700
Links: << >>  << T >>  << A >>
If you have not all ready, try the latest service pack for the 1.5 version of the software.  The service packs can be found on the support.xilinx.com website.  I had a customer with a similar issue using 1.5 and the first example.

Regards,
Cory, Xilinx CAE

Article: 22530
Subject: Re: Xilinx Student Edition 1.5 License.dat
From: Jon Kirwan <jkirwan@easystreet.com>
Date: Wed, 10 May 2000 23:36:03 -0700
Links: << >>  << T >>  << A >>
On Thu, 11 May 2000 01:58:29 -0400, "R. T. Finch" <robfinch@cyg.net>
wrote:

>Thanks for all the help.
>
>I think I figured it out. The install adds "C:\fndtn\bin\nt" to the PATH.
>This caused my path to exceed 128 chars, causing the path setting to be
>ignored. So i guess the license checker didn't work properly.
>I shortened the PATH and things *seem* to work now. (Of course now the other
>stuff on my machine that needs to be in the PATH doesn't work.)
>You'd think they'd have figured out not to use the PATH by now to get
>working applications.

I first tried to install it to my "C:\Program Files\" directory,
typing in C:\progra~1\fndtn as the installation directory.

Bad, bad news.  Some of the entries in my registry were for
"C:\progra~1\fndtn" and some were for "C:\Program Files\fndtn" which
caused the tools to croak.  Some of them apparently cannot handle long
filenames, perhaps all of them.  Hard to be sure, since the registry
entries were some of one and some of another.  So I removed everything
and reinstalled the batch all over again.

I felt that if I used the short 8.3 names for the installation
directory, that things would work out okay.  But I suppose some of the
API calls they used returned the long filename directory names, which
their installation software occasionally picked up and used, instead
of the names I gave.  Oh, well.

The tools either need an explicit statement placed during installation
that carefully says "stay clear of anything that even has a hint of
VFAT in it" or else they should get all the tool folks to fix their
acts.  I suppose part of the problem is that there are too many hands
in the kitchen, though.

Jon
Article: 22531
Subject: Re: pipeline shiftreg in virtex
From: William LenihanIii <lenihan3we@earthlink.net>
Date: Thu, 11 May 2000 07:04:07 GMT
Links: << >>  << T >>  << A >>
Rick has given a good clarification of why I want the shift reg 'distributed' in
regular CLB/Slice registers across the chip (as opposed to the 'efficient' way of
implementing them in the SRL16's that would be most appropriate in 99% of
applications).

Since I posted this message, I've discovered that

(a) the reset solution works quite well (but does need careful documentation in
the HDL code to explain why I need a reset that I'm not really using except to
bring to a dummy I/O pin or uP port) and

(b) more recent versions (3.4 just released) of my synthesis tool, Synopsys FPGA
Compiler II, has a feature called "retiming", which will take some existing
combinatorial datapath + registers, and redistribute the registers in/around the
combinatorial logic to balance the timing in all sections of the pipeline -- this
solution also works just fine, except that the catch is that you must have SOME
combinatorial logic in the path, a pure shift register doesn't cause the retiming
to occur. Fortunately, my datapath had a mux picking between 2 data sources and
that was all I needed.

Thanks to all who responded.


Rickman wrote:

> William is trying to use multiple registers across the chip so that the
> delay between each of them is very small. This will allow him to use a
> very high clock rate. The LUT implementation puts all of the registers
> in one spot so that it only cuts the travel time in half at best.
>
> This is one of the many problems with using an HDL to synthesize a
> design. You spend less time describing a design at the logical level,
> but you then spend more time getting the implementation you really want
> (assuming you need tight control). In many designs you really don't need
> to specify the exact implementation since it is not important or the
> tools do a good job. In other cases, the tools have a very hard time
> giving you what you really need.
>
> In this case William has been told that if he specifies the reset
> behaviour, he will get the separate registers which he can then place
> where he wants them. But the reset code then needs to be documented as
> an implementation control so that a future designer does not take it out
> and break the design.
>
> Gary Spivey wrote:
> >
> > Ok,
> >   I'll bite - I am missing something here. While all of this information is
> > quite useful (Thank you Ray), what is the real issue? You said that they
> > need to act as pipeline registers to help break up the long travel time
> > across the chip. Doesn't the LUT implementation do that? The signals are
> > being registered ... correct? So obviously I am missing something. Please
> > clue me in ...
> >
> > Cheers,
> > Gary
> > spivey@ieee.org
> >
> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:39192201.728B434A@andraka.com...
> > > Synplify infers the SRL16 or SRL16e if there is no reset term.  These, as
> > > you know, use the LUT as a 16 bit shift register in the VIrtex devices.
> > > Put a reset term on the shift register to keep it out of the LUT.  If you
> > > don't use the reset term, connect it to a dummy signal and keep that from
> > > getting optimized out in synthesis by putting a syn_keep attribute on the
> > > dummy signal.
> > >
> > >
> > >
> > > William LenihanIii wrote:
> > >
> > > > I have some shift registers in a Xilinx Virtex design and between the
> > > > synthesis tool (FPGA Compiler II) and the Xilinx Alliance P&R (2.1i), it
> > > > is placing these shift registers inside the Look-up tables, not in the
> > > > 'regular' registers in the slices/CLBs -- which is where I need them
> > > > since they are acting as pipeline registers to help break up the long
> > > > travel time from one side of the chip to the other -- and forcing them
> > > > inside a "SRL16" of one CLB isn't going to do that.
> > > >
> > > > Is there a way of coaxing the synthesis and/or P&R tool to put shift
> > > > registers in a resource of the designers' choosing (without manual
> > > > instantiation of SRL16's vs. FDCE's)?
> > > >
> > > > --
> > > > ========================
> > > > William Lenihan
> > > > lenihan3we@earthlink.net
> > > > ========================
> > >
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
========================
William Lenihan
lenihan3we@earthlink.net
========================


Article: 22532
Subject: Re: appropriate ASIC Prototyping Board
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Thu, 11 May 2000 10:02:11 +0200
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
 
> OK, I'll bite:   If you are doing a PCI based network interface in an ASIC, wouldn't you
> want control over the PCI interface design too?  
Yes, of course! But there is a difference between designing a whole PCI interface including the PCI
protocol and PCI timing and using a predefined interface, like the PCI LogiCORE or the PCI
DesignWare from Synopsys (for the later ASIC).
The PCI core is in fact a problem when transferring the FPGA design to an ASIC. I don't know a good
solution till now.

> As far as the Dini Board goes, I'm using one for a current project.  Its pretty good for
> what it is supposed to be: an ASIC prototyping platform.  
As I may ask, whats the gate count of your targeted ASIC and how many FPGAs are on the Dini-Board?


Thanks for your comments

Patrick

-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713
Article: 22533
Subject: Re: appropriate ASIC Prototyping Board
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Thu, 11 May 2000 11:18:21 +0200
Links: << >>  << T >>  << A >>
Anna Acevedo wrote:
> 
> Take a look at the following:
> 
> http://www.embedded-solutions.ltd.uk/tech_info_3.htm
With this board the problem is that I have no control over the PCI core as it is not
located on the FPGA and that we think about a 64bit/66MHz version.

> http://www.annapmicro.com/
They don't have a VIRTEX1000(e)-board.
> 
> http://www.associatedpro.com/
It seems that they don't have any PCI-Boards :-(
> 
> http://www.vcc.com/prod1.html
On this board the FPGA is too small. It should be a VIRTEX1000(E)

Anyhow, do you have some more ideas??


Thanks for your comments.
Patrick
-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713
Article: 22534
Subject: Shifting with STD_LOGIC_VECTOR???
From: "MK Yap" <mkyap@REMOVE.ieee.org>
Date: Thu, 11 May 2000 18:19:04 +0800
Links: << >>  << T >>  << A >>
Hi,

I realized that shifting using sll, ror..... etc can only be done using
bit_vector...
what can i do so that my input and output port can be changed to
std_logic_vector to reflect real situation????

Any help is appreciated??
MK

**********
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY test IS
 PORT(
  nReset   : in STD_LOGIC;
  BClk   : in STD_LOGIC;
  DataI   : in bit_VECTOR (15 DOWNTO 0);
  DataO   : out bit_VECTOR(15 downto 0)
  );
END test;

ARCHITECTURE p2s OF test IS
BEGIN
 fedge: PROCESS(nReset,BClk)
 VARIABLE tmp : integer range 0 to 7;
 BEGIN
  IF nReset='0' THEN
   DataO <=(OTHERS=>'0');
   tmp:=0;
  ELSIF BClk'event AND BClk='0' THEN
   tmp:=4;
   DataO <= DataI sll tmp;
  END IF;
 END PROCESS fedge;
END p2s;


Article: 22535
Subject: FPGA emulators?
From: Steven Sanders <sanders@imec.be>
Date: Thu, 11 May 2000 13:51:32 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0A6168B11B5BF4531C8C9160
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello,

I was wondering if there exists something like a FPGA-emulator, where
you run your VHDL-code real-time in the hardware (via a POD) and you can
check signals, variables...or set brakepoints, tracepoints.... . The
VHDL of course is NOT synthesized, just compiled (like in ModelSIM).

Thanx

Steven


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Content-Transfer-Encoding: 7bit
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n:              Sanders;Steven
org:            imec vzw
adr:            Flanders Language Valley 44;;;Ieper;W.-Vl.;8900;Belgium
email;internet: sanders@imec.be
tel;work:       057 230 140
tel;fax:        057 230 164
tel;home:       059 298 862 
note:           cellular: +32 76 582 612
x-mozilla-cpt:  ;0
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version:        2.1
end:            vcard


--------------0A6168B11B5BF4531C8C9160--

Article: 22536
Subject: Re: Shifting with STD_LOGIC_VECTOR???
From: Alan Fitch <alan.fitch@doulos.com>
Date: Thu, 11 May 2000 12:52:16 +0100
Links: << >>  << T >>  << A >>
In article <391a8741.0@news.cyberway.com.sg>, MK Yap
<mkyap@REMOVE.ieee.org> writes
>Hi,
>
>I realized that shifting using sll, ror..... etc can only be done using
>bit_vector...
>what can i do so that my input and output port can be changed to
>std_logic_vector to reflect real situation????
>
>Any help is appreciated??
>MK
>
>**********
>LIBRARY ieee ;
>USE ieee.std_logic_1164.all;
>--USE ieee.std_logic_arith.all;
>USE ieee.numeric_std.all;
>
>ENTITY test IS
> PORT(
>  nReset   : in STD_LOGIC;
>  BClk   : in STD_LOGIC;
>  DataI   : in bit_VECTOR (15 DOWNTO 0);
>  DataO   : out bit_VECTOR(15 downto 0)
>  );
>END test;
>
>ARCHITECTURE p2s OF test IS
>BEGIN
> fedge: PROCESS(nReset,BClk)
> VARIABLE tmp : integer range 0 to 7;
> BEGIN
>  IF nReset='0' THEN
>   DataO <=(OTHERS=>'0');
>   tmp:=0;
>  ELSIF BClk'event AND BClk='0' THEN
>   tmp:=4;
>   DataO <= DataI sll tmp;
>  END IF;
> END PROCESS fedge;
>END p2s;
>
>

There's two ways - a) use "array type conversion" to produce the correct
types, e.g. if you use std_logic_vector on your ports DataI and DataO,
you can say

DataO <= STD_LOGIC_VECTOR( UNSIGNED(DataI) sll tmp);


Or just give up on the VHDL93 operators and do it by hand

DataO <= DataI(tmp-1 downto 0) & DataI(15 downto tmp);

Though what I've written there won't work when tmp=0.

In the second case, you don't need numeric_std with your code above.

regards

Alan


-- 
Alan Fitch
DOULOS Ltd. 
        Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK
Tel: +44 (0)1425 471 223                    Email: alan.fitch@doulos.com
Fax: +44 (0)1425 471 573             
**               Visit THE WINNING EDGE  www.doulos.com               **

Article: 22537
Subject: Re: FPGA emulators?
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Thu, 11 May 2000 14:05:05 +0200
Links: << >>  << T >>  << A >>
Steven Sanders a écrit :
> 
> Hello,
> 
> I was wondering if there exists something like a FPGA-emulator, where
> you run your VHDL-code real-time in the hardware (via a POD) and you
> can check signals, variables...or set brakepoints, tracepoints.... .
> The VHDL of course is NOT synthesized, just compiled (like in
> ModelSIM).

I don't see the point. What's the difference with simulation?

-- 
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 22538
Subject: Re: FPGA emulators?
From: Laurent Gauch <laurent.gauch@aps-euro.com>
Date: Thu, 11 May 2000 08:23:30 -0400
Links: << >>  << T >>  << A >>
Hi Steven,

I don't understand your question !
Your simulateur (maybe for your ModelSim) IS the FPGA-emulator (but I don't
like the word 'emulator' in this case).
You cannot find a emulator of a emulator, because the FPGA is for me the
greater emulor I know.
In a FPGA you can emulate MPUs, MCUs, ... etc , or a vending machine !

Have a sunny day !
Laurent


Steven Sanders a écrit :

> Hello,
>
> I was wondering if there exists something like a FPGA-emulator, where
> you run your VHDL-code real-time in the hardware (via a POD) and you can
> check signals, variables...or set brakepoints, tracepoints.... . The
> VHDL of course is NOT synthesized, just compiled (like in ModelSIM).
>
> Thanx
>
> Steven

Article: 22539
Subject: Re: Shifting with STD_LOGIC_VECTOR???
From: Laurent Gauch <laurent.gauch@aps-euro.com>
Date: Thu, 11 May 2000 08:35:56 -0400
Links: << >>  << T >>  << A >>
Mebay don't use sll function, but

  DataO <= DataI(14 downto 0) & '0' ;
or
  DataO <= DataI(11 downto 0) & "0000" ;  --  for your tmp:=4;

in this example: for DataO and DataI with a 16 bits width.

Laurent
www.aps-euro.com



MK Yap a écrit :

> Hi,
>
> I realized that shifting using sll, ror..... etc can only be done using
> bit_vector...
> what can i do so that my input and output port can be changed to
> std_logic_vector to reflect real situation????
>
> Any help is appreciated??
> MK
>
> **********
> LIBRARY ieee ;
> USE ieee.std_logic_1164.all;
> --USE ieee.std_logic_arith.all;
> USE ieee.numeric_std.all;
>
> ENTITY test IS
>  PORT(
>   nReset   : in STD_LOGIC;
>   BClk   : in STD_LOGIC;
>   DataI   : in bit_VECTOR (15 DOWNTO 0);
>   DataO   : out bit_VECTOR(15 downto 0)
>   );
> END test;
>
> ARCHITECTURE p2s OF test IS
> BEGIN
>  fedge: PROCESS(nReset,BClk)
>  VARIABLE tmp : integer range 0 to 7;
>  BEGIN
>   IF nReset='0' THEN
>    DataO <=(OTHERS=>'0');
>    tmp:=0;
>   ELSIF BClk'event AND BClk='0' THEN
>    tmp:=4;
>    DataO <= DataI sll tmp;
>   END IF;
>  END PROCESS fedge;
> END p2s;

Article: 22540
Subject: Re: FPGA emulators?
From: Steven Sanders <sanders@imec.be>
Date: Thu, 11 May 2000 15:07:34 +0200
Links: << >>  << T >>  << A >>
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The difference is that you can see how the hardware connected to the FPGA
really responds.
Of course I can use a testbench of the other hardware (if available in the
first place) and simulate but
then I still will not be sure if the other hardware will respond that way.
The clue is that there is a real-time
time connection with the surrounding hardware and your code responding to
it.

Of course, this is the NOT the same as synthesizing and placing, because:
1) I want to check internal signals and variables (outputting them via pins
is waste of pins and time)
2) I don`t want to lose time with synthesis and place&route and logic
analyser setup.

Just write the code, insert your POD and see how it all REALLY responds.

Nicolas Matringe wrote:

> Steven Sanders a écrit :
> >
> > Hello,
> >
> > I was wondering if there exists something like a FPGA-emulator, where
> > you run your VHDL-code real-time in the hardware (via a POD) and you
> > can check signals, variables...or set brakepoints, tracepoints.... .
> > The VHDL of course is NOT synthesized, just compiled (like in
> > ModelSIM).
>
> I don't see the point. What's the difference with simulation?
>
> --
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE

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Article: 22541
Subject: Re: EETools Topmax
From: Kenneth Casselman <ken.casselman@home.com>
Date: Thu, 11 May 2000 13:43:11 GMT
Links: << >>  << T >>  << A >>
Keith R. Williams wrote:
 
(snip) 

> > BP Micro BP-1400 $8995, very good device support, pin driver (doesn't
> > require family modules), supports devices down to 2.7V, frequent and
> > recent software updates, nearly fell out of my chair when they replied to
> > my email with the price quote (yes, that's $8995), local company
> 
> That must be a production tool.  BP Micro also has a $1500 programmer.
>  I had one of theirs in a previous assignment and it was first-rate.
> If I can convince management to spend the $1500 the ChipMax is going
> in the garbage.
> 

 (snip)

I have been using a BP1148 from BP Microsystems Inc. for a couple of
years now, and I have found it to be completely reliable. This is their
entry level machine. It provides good support for memory devices and
programmable logic, but is somewhat limited when it comes to micros
(OK for 8051 type parts, not so good when it comes to Motorola or PIC
parts - check the device support list on their web site). If you can
afford it, you're probably better going with the BP1200 (the 1148 can
be upgraded to a 1200 if you want to go that route). BP are a bit
expensive (the Canadian dollar ain't worth what it used to be), but I
think you get what you pay for.  Rugged, reliable, free software
upgrades...

Oh yes, software.  I waited a long time for BP to release the Windows
version of their software, but now that it's available, I find I prefer
the DOS version (maybe I just got used to it).

Ken
Article: 22542
Subject: Re: appropriate ASIC Prototyping Board
From: Ray Andraka <ray@andraka.com>
Date: Thu, 11 May 2000 14:44:02 GMT
Links: << >>  << T >>  << A >>


Patrick Schulz wrote:

> Ray Andraka wrote:
>
> > OK, I'll bite:   If you are doing a PCI based network interface in an ASIC, wouldn't you
> > want control over the PCI interface design too?
> Yes, of course! But there is a difference between designing a whole PCI interface including the PCI
> protocol and PCI timing and using a predefined interface, like the PCI LogiCORE or the PCI
> DesignWare from Synopsys (for the later ASIC).
> The PCI core is in fact a problem when transferring the FPGA design to an ASIC. I don't know a good
> solution till now.

Be careful there guy!  The backend interfaces to various PCI cores is different, and if you are using
an ASIC PCI core, then that interface is where you are likely to have your problems.  Can you put the
ASIC PCI core in your emulated design --I think what your really want to verify is that back end
interface, assuming the core is already verified.

>
>
> > As far as the Dini Board goes, I'm using one for a current project.  Its pretty good for
> > what it is supposed to be: an ASIC prototyping platform.
> As I may ask, whats the gate count of your targeted ASIC and how many FPGAs are on the Dini-Board?
>

The one I'm working on has six XCV1000-4's on it, which I believe are the BGA560 packages.  Right now
it is in a proof of concept stage.  The design we have running on it is about 2 million gates.  The
limited interconnect between FPGAs has been  a problem, but you'll get that on any board.

>
> Thanks for your comments
>
> Patrick
>
> --
> Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
> University of Mannheim - Dep. of Computer Architecture
> 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
> Phone: +49-621-181-2720     Fax: +49-621-181-2713

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22543
Subject: Re: Info on using Reconfig feature of Virtex?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 11 May 2000 14:50:16 GMT
Links: << >>  << T >>  << A >>
The software really doesn't support partial reconfiguration right now.  You not
only have to control the placement, but you also need to control where the
routes are so that a) routes within the part of the design you want to leave
running are not ripped up or clobbered, b) the routes in the new partial
reconfiguration are completely contained within the columns you are configuring
and c) the I/Os of the reconfigured part connect to the sockets in the
previously configured part.

Right now, the only options you have are to either do the place and route in the
FPGA editor (EPIC), which will surely have the nice young men in the clean white
coats coming to take you away, or you can figure out how to do your design,
placement and routing in Jbits, which also is alot of work and requires intimate
knowledge of the chip (I'm not sure if there is enough info there to do a manual
route either).

Jim Patterson wrote:

> Where can I get some info on using the partial reconfiguration (while
> powered up) features of the Xilinx Virtex family.  I can't find much on
> their site.  I have read that floorplanning is key as the parts only do a
> column at a time.  I have never used the floorplanner.  Is it tough?  Design
> is in Verilog, using many RPM cores from coregen, including block RAM.
> Using the Foundation 2.1i.  Thanks.
>
> --
> Jim Patterson
> jpatters@stny.rr.com

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22544
Subject: Re: FPGA emulators?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 11 May 2000 14:54:59 GMT
Links: << >>  << T >>  << A >>
You can use the FPGA as the 'emulator' by taking advantage of reconfiguration
to get at test points, inserting special test pattern generators or analyzers
etc.  My paper from MAPLD two years ago discusses system debug and test using
the FPGAs in the system.  The paper, "An FPGA Based Processor Yields a Real
Time High Fidelity Radar Environment Simulator " is available on my website:
http://www.andraka.com/papers.htm

Laurent Gauch wrote:

> Hi Steven,
>
> I don't understand your question !
> Your simulateur (maybe for your ModelSim) IS the FPGA-emulator (but I don't
> like the word 'emulator' in this case).
> You cannot find a emulator of a emulator, because the FPGA is for me the
> greater emulor I know.
> In a FPGA you can emulate MPUs, MCUs, ... etc , or a vending machine !
>
> Have a sunny day !
> Laurent
>
> Steven Sanders a écrit :
>
> > Hello,
> >
> > I was wondering if there exists something like a FPGA-emulator, where
> > you run your VHDL-code real-time in the hardware (via a POD) and you can
> > check signals, variables...or set brakepoints, tracepoints.... . The
> > VHDL of course is NOT synthesized, just compiled (like in ModelSIM).
> >
> > Thanx
> >
> > Steven

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22545
Subject: Re: pipeline shiftreg in virtex
From: "Gary Spivey" <spivey@ieee.org>
Date: 11 May 2000 10:37:01 -0500
Links: << >>  << T >>  << A >>

Thanks a bunch,
   I knew I was missing something. I was viewing it as a multi-bit word
being registered in a LUT rather than in several flip-flops - so that
registering it in the LUT still did the registration. But what we are
looking at is one bit being registered multiple times (which is a hole lot
closer to the meaning of pipelined I admit). And now this makes a whole lot
more sense. I can take my dunce cap off now.

Thanks again,
Gary

"Rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3919B309.85A3C0CD@yahoo.com...
> William is trying to use multiple registers across the chip so that the
> delay between each of them is very small. This will allow him to use a
> very high clock rate. The LUT implementation puts all of the registers
> in one spot so that it only cuts the travel time in half at best.
>
> This is one of the many problems with using an HDL to synthesize a
> design. You spend less time describing a design at the logical level,
> but you then spend more time getting the implementation you really want
> (assuming you need tight control). In many designs you really don't need
> to specify the exact implementation since it is not important or the
> tools do a good job. In other cases, the tools have a very hard time
> giving you what you really need.
>
> In this case William has been told that if he specifies the reset
> behaviour, he will get the separate registers which he can then place
> where he wants them. But the reset code then needs to be documented as
> an implementation control so that a future designer does not take it out
> and break the design.
>
>
> Gary Spivey wrote:
> >
> > Ok,
> >   I'll bite - I am missing something here. While all of this information
is
> > quite useful (Thank you Ray), what is the real issue? You said that they
> > need to act as pipeline registers to help break up the long travel time
> > across the chip. Doesn't the LUT implementation do that? The signals are
> > being registered ... correct? So obviously I am missing something.
Please
> > clue me in ...
> >
> > Cheers,
> > Gary
> > spivey@ieee.org
> >
> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:39192201.728B434A@andraka.com...
> > > Synplify infers the SRL16 or SRL16e if there is no reset term.  These,
as
> > > you know, use the LUT as a 16 bit shift register in the VIrtex
devices.
> > > Put a reset term on the shift register to keep it out of the LUT.  If
you
> > > don't use the reset term, connect it to a dummy signal and keep that
from
> > > getting optimized out in synthesis by putting a syn_keep attribute on
the
> > > dummy signal.
> > >
> > >
> > >
> > > William LenihanIii wrote:
> > >
> > > > I have some shift registers in a Xilinx Virtex design and between
the
> > > > synthesis tool (FPGA Compiler II) and the Xilinx Alliance P&R
(2.1i), it
> > > > is placing these shift registers inside the Look-up tables, not in
the
> > > > 'regular' registers in the slices/CLBs -- which is where I need them
> > > > since they are acting as pipeline registers to help break up the
long
> > > > travel time from one side of the chip to the other -- and forcing
them
> > > > inside a "SRL16" of one CLB isn't going to do that.
> > > >
> > > > Is there a way of coaxing the synthesis and/or P&R tool to put shift
> > > > registers in a resource of the designers' choosing (without manual
> > > > instantiation of SRL16's vs. FDCE's)?
> > > >
> > > > --
> > > > ========================
> > > > William Lenihan
> > > > lenihan3we@earthlink.net
> > > > ========================
> > >
>
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
>
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com


Article: 22546
Subject: floorplanning
From: Vipan Kakkar <v.kakkar@its.tudelft.nl>
Date: Thu, 11 May 2000 17:47:30 +0200
Links: << >>  << T >>  << A >>
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I have a FIR filter description in VHDL (RTL). It has about 10 entities.
I would like to realize this FIR in FPGA (XC4000). (Xilinx)

My question is: Is it better to synthesize these entities seperately and
then copy these entities into a top level entity. If this approach is
OK. Then how should I copy these synthesized entities (blocks) into a
top level entity. Let me know the command.
Is it from the floorplanner window or what?



--
_______________________________________________________________________________
Vipan Kakkar (Research Assiatant)



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<html>
I have a FIR filter description in VHDL (RTL). It has about 10 entities.
I would like to realize this FIR in FPGA (XC4000). (Xilinx)
<p>My question is: Is it better to synthesize these entities seperately
and then copy these entities into a top level entity. If this approach
is OK. Then how should I copy these synthesized entities (blocks) into
a top level entity. Let me know the command.
<br>Is it from the floorplanner window or what?
<br>&nbsp;
<br>&nbsp;
<pre>--&nbsp;
_______________________________________________________________________________
Vipan Kakkar (Research Assiatant)</pre>
&nbsp;</html>

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Article: 22547
Subject: Re: FPGA emulators?
From: Anurag Tiwari <atiwari@cs.wright.edu>
Date: Thu, 11 May 2000 11:54:34 -0400
Links: << >>  << T >>  << A >>
The point is that if try to do the simulation using hardware the
simulation is speeded up whereas if you design is to large and you need
large amount of clk cycles to get to the result software simulation like
Model Sim could be very slow .

There are some hardware accelators for speeding up the simulation=20
I dont remeber the name but one might check them on net.

--Anurag

On Thu, 11 May 2000, Nicolas Matringe wrote:

> Date: Thu, 11 May 2000 14:05:05 +0200
> From: Nicolas Matringe <nicolas@dotcom.fr>
> Newsgroups: comp.arch.fpga
> Subject: Re: FPGA emulators?
>=20
> Steven Sanders a =E9crit :
> >=20
> > Hello,
> >=20
> > I was wondering if there exists something like a FPGA-emulator, where
> > you run your VHDL-code real-time in the hardware (via a POD) and you
> > can check signals, variables...or set brakepoints, tracepoints.... .
> > The VHDL of course is NOT synthesized, just compiled (like in
> > ModelSIM).
>=20
> I don't see the point. What's the difference with simulation?
>=20
> --=20
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE
>=20

Article: 22548
Subject: Re: SpartanXL driving 5V CMOS input
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 11 May 2000 09:36:38 -0700
Links: << >>  << T >>  << A >>
Don't forget: Every Xilinx output pin is always also an input pin, whether you want it or not.
The speed-up trick uses no additional device pin, since the 2-input AND gate is internal to the device.
You have to use a CLB to implement the AND function,
and you may remember that it is desirable to have a few extra ns of delay in this path, since that gives the output a chance to rise higher than just the input
threshold.

It's one of the nicest tricks I have ever seen. ( Idid not invent it, a European Xilinx FAE did ).

Peter Alfke, Xilinx Applications
======================================
Mark Harvey wrote:

> Peter,
>
> Thanks for the reply.
> Is the solution you describe the one that I have seen described in the Virtex Tech Topics 5volt.pdf file? It uses two device pins instead of just one, right?

Article: 22549
Subject: Re: SpartanXL driving 5V CMOS input
From: Greg Neff <gregneff@my-deja.com>
Date: Thu, 11 May 2000 18:33:23 GMT
Links: << >>  << T >>  << A >>
In article <391AE196.1BEF6300@xilinx.com>,
  peter.alfke@xilinx.com wrote:
> Don't forget: Every Xilinx output pin is always also an input pin,
whether you want it or not.
> The speed-up trick uses no additional device pin, since the 2-input
AND gate is internal to the device.
> You have to use a CLB to implement the AND function,
> and you may remember that it is desirable to have a few extra ns of
delay in this path, since that gives the output a chance to rise higher
than just the input
> threshold.
>
(snip)

Sounds very interesting.  Here is the complete link for those that may
have missed it:

http://www.xilinx.com/products/virtex/techtopic/5volt.pdf

I could have used this on a SpatanXL design I just finished.  In any
case, I can see where the delay in the AND gate loop could be a little
problematic.  Too little delay, and you don't get enough of a boost.
Too much delay, and you get a shelf at VOH (that will probably ring a
little bit) which is inside the CMOS input threshold range.

Has anyone actually done this and tried to correlate loop delay vs.
output waveshape?  If so, was any testing done to see how much this was
affected by temperature, or VCC variation?

I guess I'm trying to figure out how to characterize this sort of
combinational feedback mechanism, to determine a quantifiable,
reliable, and repeatable improvement in speed.  This will vary
depending on the variation in the output disable point.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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