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Messages from 23150

Article: 23150
Subject: Re: PWM
From: David Kessner <davidk@free-ip.com>
Date: Thu, 15 Jun 2000 13:19:08 -0600
Links: << >>  << T >>  << A >>
Ángel Gutiérrez wrote:
> I need the VHDL to make a PWN (12 bits)

http://www.free-ip.com.  Follow the links to the Free-LIB1 core.

David Kessner
davidk@free-ip.com
Article: 23151
Subject: 3.1i
From: erika_uk@my-deja.com
Date: Thu, 15 Jun 2000 21:36:21 GMT
Links: << >>  << T >>  << A >>
why the version 3.1i has been already issued ???????

In article <3947A8AB.925252AA@xilinx.com>,
  brian.philofsky@xilinx.com wrote:
> This is a multi-part message in MIME format.
> --------------356CEC21F8BB6615EE5A328C
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
>
> As far as I know, it is only availible in HTML at
> http://toolbox.xilinx.com/docsan/2_1i
>
> There is also the brand new 3.1i version at, you guessed it,
> http://toolbox.xilinx.com/docsan/3_1i
>
> Good luck.
>
> --  Brian
>
> Domagoj wrote:
>
> > Hi,
> >     I was looking there for a new library guide pdf, but couldn't
find it.
> > Is it available at all ??
> >
> > --
> >
> > -------------------------------------------
> > -             Domagoj              -
> > - Domagoj@engineer.com -
> > -------------------------------------------
> > Utku Ozcan <ozcan@netas.com.tr> wrote in message
> > news:394673E8.8C22A74B@netas.com.tr...
> > > > [snip]
> > > > 3. How to use the LUT as shift reg.
> > >
> > > Please look at SRL16 and SRL16E element in the Libraries Guide.
> > > For more info, Alliance or Foundation 2.1i Java-based document
> > > interface on http://support.xilinx.com and go to Software Manuals.
> > >
> > > Utku
> > >
> > > --
> > > I feel better than James Brown.
> > >
> > >
> > >
>
> --------------356CEC21F8BB6615EE5A328C
> Content-Type: text/x-vcard; charset=us-ascii;
>  name="brian.philofsky.vcf"
> Content-Transfer-Encoding: 7bit
> Content-Description: Card for Brian Philofsky
> Content-Disposition: attachment;
>  filename="brian.philofsky.vcf"
>
> begin:vcard
> n:Philofsky;Brian
> tel;work:1-800-255-7778
> x-mozilla-html:TRUE
> url:http://www.xilinx.com
> org:Xilinx, Inc.;Software Marketing
> adr:;;2100 Logic Dr.;San Jose;CA;95124;USA
> version:2.1
> email;internet:brianp@xilinx.com
> title:Technical Marketing Engineer
> fn:Brian Philofsky
> end:vcard
>
> --------------356CEC21F8BB6615EE5A328C--
>
>


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Article: 23152
Subject: Designing a narrowband bandpass filter to pass a tone (analog domain)
From: Nestor C. <nestor@ece.concordia.ca>
Date: Fri, 16 Jun 2000 00:43:01 -0400
Links: << >>  << T >>  << A >>
Greetings all designers.

I don't know if this is the appropriate newsgroup to obtain help for
my problem, but here goes.

Does anyone know a manufacturer producing very narrowband bandpass
filters (BPF), or resonator filters in the range 1.5MHz-1.6MHz, with a
center ideally at 1.5625MHz or 1.544MHz?  
I would like to pass a tone  centered at either one of these two
frequencies with at least a 35dB out-of-band rejection.

I have examined the possibility of designing my own BPF using the LC
elliptic design procedure, but the final result ends up being too
costly in terms of the required printed circuit board (PCB) area (even
for surface-mounted parts), the required number of individual
components, and the large deviation from the design spec due to
manufacturing tolerances.

I am desperately seeking a single component solution, if available, or
a different approach, in order to meet my goal.

I have tried "whomakesit.com", but without any success in locating a
manufacturer that could satisfy my needs.  Since it's possible I may
have overlooked one manufacturer in my searches, I was hoping to
obtain some suggestions from the contributors to these newsgroups, who
know more about analog design than I do.

Thanks in advance to all and any information that you can provide.

Regards,

Nestor


Article: 23153
Subject: Re: VHDL synthesis.
From: "Xilinx CAE Cory" <>
Date: Thu, 15 Jun 2000 21:44:26 -0700
Links: << >>  << T >>  << A >>
The "front end tools" take as input HDL code which is synthesized into a netlist.  The "back end tools" take as input a netlist which is converted into a bit file for download.

     Synplify's Synplicity is a "front end tool" that will take in VHDL or Verilog and synthesize it to create a netlist.  The netlist produced is then used in Foundation 2.1i or Alliance 3.1i/2.1i to create the bit file for download.

The Foundation 2.1i is a complete design package.  It contains the "front end tools" and the "back end tools", where as the Alliance 3.1i/2.1i toolset is strictly the "back end tools".
Article: 23154
Subject: Re: foundation
From: "Xilinx CAE Cory" <>
Date: Thu, 15 Jun 2000 21:57:29 -0700
Links: << >>  << T >>  << A >>
This may also be a license issue.  If a valid license is not set up, then the tools will not allow a report to be generated.  Make sure that the license file is set up correctly. 

Cory, Xilinx CAE
Article: 23155
Subject: Xilinx config over parallel port ?
From: sceloporus occidentalis <s_occidentalis@hotmail.com>
Date: Fri, 16 Jun 2000 06:22:24 GMT
Links: << >>  << T >>  << A >>
Looking to configure XC4000 series directly through PC parallel port,
ost likely in asynchronous parallel mode.  Am working it out but any
experience, schematics or ideas appreciated.  Thanks!

s_occidentalis@hotmail.com


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Article: 23156
Subject: Re: Designing a narrowband bandpass filter to pass a tone (analog
From: Dominique SZYMIK <szymik@nospam.univ-lille1.fr>
Date: Fri, 16 Jun 2000 08:45:00 +0200
Links: << >>  << T >>  << A >>


"Nestor C." wrote:
> 
---------- 
> Does anyone know a manufacturer producing very narrowband bandpass

how much narrow?

> filters (BPF), or resonator filters in the range 1.5MHz-1.6MHz, with a
> center ideally at 1.5625MHz or 1.544MHz?
> I would like to pass a tone  centered at either one of these two
> frequencies with at least a 35dB out-of-band rejection.

A PLL is a narrow single tone bandpass...

> I have examined the possibility of designing my own BPF using the LC
> elliptic design procedure, but the final result ends up being too
> costly in terms of the required printed circuit board (PCB) area (even
> for surface-mounted parts), the required number of individual
> components, and the large deviation from the design spec due to
> manufacturing tolerances.
> 
If you got the money you can get a custom ceramic filter designed.
(Murata) but it is not a one off solution.

Tell us: -3dB -35dB bandwidth you need, and it's a single tone out 
of noise you want to get out?

d.
Article: 23157
Subject: XC4005XL OTP?
From: "Brent" <Fun@work.net>
Date: Fri, 16 Jun 2000 00:36:28 -0700
Links: << >>  << T >>  << A >>
Greetings again, and thank you to those
who responded and answered my previous question.
This question I have, is that I am wondering if Xilinx in perticular
offers Fuse based versions of their XC4005XL FPGA, (which is
in an eval board that I am considering). I have noticed that Altera
and other companies offer a more extensive line of Fuse Based FPGA than what
I have found of Xilinx's. (Although, the only place I have been able to find
even Fuse based Xilinx FPGAs is on questlink.com ...)
Thank you all again.



Article: 23158
Subject: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
From: "Radboud Verberne" <machine@dds.nl>
Date: Fri, 16 Jun 2000 09:59:35 +0200
Links: << >>  << T >>  << A >>
>Does anyone know a manufacturer producing very narrowband bandpass
>filters (BPF), or resonator filters in the range 1.5MHz-1.6MHz, with a
>center ideally at 1.5625MHz or 1.544MHz?
>I would like to pass a tone  centered at either one of these two
>frequencies with at least a 35dB out-of-band rejection.


Just use a normal crystal! a the desired frequency. A crystal is very narrow
banded. At 10 Mhz the bandwidth is about 12 Khz. The bandwidth at 1,5/1,6
Mhz should be much smaller.

Regards Radboud


Article: 23159
Subject: Re: Xilinx config over parallel port ?
From: Leon Heller <leon_heller@hotmail.com>
Date: Fri, 16 Jun 2000 08:32:34 GMT
Links: << >>  << T >>  << A >>
In article <8ich2o$3i9$1@nnrp1.deja.com>,
  sceloporus occidentalis <s_occidentalis@hotmail.com> wrote:
> Looking to configure XC4000 series directly through PC parallel port,
> ost likely in asynchronous parallel mode.  Am working it out but any
> experience, schematics or ideas appreciated.  Thanks!

I use the Xilinx parallel cable to download the configuration directly
into a SpartanXL chip on a prototype board. You could simply put the
cable circuit (schematic on the Xilinx web site) on your board with a
parallel port connector.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


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Article: 23160
Subject: Re: VHDL synthesis.
From: Leon Heller <leon_heller@hotmail.com>
Date: Fri, 16 Jun 2000 08:42:01 GMT
Links: << >>  << T >>  << A >>
In article <##RhEZv1$GA.401@cpmsnbbsa08>,
  "Brent" <Fun@work.net> wrote:
> Greetings everyone,
>
> I'm looking into learning FPGA and VHDL.
> I've recently been studying various HDL packages, such as Xilinx's
> foundation base, and Synplicity's Synplify.
>
> What I noticed is that they all mention they dont have Verilog and HDL
> synthesis.
>
> Does this mean that they dont actually have tools which enable me to
> write out an HDL file and compile it into a bitstream?

You need Foundation Express, rather than Foundation Base. I've just
bought it (about 300 UK pounds) and it includes Verilog and VHDL
synthesis, and implementation tools for most of the chips, apart from
the bigger Virtex ones. I think the Student Edition has Verilog and
VHDL also, and is a lot cheaper.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


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Article: 23161
Subject: Re: Designing a narrowband bandpass filter to pass a tone (analog
From: Tom Burgess <tom.burgess@home.com>
Date: Fri, 16 Jun 2000 09:15:43 GMT
Links: << >>  << T >>  << A >>
How about a crystal filter? 1.544 MHz is a stock crystal frequency from Epson
& CTS, so all you need is a bit of analog magic to get it to do what you want.

It would be nice if someone made a fast FPGA with onboard A/D and D/A converters,
in which case it could all be done digitally - but at some point you still need a
crystal for the clock. It would be a real coup for an FPGA manufacturer to come
up with an stable on-chip frequency synthesizer (no XTAL needed) along with the
aforementioned A/D & D/A converters. A single chip programmable signal processing
solution, and a nice challenge for the easily-bored R&D stable. Gazing into my amorphous
evacuated crystal pyramid, I expect significant progress announcements before
Q1/2001, because the ravings of Tom Burgess are but a wheedly Casio synth drone
over the relentless gutbusting hammer beats of technological inevitability.

regards, tom


"Nestor C." wrote:
> 
> Greetings all designers.
> 
> I don't know if this is the appropriate newsgroup to obtain help for
> my problem, but here goes.
> 
> Does anyone know a manufacturer producing very narrowband bandpass
> filters (BPF), or resonator filters in the range 1.5MHz-1.6MHz, with a
> center ideally at 1.5625MHz or 1.544MHz?
> I would like to pass a tone  centered at either one of these two
> frequencies with at least a 35dB out-of-band rejection.
> 
> I have examined the possibility of designing my own BPF using the LC
> elliptic design procedure, but the final result ends up being too
> costly in terms of the required printed circuit board (PCB) area (even
> for surface-mounted parts), the required number of individual
> components, and the large deviation from the design spec due to
> manufacturing tolerances.
> 
> I am desperately seeking a single component solution, if available, or
> a different approach, in order to meet my goal.
> 
> I have tried "whomakesit.com", but without any success in locating a
> manufacturer that could satisfy my needs.  Since it's possible I may
> have overlooked one manufacturer in my searches, I was hoping to
> obtain some suggestions from the contributors to these newsgroups, who
> know more about analog design than I do.
> 
> Thanks in advance to all and any information that you can provide.
> 
> Regards,
> 
> Nestor
Article: 23162
Subject: Re: difference between fpga and epld
From: rob_dickinson@my-deja.com
Date: Fri, 16 Jun 2000 09:15:56 GMT
Links: << >>  << T >>  << A >>
This is a serious question, because I often wonder why people ask such
questions:-

was it really quicker to post this question to a news group and wait a
day or so for someone to give you a one liner answer than to read page
1 of any EPLD datasheet and page 1 of any FPGA datasheet?

Rob

PS the answer you were given was correct as far as it went but a full
answer would take at least 200 words and did you really expect someone
to bother?


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Article: 23163
Subject: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
From: jan@panteltje.demon.nl (Jan Panteltje)
Date: Fri, 16 Jun 2000 11:43:38 GMT
Links: << >>  << T >>  << A >>
>Greetings all designers.
>
>I don't know if this is the appropriate newsgroup to obtain help for
>my problem, but here goes.
>
>Does anyone know a manufacturer producing very narrowband bandpass
>filters (BPF), or resonator filters in the range 1.5MHz-1.6MHz, with a
>center ideally at 1.5625MHz or 1.544MHz?  
>I would like to pass a tone  centered at either one of these two
>frequencies with at least a 35dB out-of-band rejection.
Did you try to have a singe xtal manufatured at one of those frequencies?
Jan
Article: 23164
Subject: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
From: "Reg Edwards" <G4fgq.Regp@btinternet.com>
Date: Fri, 16 Jun 2000 12:49:01 +0100
Links: << >>  << T >>  << A >>
Just use a single quartz crystal cut to the required frequency. 



Article: 23165
Subject: Re: 3.1i
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Fri, 16 Jun 2000 15:27:30 +0300
Links: << >>  << T >>  << A >>
erika_uk@my-deja.com wrote:

> why the version 3.1i has been already issued ???????

I think 3.1i is only being shipped to North America.
It might take 1 quarter to come to overseas.

Utku

--
I feel better than James Brown.



Article: 23166
Subject: Re: 68k - core, a free core 1, and 2 worth money = time.
From: "Mike Johnson" <mikej@freeuk.com>
Date: Fri, 16 Jun 2000 13:36:12 +0100
Links: << >>  << T >>  << A >>
For your interest there are 6502 & PIC cores at www.free-ip.com

Cheers

mikej@REMOVETHISfreeuk.com

Left blanks <noone@yoma.com> wrote in message
news:8i0eqa$m99$1@slb7.atl.mindspring.net...
>
> I just happen to have these nice and handy for ya:
>
> A "free" core, raw and untested :
> http://www.eej.ulst.ac.uk/tutor/m68000.html
> (It's nice to loath over what its missing and
> where...)
>
> Two "real" Motorola 68000 cores with support
>
> http://www.vlsi-concepts.com/V68000.html
> VLSI Concepts phone (610-408-9121)
> email hepler@vlsi-concepts.com
>
> and also:
>
> http://www.dcd.com.pl/english/d68000.htm
> tel. (210) 677 0185
> fax (210) 677 0635
> e-mail:info-us@dcd.com.pl
>
> --
> JoeT also squattith amiga @ mind spring.com !
>     Amiga, BeOS, Linux, QNX, Windoze
> So many mice: with so many meanings....
>
> "Holger Azenhofer" <holger.azenhofer@vs.dasa.de>
> wrote in message
> news:8g35hv$sdu@newsserv.vs.dasa.de...
> > Hi,
> >
> > I'm looking for a 68k - core in order to replace
> an old 68000 design with an
> > fpga.
> > does someone know an 68k core and where to get
> it.
> > 68020 would be fine.
> >
> > thanks
> >
> > Holger
> >
> >
>
>


Article: 23167
Subject: Re: PCI for a fpga board
From: Martin Heimlicher <heimlicher@scs.ch>
Date: Fri, 16 Jun 2000 16:54:18 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------B87A23F014A4842411807AC3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

On our PCI card with the PLX9080, we achieve only 40 MB/sec using DMA.
That's why we use programmed I/O to get over 100 MB/sec. The problem
with DMA on our Alpha 264 boards, is that the chipset is working only
with cache lines of 64 bytes. The PLX does not read cache line aligned
and therefore a large part of the bandwidth is lost.

BTW: Try to use Read Multiple or Read Line (it may help).

Regards,
  Martin
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Content-Transfer-Encoding: 7bit
Content-Description: Card for Martin Heimlicher
Content-Disposition: attachment;
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begin:vcard 
n:Heimlicher;Martin
tel;cell:+41 (0) 79 689 37 86
tel;fax:+41 (0) 1 445 16 10
tel;work:+41 (0) 1 445 16 07
x-mozilla-html:FALSE
url:http://www.scs.ch/
org:Supercomputing Systems AG;High Performance Computing
adr:;;Technoparkstrasse 1;Zürich;;8005;Switzerland
version:2.1
email;internet:martin.heimlicher@scs.ch
title:dipl. El.-Ing. ETH
fn:Martin Heimlicher
end:vcard

--------------B87A23F014A4842411807AC3--

Article: 23168
Subject: Re: Virtex IRDY and TRDY
From: Tom Fischaber <tom.fischaber@xilinx.com>
Date: Fri, 16 Jun 2000 09:00:15 -0600
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
The Spartan II powerdown mode does not assert the GSR as the SpartanXL
mode did.&nbsp; Instead, it preserves all internal register and RAM values.&nbsp;
This information should be pushed to the web in the next couple of days,
at which time it will be available at <A HREF="http://www.xilinx.com/techdocs/8812.htm">http://www.xilinx.com/techdocs/8812.htm</A>
(unfortunately it is not posted at the time of this posting though).&nbsp;
Here is the solution:
<p>General Description:
<p>What is the status of the I/O pins, configuration memory, distributed
RAM,
<br>and block RAM on a Spartan-II device in power down mode?
<p>Spartan-II Power down status summary:
<p>- Outputs are in a high-z state and inputs are disabled
<br>- All I/O pullups and pulldowns are disabled
<br>- Configuration memory is retained
<br>- Distributed RAM content is retained
<br>- Block RAM content is retained
<br>- Data register values are retained
<p>I hope that this helps clear up that question at least.&nbsp; I unfortunately
cannot comment on your documentation question, as I do not have control
of this process.
<p>Tom Fischaber
<br>Xilinx Applications
<blockquote TYPE=CITE>&nbsp;
<br>Even worse (for me) is I wanted to use the powerdown feature (PWDN
pin)
<br>on the Spartan II. This is **NOT described at all** in the Spartan
II
<br>datasheet. On a hunch I checked an old Spartan datasheet and found
a
<br>description which said that using that mode would assert the GSR and
<br>reset all the flip-flops, which was not acceptable for my application.
I
<br>ended up changing my approach.
<p>Perhaps someone from Xilinx would care to address in a meaningful form
<br>the increasing lack of important information from the newer datasheets.</blockquote>
</html>

Article: 23169
Subject: Re: Question: Xilinx FPGA PROGRAM pin
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 16 Jun 2000 11:20:16 -0400
Links: << >>  << T >>  << A >>
James Young wrote:
> 
> I'm  trying to program a single Xilinx FPGA 5210 in asynchronous peripheral
> mode (without using the JTAG pins).  I don't completely understand the
> PROGRAM pin's role in the configuration.  Is it toggled low, then brought
> high before configuration, and stays high throughout configuration?  Or is
> it brought low and stays low throughout configuration?  Or do I just leave
> it high throughout configuration and don't bother toggling it at all?

I see that Peter Alfke already replied to your post, but his answer was
a little terse I think. I am not sure he competely clarified your
confusion. The Program pin is used like a grand master reset. The FPGA
will do a "reset" on power up so that toggling the Program pin is not
needed in that case, as Peter indicated. But if you wish to not depend
on the power up (as in the case where you want to wait for other parts
to come up such as a processor) or if you need to reconfigure after the
FPGA is already configured, then you need to use the Program pin. 

To use Program, you pull it low for some minimum amount of time (which I
forget, but it is not long). The chip will start clearing the
configuration RAM. Sometime after the Program pin is released high, the
chip will complete another cycle of RAM clearing and start loading the
configuration data. You will not need to do anything further with
Program until you want to reload the FPGA. 

I assume that the rest of the configuration process is clear? I know
that although it is actually simple, it is a very unusual process and
seems complex the first time you see it. You just have to learn the
several rules and it all falls in place. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23170
Subject: Virtex ".FFX" contraint???
From: russojl@my-deja.com
Date: Fri, 16 Jun 2000 15:24:31 GMT
Links: << >>  << T >>  << A >>
In 4k type stuff, you used to be able to constrain flip flops
with a ".FFX" suffix, like:

loc=R1C1.FFX

What's the new way to do it in the Virtex.

Thanks,
	Jon

PS I'm starting to RTFM, but I figured someone could get the info to
me faster, since my reference skills are poor.


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Article: 23171
Subject: Re: XC4005XL OTP?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 16 Jun 2000 11:55:48 -0400
Links: << >>  << T >>  << A >>
Brent wrote:
> 
> Greetings again, and thank you to those
> who responded and answered my previous question.
> This question I have, is that I am wondering if Xilinx in perticular
> offers Fuse based versions of their XC4005XL FPGA, (which is
> in an eval board that I am considering). I have noticed that Altera
> and other companies offer a more extensive line of Fuse Based FPGA than what
> I have found of Xilinx's. (Although, the only place I have been able to find
> even Fuse based Xilinx FPGAs is on questlink.com ...)
> Thank you all again.

I don't think Xilinx will ever produce a Fuse based product similar to
any of their SRAM products. One of the significant features of an SRAM
based product is the SRAM. Not only can you reprogram it many, many
times (even differently at different points in a given application) the
SRAM can be used as... well, SRAM! If you replace the SRAM with fuses
you lose all of this and gain little except for relieving the need to
program the device. 

Xilinx did at one time provide a fuse based product. But they were not
at all compatible with any of the SRAM parts and obviously, they were
not a commercial success. 

Another big reason that Xilinx won't make Fuse based products (as the
Xilinx people have told us) is that including other elements in the chip
(such as Fuses or Flash memory) requires other processing steps that
SRAM does not use. This prevents the chips from using the very latest
processes, makes the chips larger and cost more. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
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Internet URL http://www.arius.com
Article: 23172
Subject: Re: FIFO design
From: dave_admin@my-deja.com
Date: Fri, 16 Jun 2000 16:03:44 GMT
Links: << >>  << T >>  << A >>
Great site , man . As I understand, ADD_WIDTH (2**ADD_WIDTH) defines the
length of the FIFO, and WIDTH defines width. Are all the architectures 
working ? In FIFO_v7 you used " ADD_WIDTH : integer := 4;" in component
DPMEM. In all other architectures you used  "ADD_WIDTH : integer := 4" . Why
the change ? Is the code synthesizable ?

regards,
Dave.


In article <39487175.46DFC43C@yahoo.com>,
  khatib@ieee.org wrote:
> Try to visit my memory cores page at
> http://www.geocities.com/SiliconValley/Pines/6639/ip/memory_cores.html
> You can also check http://www.opencores.org and http://www.free-ip.com
> You can find Free Open design cores
>
> Let me know if you are going to use my FIFO core
>
> Regards
> Jamil Khatib
> OpenCores Organization
>
> dave_admin@my-deja.com wrote:
>
> > Hi,
> >
> > Can somebody give me an example of FIFO design with width >1 ?
> > If it is parameterizable, even better.
> > VHDL is preferable, but Verilog is fine too.
> >
> > regards,
> > Dave.
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23173
Subject: Re: XC4005XL OTP?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 16 Jun 2000 09:15:05 -0700
Links: << >>  << T >>  << A >>
You are mistaken.

Neither Xilinx nor Altera nor Lattice nor Lucent make "fuse based FPGAs"
Actel and Quicklogic make anti-fuse based FPGAs.
And somebody may still make fuse-based bipolar PALs.

Perhaps you are thinking of non-volatile CPLDs.
Xilinx makes those, as does Altera and Lattice.

Peter Alfke



Brent wrote:

> Greetings again, and thank you to those
> who responded and answered my previous question.
> This question I have, is that I am wondering if Xilinx in perticular
> offers Fuse based versions of their XC4005XL FPGA, (which is
> in an eval board that I am considering). I have noticed that Altera
> and other companies offer a more extensive line of Fuse Based FPGA than what
> I have found of Xilinx's. (Although, the only place I have been able to find
> even Fuse based Xilinx FPGAs is on questlink.com ...)
> Thank you all again.

Article: 23174
Subject: 386 Chipset Example
From: cs993152@ella.cs.yorku.ca (Abdul S Khan)
Date: 16 Jun 2000 16:44:19 GMT
Links: << >>  << T >>  << A >>
I in the process of prototyping a IA 80386 system. I want to design my own
chipset to do bus steering from 8bit devices. Is there any example VHDL
code out there to give me a start? Anyone have any pointers? 

Thanks in advance

-- 
+----------------------------------------------------------------------+
|cs993152@ella.ariel.cs.yorku.ca (Shiraz Khan)                         |
+----------------------------------------------------------------------+
|Toronto, Ontario, Canada                                              |
+----------------------------------------------------------------------+


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