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Messages from 24275

Article: 24275
Subject: Re: Viewlogic Licencing
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 02 Aug 2000 08:18:43 -0400
Links: << >>  << T >>  << A >>
Philip Freidin wrote:
> Rick Collins wrote:
> >Maybe I am just a contrarian, but I saw the licensing working the other
> >way. I would *only* buy the FPGA workstations since I needed to be able
> >to support the FPGA stations. Using a board station would make the
> >design incompatible with the rest of the world of FPGA stations.
> 
> Well, first of all, Xilinx stopped reselling the restricted version
> about 2 years ago, and I believe only Lucent now sells a restricted
> version.

Yes, but I am using the Lucent stuff for now. 

 
> Second, the restricted version only works with the designated FPGA
> vendor's libraries, so you cant use the generic PCB libraries.
> If you had infinite time, you could create your own, but you would
> still have the problem that there is no export netlister from the
> restricted version to PCB packages.

My point is that using the viewlogic for board design will get in the
way of doing FPGA design. I won't be able to use the same package for
each. So while I have to use Viewlogic for FPGA design why not use what
I want for schematic? 

 
> Viewlogic (and expect Innoveda) have had rather attractive upgrade plans
> to convert restricted Viewdraw to unrestricted. I now mostly have
> unrestricted licences. Compared to the time spent screwing around with
> different versions (and considering what I charge per hour), it just
> wasn't worth the effort.

That is fine if you only have to support your own in-house use of the
tools. But one of my goals in selling these DSP boards is to allow my
customers to design their own FPGAs using the low end viewlogic based
tools. It would be a real crimp to have to tell them that the tools are
$100 for the FPGA stuff and an additional $2000 to be able to read my
schematics!!!


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 24276
Subject: Re: Desperatly needing a SpartanII
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Wed, 02 Aug 2000 14:43:30 +0200
Links: << >>  << T >>  << A >>
"K. Orthner" a écrit :
> Nicolas:
>  The XCV50 is a virtex part and has the same blockRAM ( and
> everything elser ) as the XC2S50.  I think you're thinking of a
> XCS50, which is a spartan, which does not have the BlockRAMs.

Yes you're right, I misread the part name. I shouldn't read the news
before having coffee.


> Ray:
>  According to my data book, the XCV50 (Virtex) is not available in
> the PQ208 package, which is the reason that Nicolas has a problem in
> the first place.  (I think!)

Exactly (I said it, didn't I ?)


> I take it that you're past the state of choosing a different package?

The PCB is already on my desk, waiting for the chip to be soldered :o(

-- 
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      F-92400 COURBEVOIE - FRANCE
Fax +33 1 46 67 51 01      http://www.dotcom.fr/
Article: 24277
Subject: Re: Desperatly needing a SpartanII
From: Ray Andraka <ray@fpga-guru.com>
Date: Wed, 02 Aug 2000 14:14:41 GMT
Links: << >>  << T >>  << A >>
Huh?

I think you need to go take another look at your data book.  The XCV50 and
XC2S50 are virtually identical except the spartanII has a power down mode
where the Virtex has a temperature sense diode.  Same number of CLBs and
block rams, same DLLs, same special PCI logic.  I'm pretty sure they'll even
take the same bitstreams.  I've got one customer that couldn't get the
XC2S50 in the FG256 package, so we did a last minute substitution for an
XCV50 in the same package.  *NO* changes were needed in the design to put it
in the other

Nicolas Matringe wrote:

> Ray Andraka a écrit :
> >
> > In a pinch you should be able to use an XCV50 in the same package
> > unless you are using the power down mode (replaces the temperature
> > sense diode). I think even the bitstreams are the same, although the
> > xilinx jtag tool may tell you different.
>
> What about the BlockRAMs ? I need four of them and I know there won't be
> enough space in an XCV50 for the logic AND the 16kbits of RAM.
>
> --
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel +33 1 46 67 51 11      F-92400 COURBEVOIE - FRANCE
> Fax +33 1 46 67 51 01      http://www.dotcom.fr/

Article: 24278
Subject: Re: Desperatly needing a SpartanII
From: Ray Andraka <ray@fpga-guru.com>
Date: Wed, 02 Aug 2000 14:16:43 GMT
Links: << >>  << T >>  << A >>
Oh,

I didn't look at his packaging.  I haven't used the PQ208's in a while so I
just ass_u_me'd  the VIrtex was available in the same.

Nicolas Matringe wrote:

> "K. Orthner" a écrit :
> > Nicolas:
> >  The XCV50 is a virtex part and has the same blockRAM ( and
> > everything elser ) as the XC2S50.  I think you're thinking of a
> > XCS50, which is a spartan, which does not have the BlockRAMs.
>
> Yes you're right, I misread the part name. I shouldn't read the news
> before having coffee.
>
> > Ray:
> >  According to my data book, the XCV50 (Virtex) is not available in
> > the PQ208 package, which is the reason that Nicolas has a problem in
> > the first place.  (I think!)
>
> Exactly (I said it, didn't I ?)
>
> > I take it that you're past the state of choosing a different package?
>
> The PCB is already on my desk, waiting for the chip to be soldered :o(
>
> --
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel +33 1 46 67 51 11      F-92400 COURBEVOIE - FRANCE
> Fax +33 1 46 67 51 01      http://www.dotcom.fr/

Article: 24279
Subject: Re: FPGA selection
From: Ray Andraka <ray@fpga-guru.com>
Date: Wed, 02 Aug 2000 14:18:30 GMT
Links: << >>  << T >>  << A >>
You've got three nearly orthagonal parameters here.  You need to weigh your
specific needs to make a choice.  IE, maximum logic is a pretty big device
that you are going to spend alot of money on.

Jamil Khatib wrote:

> Hi,
>
> Could you please suggest me the best FPGA to use that has minimum price,
> maximum logic gates and provides maximum FIFO memory buffer.
>
> Thanks in advance
> Jamil Khatib

Article: 24280
Subject: Category : Subject
From: "Jian Lin" <Jianlin@ee.umanitoba.ca>
Date: Wed, 2 Aug 2000 07:26:21 -0700
Links: << >>  << T >>  << A >>
Hi, 
Is there a FPGA part which has 5-input LUT and about 2000 Flip-flops?
Thanks a lot.
Jian
Article: 24281
Subject: 8251A USART
From: Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk>
Date: Wed, 02 Aug 2000 17:36:22 +0100
Links: << >>  << T >>  << A >>

Hi

Does anybody know the price of a synthesizable 8251A core? I'm also
looking for a Manchester encoder/decoder. Is there a place where I
can find these cores for free? I'll decide which FPGA to use in my
design as soon as I find the cores.

Thanks

Eduardo.
Article: 24282
Subject: Re: FPGA selection
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 02 Aug 2000 10:19:21 -0700
Links: << >>  << T >>  << A >>


Jamil Khatib wrote:
> Could you please suggest me the best FPGA to use that has minimum price,
> maximum logic gates and provides maximum FIFO memory buffer.
> Jamil Khatib

Xilinx.
Xilinx Spartan and Spartan-II
Xilinx Virtex
Xilinx Virtex-E
Xilinx.

I am not biassed, really.


-- 
Philip Freidin

Mindspring that acquired Earthlink that acquired Netcom has
decided to kill off all Shell accounts, including mine.

My new primary email address is    philip@fliptronics.com

I'm sure the inconvenience to you will be less than it is for me.
Article: 24283
Subject: Re: 8251A USART
From: Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk>
Date: Wed, 02 Aug 2000 19:13:32 +0100
Links: << >>  << T >>  << A >>

My design will have, basically, an 8251 and a manchester
encoder/decoder. It'll be used to teach concepts of data
communications to undergraduate students. We're considering
the use of the same board (with the same FPGA) to implement
different UARTs and USARTs. Do you think the Xilinx XCV50
FPGA is a good option? We're going to build 30 kits and the
cost of the FPGAs (XCV50) + serial PROMs will be something
around US$1,500.00. Is it the best option for this design?
Is there a less expensive solution?

Thanks

Eduardo.


Peter Alfke wrote:
> 
> Eduardo Augusto Bezerra wrote:
> 
> > Hi
> >
> > Does anybody know the price of a synthesizable 8251A core? I'm also
> > looking for a Manchester encoder/decoder. Is there a place where I
> > can find these cores for free? I'll decide which FPGA to use in my
> > design as soon as I find the cores.
> >
> 
> A Manchester encoder is trivial, essentially an XOR.
> A Manchester decoder is described in the Xilinx XCell magazine in
> 1995.
> The design uses only three XC3000 or XC4000 or Spartan CLBs.
> 
> http://www.xilinx.com/xcell/xl17/xl17-30.pdf
> 
> Peter Alfke, Xilinx Applications

--
Eduardo Augusto Bezerra
Space Science Centre
School of Engineering and Information Technology
University of Sussex
Brighton, BN1 9QT
England, UK

Phones: +44 (0)1273 877086 or +44 (0)700 5568783
Fax: +44 (0)1273 678399
EIT II, room 4B11

*** UK ***
mailto:E.A.Bezerra@sussex.ac.uk - http://www.sussex.ac.uk/~tapu9
Space Group's web site: http://www.sussex.ac.uk/engg/research/space
*** Brasil ***
mailto:eduardob@inf.pucrs.br - http://www.inf.pucrs.br/~eduardob
GAPH's web site: http://www.inf.pucrs.br/~gaph
*** ACM ***
mailto:eduardob@acm.org
Article: 24284
Subject: Re: 8251A USART
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 02 Aug 2000 14:53:01 -0400
Links: << >>  << T >>  << A >>
> My design will have, basically, an 8251 and a manchester
> encoder/decoder. It'll be used to teach concepts of data
> communications to undergraduate students. We're considering
> the use of the same board (with the same FPGA) to implement
> different UARTs and USARTs. Do you think the Xilinx XCV50
> FPGA is a good option? We're going to build 30 kits and the
> cost of the FPGAs (XCV50) + serial PROMs will be something
> around US$1,500.00. Is it the best option for this design?
> Is there a less expensive solution?

The XCV50 is overkill for just an 8251 and a Manchester encoder/decoder,
but it makes sense if you want to work with a current FPGA family.  The
older Xilinx XC4000 family will also suit your application.

Remember that the XCV50 only comes in a surface mount package so you will
need to build a PCB to hold it.  You will spend several times your $1500
building and supporting the lab infrastructure that surrounds the FPGA and
serial PROM.  You might want to check the list of FPGA boards at
www.optimagic.com to see if there is a one that will suit your needs.

>
>
> Thanks
>
> Eduardo.
>
> Peter Alfke wrote:
> >
> > Eduardo Augusto Bezerra wrote:
> >
> > > Hi
> > >
> > > Does anybody know the price of a synthesizable 8251A core? I'm also
> > > looking for a Manchester encoder/decoder. Is there a place where I
> > > can find these cores for free? I'll decide which FPGA to use in my
> > > design as soon as I find the cores.
> > >
> >
> > A Manchester encoder is trivial, essentially an XOR.
> > A Manchester decoder is described in the Xilinx XCell magazine in
> > 1995.
> > The design uses only three XC3000 or XC4000 or Spartan CLBs.
> >
> > http://www.xilinx.com/xcell/xl17/xl17-30.pdf
> >
> > Peter Alfke, Xilinx Applications
>
> --
> Eduardo Augusto Bezerra
> Space Science Centre
> School of Engineering and Information Technology
> University of Sussex
> Brighton, BN1 9QT
> England, UK
>
> Phones: +44 (0)1273 877086 or +44 (0)700 5568783
> Fax: +44 (0)1273 678399
> EIT II, room 4B11
>
> *** UK ***
> mailto:E.A.Bezerra@sussex.ac.uk - http://www.sussex.ac.uk/~tapu9
> Space Group's web site: http://www.sussex.ac.uk/engg/research/space
> *** Brasil ***
> mailto:eduardob@inf.pucrs.br - http://www.inf.pucrs.br/~eduardob
> GAPH's web site: http://www.inf.pucrs.br/~gaph
> *** ACM ***
> mailto:eduardob@acm.org

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


Article: 24285
Subject: VirtexE FF set/reset
From: RSB <rick_bogdan@ins.memec.com>
Date: Wed, 2 Aug 2000 13:18:06 -0700
Links: << >>  << T >>  << A >>
Does anyone know how the set/reset ckts work in the VIRTEX-E. I noticed a block with options for these functions in FPGA editor. It appears that this may be a LUT function. If so what kind of delays/timings can I expect?
Article: 24286
Subject: Re: Viewlogic Licensing
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 02 Aug 2000 16:24:51 -0400
Links: << >>  << T >>  << A >>
I got the response back from a Innoveda representative. They still have
the licensing problem and the only solution is to upgrade all of the
workstations to a FULL seat. They also sent me pricing for this and if
you want to use VHLD (or I assume Verilog, but not both) it will cost
$5,000 for a seat upgrade or $12,000 for a FULL seat from scratch. They
did not respond to my question about maintenance, so it is unclear which
of these prices include some period of support. 

For my purposes, this eliminates using Viewlogic as a board level tool
as it will greatly complicate the use of Viewlogic as an FPGA design
tool. 

BTW, Viewlogic has OEM versions for Actel, Lucent, Lattice, Motorola and
Atmel products. 

I'm still unclear as to how Austin Franklin feels about using Orcad  ;)



rickman wrote:
> > Is the FPGA only thing even an issue anymore, now that VL isn't being
> > packaged with the FPGA tool suites from the vendors?  I do remember what a
> > PITA it was.
> 
> That is what Lucent provides. But I may be switching to Xilinx Spartan
> II with my next board design. If so, I may still want to use Viewlogic
> for both. Doesn't  Viewlogic still sell FPGA only systems? I looked on
> the web site and found separate products for board level design and
> FPGA. They don't have much information to go on so it is hard to tell.
> 
> I am sending them an email. We'll see how they respond to the issue.
> 
> --
> 
> Rick Collins
> 
> rick.collins@XYarius.com
> 
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
> 
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
> 
> Internet URL http://www.arius.com

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 24287
Subject: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
From: Wayne <Wayne@GoodWare.com>
Date: Wed, 02 Aug 2000 14:37:46 -0700
Links: << >>  << T >>  << A >>

I've been using QuickLogic for about a year now and have had good luck with
them. What sort of problems did you have with Actel ?

Wayne

Steve Rencontre wrote:

> In article <01bffb20$69dd0180$3e06f7a5@drt1>, austin@darkroom88.com
> (Austin Franklin) wrote:
>
> > I have a design that currently uses a PLX 9080, and I need to move it
> > to a
> > 64 bit and/or 66MHz PCI interface...  PLX does not currently offer a
> > solution, that I can find...neither does AMCC.  Any suggestions for off
> > the
> > shelf chips to do this, or any experience with the QuickLogic QL5064
> > interface chip?
>
> I've been thinking about QuickLogic, but past experience with Actel has
> put me off OTP technologies.
>
> --
> Steve Rencontre         http://www.rsn-tech.co.uk
> //#include <disclaimer.h>

Article: 24288
Subject: 32-input AND and 100-input OR - can I do it fast?
From: "Ken Christensen" <christen@csee.usf.edu>
Date: Wed, 2 Aug 2000 17:41:04 -0400
Links: << >>  << T >>  << A >>
Hello, FPGA's are not my area. so, my apologies if this is a really stupid
(or textbook) question.  What size AND and OR arrays are available in
existing devices?  If I want arrays of 32 input ANDs and 100 input ORs, can
I do this in *two-levels*?  If so, what is the gate delay of the 32 input
AND and 100 input OR?  I want to implement some rather complex two-level
logic equations with delay of less than 1 nanosecond. is this achievable
with FPGA technology?  If yes, which technology/vendor?  If not with FPGA's,
how could I implement this?

Thank you!


Ken Christensen
===============================================================
=  Kenneth J. Christensen (Assistant Professor)
=  Department of Computer Science and Engineering
=  University of South Florida
=  (813) 974-4761
=  http://www.csee.usf.edu/~christen
===============================================================


Article: 24289
Subject: Re: 32-input AND and 100-input OR - can I do it fast?
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 2 Aug 2000 21:54:15 GMT
Links: << >>  << T >>  << A >>
In article <8ma4e0$62v$1@news.usf.edu>,
Ken Christensen <christen@csee.usf.edu> wrote:
>Hello, FPGA's are not my area. so, my apologies if this is a really stupid
>(or textbook) question.  What size AND and OR arrays are available in
>existing devices?  If I want arrays of 32 input ANDs and 100 input ORs, can
>I do this in *two-levels*?  If so, what is the gate delay of the 32 input
>AND and 100 input OR?  I want to implement some rather complex two-level
>logic equations with delay of less than 1 nanosecond. is this achievable
>with FPGA technology?  If yes, which technology/vendor?  If not with FPGA's,
>how could I implement this?

	The basic building block of FPGAs are commonly 4 luts.  A 100
input AND or OR requires a tree of 4-LUTs which is 4 levels deep.  A
single lut evaluation takes .5 ns in a modern FPGA, but the
interconnect can easily double that time.

	Some FPGAs (altera) can implement PLD like structures, which
might be faster for such wide turms.

	Out of curiosity, what ARE you trying to do?
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 24290
Subject: Re: Viewlogic Licensing
From: Ray Andraka <ray@fpga-guru.com>
Date: Wed, 02 Aug 2000 22:09:24 GMT
Links: << >>  << T >>  << A >>


rickman wrote:

> I got the response back from a Innoveda representative. They still have
> the licensing problem and the only solution is to upgrade all of the
> workstations to a FULL seat. They also sent me pricing for this and if
> you want to use VHLD (or I assume Verilog, but not both) it will cost
> $5,000 for a seat upgrade or $12,000 for a FULL seat from scratch. They
> did not respond to my question about maintenance, so it is unclear which
> of these prices include some period of support.

Yikes, I was hoping they had gotten past all that.  It's a shame to have something
so assinine cripple such a first rate tool.

>
>
> For my purposes, this eliminates using Viewlogic as a board level tool
> as it will greatly complicate the use of Viewlogic as an FPGA design
> tool.
>
> BTW, Viewlogic has OEM versions for Actel, Lucent, Lattice, Motorola and
> Atmel products.
>
> I'm still unclear as to how Austin Franklin feels about using Orcad  ;)
>

We are all wondering this.  Austin, care to tell us how you feel without holding
anything back?  :-)

Article: 24291
Subject: Re: 32-input AND and 100-input OR - can I do it fast?
From: Ray Andraka <ray@fpga-guru.com>
Date: Wed, 02 Aug 2000 22:11:42 GMT
Links: << >>  << T >>  << A >>
FPGAs don't do wide combinatorial functions especially well.  You could do it
with the tristate bus or with a fast carry chain, but not at less than a ns.

Ken Christensen wrote:

> Hello, FPGA's are not my area. so, my apologies if this is a really stupid
> (or textbook) question.  What size AND and OR arrays are available in
> existing devices?  If I want arrays of 32 input ANDs and 100 input ORs, can
> I do this in *two-levels*?  If so, what is the gate delay of the 32 input
> AND and 100 input OR?  I want to implement some rather complex two-level
> logic equations with delay of less than 1 nanosecond. is this achievable
> with FPGA technology?  If yes, which technology/vendor?  If not with FPGA's,
> how could I implement this?
>
> Thank you!
>
> Ken Christensen
> ===============================================================
> =  Kenneth J. Christensen (Assistant Professor)
> =  Department of Computer Science and Engineering
> =  University of South Florida
> =  (813) 974-4761
> =  http://www.csee.usf.edu/~christen
> ===============================================================

Article: 24292
Subject: Re: 32-input AND and 100-input OR - can I do it fast?
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 02 Aug 2000 15:17:59 -0700
Links: << >>  << T >>  << A >>
"Ken Christensen" <christen@csee.usf.edu> writes:

> Hello, FPGA's are not my area. so, my apologies if this is a really stupid
> (or textbook) question.  What size AND and OR arrays are available in
> existing devices?  If I want arrays of 32 input ANDs and 100 input ORs, can
> I do this in *two-levels*?  If so, what is the gate delay of the 32 input
> AND and 100 input OR?  I want to implement some rather complex two-level
> logic equations with delay of less than 1 nanosecond. is this achievable
> with FPGA technology?  If yes, which technology/vendor?  If not with FPGA's,
> how could I implement this?
> 

In the Xilinx architecture these wide ANDs can be efficiently implemented
via the dedicated carry logic. Below is an example taken by a Xilinx app note
implementing in this way the wide AND of a comparator. I'm not sure about the
maximum speed that you achieve in this way, anyway 32 bits in less that 1 ns
seems quote tough to me.

Best,

-Arrigo
--
Dr. Arrigo Benedetti                e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	  			phone: (626) 395-3695
Pasadena, CA 91125	  			fax:   (626) 795-8649

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library unisim;
use unisim.all;

entity fastcomp is
    generic (n : integer := 8); 	-- Word length
    port (a_in : in std_logic_vector (n - 1 downto 0);
	  b_in : in std_logic_vector (n - 1 downto 0);
	  comp_out : out std_logic);
end fastcomp;

architecture synthesis of fastcomp is

    signal a      : std_logic_vector (n - 1 downto 0);
    signal b      : std_logic_vector (n - 1 downto 0);
    signal comp   : std_logic_vector (n - 1 downto 0);
    signal muxcyo : std_logic_vector (n - 1 downto 0);
    signal co     : std_logic;
    signal cin    : std_logic;
    signal gnd    : std_logic;
    signal pwr    : std_logic;

    component MUXCY_L
	port (
	    DI:  in std_logic;
	    CI:  in std_logic;
	    S:   in std_logic;
	    LO: out std_logic);
    end component;

begin

    gnd <= '0';
    pwr <= '1';
    a <= a_in;
    b <= b_in;
    comp_out <= co;

    pxor : process (a, b)
	variable XORcomp : std_logic_vector (n - 1 downto 0);
    begin  -- process pxor
	lp0 : for i in 0 to n - 1 loop
	    XORcomp(i) := not (a(i) xor b(i));
	end loop lp0;
	
	comp <= XORcomp;
    end process pxor;
    
    muxcyi: MUXCY_L port map (DI => pwr, CI => pwr, S => pwr, LO => cin);
    
    lp1 : for i in 0 to n - 1 generate
	g0 : if i = 0 generate
	    muxcy0 : MUXCY_L port map (DI => gnd, CI => cin, S => comp(i),
				       LO => muxcyo(i));
	end generate;
	gi : if i > 0 and i < n - 1 generate
	    muxcyi : MUXCY_L port map (DI => gnd, CI => muxcyo(i - 1),
				       S => comp(i), LO => muxcyo(i));
	end generate;
	gn : if i = n - 1 generate
	    muxcyn : MUXCY_L port map (DI => gnd, CI => muxcyo(i - 1),
				       S => comp(i), LO => co);
	end generate;
    end generate;
end synthesis;
Article: 24293
Subject: GPIO board for Avnet Virtex Development system ?
From: Muzaffer Kal <muzaffer@kal.st>
Date: 02 Aug 2000 22:50:50 GMT
Links: << >>  << T >>  << A >>
hi,
I have an Avnet Virtex Development Board. This has a bus interface
which they call GPIO. Does anyone know if there are any boards which
plug into this GPIO to add some chips? Basically I am looking for a
board which would let me do some wire-wrap or soldering area.

thanks,

Muzaffer

Article: 24294
Subject: Re: Desperatly needing a SpartanII
From: Jean-Paul Smeets <jpsmeets@xs4all.nl>
Date: Thu, 03 Aug 2000 01:21:54 +0200
Links: << >>  << T >>  << A >>
Hi, we were in the same situation a couple of months ago.

We designed boards with the  XC2S50-5PQ208, but used  XC2S100-5PQ208
for the first series.  The  XC2S100-5PQ208 were normally easier to
get.

Since a month we use both types.

We get ours from MEMEC in the Benelux, which from their WEB site has 4
companies in France.

MEMEC is normally very good at at obtaining a few samples.



On Tue, 01 Aug 2000 17:48:17 +0200, Nicolas Matringe
<nicolas@dotcom.fr> wrote:

>Hi all
>We are trying to get an XC2S50-5PQ208 but can't find any. Avnet seems to
>sell them quicker than they can buy them from Xilinx... We plan to buy
>quantities but need some parts for prototyping extremely quickly (and
>there's no Virtex with a PQ208 package). I contacted a friend of mine at
>Xilinx France, too... Still waiting.
>Can any of you sell us 1 or 2 chips (any size, as long as it's an XC2S
>with a PQ208 package)? We can give our FedEx account # for shipping (+
>small gift)
>
>Thanks in advance

J.P. Smeets
business:
Ellips
Woenselsestr 352A
5623 EG Eindhoven
tel: +31-40-2456540
fax: +31-40-2467183
email: jeanpaul@ellips.nl
home:
Loondermolen 23
5612 MH Eindhoven
tel: +31-40-2465105
email: jpsmeets@xs4all.nl
Article: 24295
Subject: Re: GPIO board for Avnet Virtex Development system ?
From: korthner@hotmail.nospam.com (K. Orthner)
Date: 3 Aug 2000 00:47:24 GMT
Links: << >>  << T >>  << A >>
This is just an educated (?) guess, but I would assume that GPIO simply 
stands for General Purpoose I/O, and isn't really a bus, per se.  I would 
think that it's just a bunch of wires running from the FPGA out to a 
connector that easily allows you to connect other things, be it boards, 
chips, or otherwise.

-Kent


muzaffer@kal.st (Muzaffer Kal) wrote:
>I have an Avnet Virtex Development Board. This has a bus interface
>which they call GPIO. Does anyone know if there are any boards which
>plug into this GPIO to add some chips? Basically I am looking for a
>board which would let me do some wire-wrap or soldering area.
>
>thanks,
>
>Muzaffer
>
>

Article: 24296
Subject: GPIO board for Avnet Virtex Development system ?
From: Muzaffer Kal <muzaffer@kal.st>
Date: 03 Aug 2000 01:45:47 GMT
Links: << >>  << T >>  << A >>
hi,
I have an Avnet Virtex Development Board. This has a bus interface
which they call GPIO. Does anyone know if there are any boards which
plug into this GPIO to add some chips? Basically I am looking for a
board which would let me do some wire-wrap or soldering area.

thanks,

Muzaffer

Article: 24297
Subject: Re: 8251A USART
From: "Geoffrey G. Rochat" <geoff@pkworks.com>
Date: Wed, 2 Aug 2000 22:15:45 -0400
Links: << >>  << T >>  << A >>
"The Verilog Hardware Description Language", 2nd Ed., by Donald E.
Thomas and Philip R. Moorby, 1995, Kluwer Academic Publishers, ISBN
0-7923-9523-9, uses an 8251 design as an example.

Eduardo Augusto Bezerra wrote in message
<39884E06.9A935AD0@sussex.ac.uk>...
>
>Hi
>
>Does anybody know the price of a synthesizable 8251A core? I'm also
>looking for a Manchester encoder/decoder. Is there a place where I
>can find these cores for free? I'll decide which FPGA to use in my
>design as soon as I find the cores.
>
>Thanks
>
>Eduardo.


Article: 24298
Subject: models of digital ICs
From: lamb_baa@hotmail.com (Eric L)
Date: 3 Aug 2000 03:52:43 GMT
Links: << >>  << T >>  << A >>
Are there any archives of digital ICs available? I checked the FAQ and there 
didn't seem to be any. What I need is say a model of a 74373 or whatever 
(doesn't matter - the more models the better). It would make sense that no one 
has collected them or even bothered programming them since FPGAs/CPLDs you can 
usually make your logic very specific to your needs and ICs are pretty basic. I 
know it's not that hard to program it myself I'd just rather not waste my time 
on modeling simple IC devices if it's already available. 

Thanks
eric

Article: 24299
Subject: Re: FPGA selection
From: Jamil Khatib <Khatib@opencores.org>
Date: Thu, 03 Aug 2000 08:02:50 +0200
Links: << >>  << T >>  << A >>
OK I give more priority on the price and the size of memory that can be
implemented on it

Thanks in advance

Ray Andraka wrote:

> You've got three nearly orthagonal parameters here.  You need to weigh your
> specific needs to make a choice.  IE, maximum logic is a pretty big device
> that you are going to spend alot of money on.
>
> Jamil Khatib wrote:
>
> > Hi,
> >
> > Could you please suggest me the best FPGA to use that has minimum price,
> > maximum logic gates and provides maximum FIFO memory buffer.
> >
> > Thanks in advance
> > Jamil Khatib



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