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Messages from 25850

Article: 25850
Subject: Re: Is correct code?
From: Mujtaba Hamid <mujtaba.hamid@xilinx.com>
Date: Fri, 22 Sep 2000 15:59:30 -0600
Links: << >>  << T >>  << A >>
It seems that D is the bi-directional port and D_IN and D_OUT are busses interfacing with the port D.
If that is the case, the correct code would be

inout [7:0] D;
input CNTRL;

wire D_IN;
reg D_OUT;

assign D = CNTRL ? D_OUT : 8'bZ; -- 3 stated output

always @ (CNTRL or D)
if (CNTRL = '0')
  D_IN <= D;


Mujtaba

Tomasz Brychcy wrote:

> Hello,
>
> I have written a model of tri state data bus:
>
> ports:
>
> inout [7:0] D;
> input [7:0] D_IN;
> input CNTRL;
> output [7:0] D_OUT;
>
> assign D=(CNTRL) ? D_IN ? 8'bz; //write
> assign D_OUT=(~CNTRL) ? D ? 8'bz; //read
>
> When I simulate the model (timing simulation) results are not correct. Behavioral simulation (before and after synthesis ) is correct. What I should do? Maybe testbench is wrong?
>
> I request for reply
>
> Tomek



Article: 25851
Subject: Re: Virtex 1800 series ISP proms
From: chadlamb@my-deja.com
Date: Fri, 22 Sep 2000 22:13:38 GMT
Links: << >>  << T >>  << A >>
Make sure you are using the 31i, sp2 or later.  We came across the same
problem.  They had screwed up the software.  We didn't have to do
anything to pins to get it to work, just update your software.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25852
Subject: Need Help: Xilinx FastCLK (XC4000XLA)
From: "James S." <ads@begone.com>
Date: 22 Sep 2000 17:23:41 -0500
Links: << >>  << T >>  << A >>
Hi,

I am fairly new to using Foundation 3.1i, and I am using it to design
something for an XC4085XLA-HQ304 FPGA.  Here is the error I am getting:

ERROR:OldMap:56 - The LOC constraint "P98" (a FCLKIOB location) is not valid
   for IPAD symbol "C1263" (pad signal=CLK25MHZ), which is being mapped to
the
   following site types:
    CLKIOB

My design is in VHDL.  I do have a clock signal going to pin 98, which is an
IO/ FCLK4 pin, but it doesn't matter to me if it's treated as an IO or a
clock pin.  What do I need to do to make this work?

Thanks,
James


Article: 25853
Subject: Re: Announce: Free HC11 CPU Core
From: "Eric Braeden" <braeden@erinet.com>
Date: Fri, 22 Sep 2000 19:31:58 -0400
Links: << >>  << T >>  << A >>

Scott Thibault <thibault@gmvhdl.com> wrote in message
news:8qfo69$rf4$1@slb7.atl.mindspring.net...
> Hi Ray,
>
> VHDLStudio is only required to run the included HC11 debugger.  The core
is
> in standard VHDL which can be simulated and synthesized with any standard
> tool.
>
> Regards,
> --Scott Thibault
> Green Mountain
> Computing Systems, Inc.
>
    Scott has some nice code here, but low-end tools like Warp choke
on several parts of it. I want to like Warp, but it just doesn't seem
to measure up.  Does anyone use it for real projects?

Eric



Article: 25854
Subject: Re: memory interface trouble...
From: "tim simpson" <tim@nospam.monster-works.co.nz>
Date: Sat, 23 Sep 2000 12:03:19 +1200
Links: << >>  << T >>  << A >>
> Even during configuration, the pins may be pulled High ( perhaps
> even Low) by a weak internal resistor, since nobody likes floating
> inputs. Maybe the uP reacts to these logic levels...

The Infineon series micros configure the external bus and system
(like emulation mode) and clock settings on Port 0, which is the
external data (multiplexed address/data) port.  There are internal
pull ups on these pins active during startup and the pins correct
pins for the configuration you require need to be pulled low
externally during reset.  As others have mentioned if your FPGA is
pulling some of these lines low during startup you could have all
sorts of strange configurations happening.  See the Infineon user manual
m167.pdf on the website for more details of the configuration settings.
They also have an appnote on how to calculate the appropriate pull-down
resistors (on an unloaded port they need to be at least 8k2).
The appnote number on system restart configuration is AP163701.

Tim Simpson
Design Engineer
EISS Subtronics Ltd
tim at monster-works.co.nz
return email address invalid


Article: 25855
Subject: Re: Multi-Arch, Moderately High performance VHDL FPGA Code?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 23 Sep 2000 00:35:05 GMT
Links: << >>  << T >>  << A >>
The short answer is yes.  You can often get reasonably high performance using
only the constructs that a decent synthesis tool generates.  All that infers is
that you have written your code in such a way that it doesn't pile many levels
of combinatorial stuff between registers.  For example, A simple shift register
will pretty much run at the max speeds of the fpga regardless of the
architecture.

Filling up a big device is not hard either, **especially** if you don't use the
device features in your code.  

So, neither of these benchmarks are truely a measure of optimality for an FPGA
design.  I'm not sure what you would use as an objective metric.  Perhaps the
ratio of equivalent gates (in your design) to marketing gates.  For example I
finished an XCV50 design this week that has 185,393 equivalent gates, nearly 4x
the marketing gate count and yet only 64% of the LUTs are used. Perhaps that
isn't a good number after all, since memory drives up the gate count.  On the
otherhand, you won't get the big ratios without using CLB RAM or shift rgister
mode, so perhaps it isn't a bad measurement of the mapping efficiency (some
weighting would have to be done to account for the block ram usage perhaps).  

FOr the speed grade comment, Having to use one of the faster speed grade parts
is not what I'd consider a badge of honor, A true mark of excellence is getting
a fast design to meet timing in a slow speed grade part.  Virtex -4 parts (you
know the slow speed grade) are quite capable of 133 MHz design if the design is
done carefully.  I'm not talking about simple shift regsiters here either.  My
16 point FFT runs at 153 MHz in an XCV100-4 in its current incarnation.


When it comes down to the bottom line, I guess the measurement could be is the
customer happy with the price and performance.  That's what it's all about isn't
it?



Robert Posey wrote:
> 
> Dear Gentle Persons,
> 
> Has anyone successfully written VHDL code for large FPGA's that is transportable
> without modification between Xlinx, Altera Etc. I looking for someone who
> has actually successfully complete the process.  To get reasonable high
> performance, its seems almost everyone uses arch. specific components, which
> likely won't match up at least between companies.  Has anyone tried this
> lately.  By Moderately high performance I mean a FPGA more than 70% utilized,
> and operating at speed levels that require one of the faster speed grades for
> a given arch.
> 
> Muddy

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25856
Subject: Re: Announce: Free HC11 CPU Core
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Sat, 23 Sep 2000 00:48:18 GMT
Links: << >>  << T >>  << A >>
Eric,
     Warp is too simple and lousy of a tool to do anything but relatively
simple CPLD designs.  You might want to start disliking Warp if you plan on
tackling the HC11 core or anything that is comparable in complexity.  I
suspect that the reason you want to like Warp is because it is free?
-Simon Ramirez, Consultant
 Synchronous Design, Inc.

P.S.  It's too bad that Cypress never did anything great with their
programmable line.  I guess there was more money in Roboclocks and such.


"Eric Braeden" <braeden@erinet.com> wrote in message
news:39cbebca$0$35381$53a6afc1@news.erinet.com...
>
> Scott Thibault <thibault@gmvhdl.com> wrote in message
> news:8qfo69$rf4$1@slb7.atl.mindspring.net...
> > Hi Ray,
> >
> > VHDLStudio is only required to run the included HC11 debugger.  The core
> is
> > in standard VHDL which can be simulated and synthesized with any
standard
> > tool.
> >
> > Regards,
> > --Scott Thibault
> > Green Mountain
> > Computing Systems, Inc.
> >
>     Scott has some nice code here, but low-end tools like Warp choke
> on several parts of it. I want to like Warp, but it just doesn't seem
> to measure up.  Does anyone use it for real projects?
>
> Eric



Article: 25857
Subject: Re: CORDIC COS/SIN with FPGA implementation
From: Ray Andraka <ray@andraka.com>
Date: Sat, 23 Sep 2000 01:14:31 GMT
Links: << >>  << T >>  << A >>
Sounds like you missed the mark on the shifter.  An 8 bit barrel shift (fully
populated) should occupy 24 4-LUTs and should be 3 levels of logic deep.  You
have to implement it, the tools will not infer the correct structure by
themselves.

"default@user.com" wrote:
> 
> I've finally gotten sick of just simulating a CORDIC block, and
> synthesized it to a Xilinx XC4010XL-3 FPGA.  I'm using some fairly
> ancient Xilinx Foundation Series 1.5 software (not even 1.5i.)
> 
> But I've run into a slight snag.  The CORDIC algorithm is supposed to be
> 'fast' thanks to a shift/add iterative cycle (no multiplication.)  I
> synthesized to an Xess XS40-010+ board, and looked at the placement
> report.  To my surprise, roughly 50% of the CORDIC's area is consumed by
> the arithmetic-right-shifter.  Is this correct?!?  The CORDIC block
> works, but the resource-consumption was way way over my estimate.  (I
> admit I have *no* prior experience with FPGA.)  In short, my 8-bit
> CORDIC block + VGA-display circuit consume 96% of the XC4010XL's CLBs.
> 
> My cordic block uses a single 8-bit adder (with muxes on each input to
> rotate between the X,Y,Z accumulators.)  The inputs and outputs on the
> adder are registered, of course.  With some pipelining, the adder is
> never idle.  Here's where the shifter sits :
> 
> |  X or Y  |                                         | adder input|
> | register | ---? arithmetic shifter -? XOR-array -? | register   |
> 
> (The XOR-array is used to implement subtraction.)
> The shifter itself has 8-bit data input and output.  A 3-bit 'rotate'
> word specifies the #bits to right-shift.  The upper bits are filled with
> 0 or 1, depending on the input-data's sign (MSB.)  The shifter is
> entirely combinational logic.
> 
> Are FPGA architectures just not efficient at implementing single-cycle
> (barrel) arithmetic-shifters?
> 
> I'm about ready to redo the shifter using a shift-register + counter
> (sequentil logic implementation.)  This maps better, but takes
> multiple-cycles to compute.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25858
Subject: PDP-11
From: K.J. Seefried III <kseefried@digitalmojo.com>
Date: Sat, 23 Sep 2000 02:46:04 GMT
Links: << >>  << T >>  << A >>

Has anyone, other than Mentec, done a custom circuit based on the
PDP-11?

Ken Seefried, CTO & Founding Partner, DigitalMoJo
Information Security Management, Consulting & Training
Article: 25859
Subject: Re: GPS design with xilinx board
From: Jonas Thor <NoSpamthor@sm.luth.seNoSpam>
Date: Sat, 23 Sep 2000 08:56:26 +0200
Links: << >>  << T >>  << A >>
Could you be a be more specific about what you are trying to do? Do
you have a GPS front-end hooked up to your FPGA board and use the FPGA
as a GPS correlator? Are you performing only acquisition with the FPGA
or are you also closing the tracking loops (code and carrier)?

/ Jonas Thor

On Tue, 19 Sep 2000 22:09:27 GMT, jing_pang@my-deja.com wrote:

>I'm doing GPS design using xilinx board. After modulating C/A code with
>navigation data using BPSK technique, I tried to mix the signal with
>L1 carrier signal. But in the spectrum analyzer, I observed a big spike
>in the center of L1 frequency. Does anybody has some idea how can I get
>rid of it?
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.

Article: 25860
Subject: Re: Announce: Free HC11 CPU Core
From: eddy_bobby@my-deja.com
Date: Sat, 23 Sep 2000 07:01:44 GMT
Links: << >>  << T >>  << A >>
Hi

 Many thanks to your amazing tribute to VHDL related people.

 I have compiled your HC11, last night,with my MTI/PE and
leonardo and found the code really *fit* into a single chip
of Flex10KE-100-1 via maxplus2(v9.6) at 17MHz clock rate
*without any additional tuning* efforts.

 Now I am very curious if your VHDLStudio can handle edif
or .vho backannotation simulation better than MTI (^^?
( In terms *better*, I meant for simulation time. )
Do you have some benchmarks on your Web? (I could not find yet)

 If the products are intended to replace *both* MTI and leo,
I would like to study your products much deeply so that to
reduce my previous annual maintenance fees.

Best Regards.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25861
Subject: dp ram
From: "Daniel Nilsson" <danielnilsson@REMOVE_THIShem3.passagen.se>
Date: Sat, 23 Sep 2000 14:08:03 +0200
Links: << >>  << T >>  << A >>
I will use a fpga to control a controllerless lcd, and a 32k*8 sram to store
graphic data, I want this thing to look just lika a sram to the cpu. How do
I manage this without using expensive dp ram or too big fpga (not bigger
than a 84 pin plcc socket)? (some waitstates sometimes aren't that
dangerous)



Article: 25862
Subject: Category : why is 0?
From: ChenSongWei <chen.songwei@mail.zte.com.cn>
Date: Sat, 23 Sep 2000 05:52:12 -0700
Links: << >>  << T >>  << A >>
Hi:
  Now, i am doing "16bits converting 64bits fifo" of four channels ,my application is to write a lot of data to a fifo first by polling ,and then read it from the fifo by polling, my design is:
  the input data is 16 bits width,and use four 16 bits latches and 2 bits counter,the data is sent into 64 bits fifo when counter==2'b11.And then i will transfer it at the top level,if i write and read only a certain fifo ,the data of being read is correct.However,when i switch channel,the reading first data is 0 from the switched channel.Obviously ,the "0" of 64 bits is excrescent,but the  back data is correct,that is ,it reads a "0" more.the phenomena happens only switching channel.
 why?
Article: 25863
Subject: Re: Bluetooth core??
From: Lasse Langwadt Christensen <Langwadt@ieee.org>
Date: Sat, 23 Sep 2000 16:08:59 +0200
Links: << >>  << T >>  << A >>


khatib@ieee.org wrote:
> 
> Hi,
> Me and some young engineers (students and non-students) like get more
> practice in digital design by doing a real design.
> We found that the bluetooth technology is a new technology and may have
> good future even in a home made systems.
> 
> Could you please help us on the following questions:
> 1. Is there any avialable cores for this technology that we can learn
> from?
> 2. how large is this core going to be?
> 3. where can I find information about implementing it?
> 4. can a group of 3 young engineers work on it?
> 5. Is ther any possibility to implement a device at home with this core?
> 6. can we implement it on FPGA?
> 7. Does it worth the time or should we look for another technology to
> learn from?
> 
> Thanks in advance
> Jamil Khatib
> 

I don't know if there's any Bluetooth cores available, though there's 
plenty of powerpoint presentations out there :)   

but you could have a look at the datasheet for the LMX5001 bluetooth 
chip (National semiconductor), it only implements the stuff 
that _has_ to be done in HW the rest is handled in SW.
You can download the bluetooth specs at www.bluetooth.com, and see 
what's needed. It can definately be implemented in an FPGA, but even 
with a chip that can handle all the timing HEC,FEC and CRC
encoding/decoding 
you'll need atleast some of the higher protocol layers to get the
rest of the way.

 
--Lasse 
(+)--------------------------(+)
 | Lasse Langwadt Christensen |
 | Aalborg, Denmark           |  
(+)--------------------------(+)

Article: 25864
Subject: Re: dp ram
From: Ray Andraka <ray@andraka.com>
Date: Sat, 23 Sep 2000 14:46:09 GMT
Links: << >>  << T >>  << A >>
You hang a relatively cheap 32Kx8 SRAM on a small FPGA.  Use the FPGA to
effectively dual port and to implement the LCD controller.  It's a 2 chip
solution that's much cheaper than using a larger FPGA just to get the memory.  A
pretty fancy controller will fit in a 4013 (XCS30).  You do need to watch that
you drive the LCD with true 50% duty cycle signals with alternating polarity. 
Any DC offset will destroy the LCD in short order (hint, use two I/Os and use
the difference between them to drive the LCD).  Your FPGA will have the memory
scanning and LCD timing, which is mostly counters and muxes. 

Daniel Nilsson wrote:
> 
> I will use a fpga to control a controllerless lcd, and a 32k*8 sram to store
> graphic data, I want this thing to look just lika a sram to the cpu. How do
> I manage this without using expensive dp ram or too big fpga (not bigger
> than a 84 pin plcc socket)? (some waitstates sometimes aren't that
> dangerous)

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25865
Subject: Re: Reassurance on Xilinx Sought
From: z80@ds2.com (Peter)
Date: Sat, 23 Sep 2000 15:57:08 +0100
Links: << >>  << T >>  << A >>

>Sounds like you didn't pay any attention whatsoever as to the chip architecture,
>and you attempted to let the tools do everything without any tailoring for a
>cheaper, faster, better implementation.

I think you are correct - this, however, is what a lot of people are
led to believe they can do. And it can be done, if one goes nowhere
near the device limits.

Also if doing e.g. ASIC prototyping, the last thing you want to do is
get involved in the FPGA architecture - you are mostly trying to prove
the design is functionally OK.


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 25866
Subject: Re: hardware compatibility and patent infringement
From: gneuner@dyn.SPAMMERS.DIE.com (George Neuner)
Date: Sat, 23 Sep 2000 17:03:49 GMT
Links: << >>  << T >>  << A >>
On Thu, 14 Sep 2000 14:46:01 -0500, Robert Posey
<muddy_take_out_this@raytheon.com> wrote:

>It not legal, but it should be legal to patent algorithms ...

What's legal is whatever the patent office allows under its
interpretation of the laws passed by Congress ... and they now allow
algorithms to be patented.


>There should be no threat of people patenting
>existing algorithms, since unless a person can prove they invented something
>first and started the patent process with reasonable dispatch, the patent
>is invalid.  So I can't patent Quick Sort and A*, there goes that easy
>trillion bucks.  

The patent office is *required* to grant the application unless the
examiner can find significant *published* prior art which disqualifies
it.  The examiner is *not* required to make an exhaustive search -
only a "reasonable" one.

One problem is that much prior art in software is either trade secret,
research or oral tradition - trade secrets and oral tradition are not
typically published, and the examiners typically disregard research
publications because there is no working implementation.

The result is that patents are granted for applications and processes
that everyone is already aware of because the examiner could not
readily discover and document the prior art.


>Until Americans acknowledge that the Government needs truly qualified people
>and that to get them will cost real money these problems will continue.  You
>can't expected an agency forced to staff its offices with engineers that
>are paid 20-30% less than private industry, and got C's in school to be
>able to monitor the volume of patent applications they receive.

The patent office is staffed mostly with wannabe patent attorneys.
Being a clerk or an examiner can be a good step towards a more
lucrative career.

The real problem is the procedure.  Applications should not be secret,
opponents should have the right to challenge with prior art before the
patent is granted.  This is the rule in many countries and it helps
prevent their patent offices from being flooded with frivilous claims.



Disclaimer: I am not a patent attorney ... my father, sister and about
a dozen family friends are.


George

Article: 25867
Subject: Re: hardware compatibility and patent infringement
From: "Kevin Aylward" <kevinanaylward@home.com>
Date: Sat, 23 Sep 2000 17:32:07 GMT
Links: << >>  << T >>  << A >>
"George Neuner" <gneuner@dyn.SPAMMERS.DIE.com> wrote in message
news:39ccdcf9.837101979@helice...
> On Thu, 14 Sep 2000 14:46:01 -0500, Robert Posey
> <muddy_take_out_this@raytheon.com> wrote:
>

> The patent office is staffed mostly with wannabe patent attorneys.
> Being a clerk or an examiner can be a good step towards a more
> lucrative career.
>

Such as inventing the Special and General Theory of Relativity

Kevin Aylward , Warden of the Kings Ale
kevin@anasoft.co.uk
http://www.anasoft.co.uk - SuperSpice "Cheap, No Shit!", a currently free
GUI xspice, unlimited component, mixed-mode Windows simulator with Schematic
Capture, waveform display, FFT's and Filter Design.
Opinions of my employer are not necessarily indicative of my own
Oscillators don't, amplifiers do"


Article: 25868
Subject: Re: memory interface trouble...
From: "Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Sat, 23 Sep 2000 22:18:21 +0200
Links: << >>  << T >>  << A >>
Hi,

"tim simpson" <tim@nospam.monster-works.co.nz> schrieb im Newsbeitrag
news:969667386.576506@Chaos.es.co.nz...
> > Even during configuration, the pins may be pulled High ( perhaps
> > even Low) by a weak internal resistor, since nobody likes floating
> > inputs. Maybe the uP reacts to these logic levels...
>

ALTERA has weak pull up resistors on their I/O Pins, which
are active when the FPGA is not configured (C167CR could be
configured by Bootstrap Loader) and which are activated for
tri-state I/O Pins.
I've tested them by trying to force 5V and 0V with a 100KOhm
resistor. The pin stays on the voltage, which was applied
by this 100K resistor, thus I really would say these Pins are
tristated...



Article: 25869
Subject: Re: memory interface trouble...
From: "Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Sat, 23 Sep 2000 22:21:43 +0200
Links: << >>  << T >>  << A >>
Hi Peter,
thanks for your answer.

"Peter Alfke" <peter.alfke@xilinx.com> schrieb im Newsbeitrag
news:39CBC534.F5257A27@xilinx.com...
> As you knoe, I don't work for Altera, but anyhow:
>
> Most FPGA pins are 3-stated during configuration. What happens right
> after the completion of configuration is up to you, the designer.
>

ALTERA has weak Pull-Ups on the I/O Pins, which are active during
configuration and for Tri-State Pins.
It's just curious, that the uP would react on it, as the according
configuration Pin to detect the BootstrapLoader Mode isn't affected
by the FPGA at all (with configured an unconfigured FPGA 100mV...)

CU, CS


Article: 25870
Subject: Re: Reassurance on Xilinx Sought
From: Ray Andraka <ray@andraka.com>
Date: Sat, 23 Sep 2000 22:43:09 GMT
Links: << >>  << T >>  << A >>


Peter wrote:
> 
> ?Sounds like you didn't pay any attention whatsoever as to the chip architecture,
> ?and you attempted to let the tools do everything without any tailoring for a
> ?cheaper, faster, better implementation.
> 
> I think you are correct - this, however, is what a lot of people are
> led to believe they can do. And it can be done, if one goes nowhere
> near the device limits.

In which case you are most likely paying for alot more device than you need.  If
your required data rates are low, you can often take advantage of bit serial
arithmetic to get the same performance in a much smaller area.  It is not
uncommone to be able to reduce several sizes, for example from an XCV400 downto
an XCV50.

> 
> Also if doing e.g. ASIC prototyping, the last thing you want to do is
> get involved in the FPGA architecture - you are mostly trying to prove
> the design is functionally OK.

This is the cover many people throw up, and I think it is a bit of a fallacy. 
FPGA design is more restrictive than ASIC design.  If you are doing an ASIC
emulation, then sure it makes sense (the asic emulation is a gate level
emulation of the ASIC design, typically clocked at a reduced clock rate in order
to meet timing in an FPGA that has been very inefficiently utilized.  On the
otherhand, if you are putting the FPGA into early production with the intention
of replacing it later with an ASIC (which from what I 've seen, does not really
happen any where near as often as it is planned), I think you are better off
doing a design tailored to the FPGA for two reasons.  First, it holds down the
cost of the initial units, and if you don't make the ASIC as soon as you planned
(or ever), you  haven't lost anything.  From there, it is quite a bit easier to
make an ASIC from a design tailored to an FPGA than the other way around. 
Personally I think you get the best bang for the buck by doing a redesign for
the ASIC if and when the time comes.

> 
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25871
Subject: Re: memory interface trouble...
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 24 Sep 2000 02:31:37 GMT
Links: << >>  << T >>  << A >>


Carlhermann Schlehaus wrote:

> ALTERA has weak pull up resistors on their I/O Pins, which
> are active when the FPGA is not configured (C167CR could be
> configured by Bootstrap Loader) and which are activated for
> tri-state I/O Pins.
> I've tested them by trying to force 5V and 0V with a 100KOhm
> resistor. The pin stays on the voltage, which was applied
> by this 100K resistor, thus I really would say these Pins are
> tristated...

What you descibe is not tristate, but rather a weak latching action ( we
at Xilinx call it "weak keeper") which prevents floating inputs and
undefined levels, but does not guarantee a specific logic level. As you
describe it, the pin becomes either a 1 or a 0, depending on the last
drive, internal or external.

Peter Alfke



Article: 25872
Subject: Looking for Long Island Verilog or VHDL designers
From: "Barry Schneider" <barry61s@worldnet.att.net>
Date: Sun, 24 Sep 2000 02:53:36 GMT
Links: << >>  << T >>  << A >>
I am presently working at a ASIC consulting company and am extremely over
worked.  We need help and will pay well.  We have a great office and have
very flexible hours.  If you are interested in a Good Job e-mail me at
barry61s@att.net.   Hope to hear from you.

                        Sincerely,
                                        Barry




Article: 25873
Subject: Re: CORDIC COS/SIN with FPGA implementation
From: "default@user.com" <default@user.com>
Date: Sat, 23 Sep 2000 20:21:42 -0700
Links: << >>  << T >>  << A >>
> Sounds like you missed the mark on the shifter.  An 8 bit barrel shift (fully
> populated) should occupy 24 4-LUTs and should be 3 levels of logic deep.  You
> have to implement it, the tools will not infer the correct structure by
> themselves.

Hi, the Xilinx XC4xxx library (the library that comes with Foundation
1.5) includes an 8-bit barrel shifter.  I played around with this macro,
and have concluded its more like a 'bit rotater.'  Opening the macro in
the schematic editor indeed shows 24 2:1 muxes, arranged as 8bits x
3deep.

The block in question, however, is an ARITHMETIC shifter.  I guess you
could call it a barrel-shifter + sign-extender.  I did a bit of
preliminary work writing structural verilog (before, I had a for-loop
inside an always@() block), the structural verilog implementation
ultimately synthesized to the same bloated FPGA map.  

I'll go and try it again, though.  My structural verilog did not use any
kind of 'barrel' structure (bit-rotate), so that's the next thing to
try.

> 
> "default@user.com" wrote:
> >
> > I've finally gotten sick of just simulating a CORDIC block, and
> > synthesized it to a Xilinx XC4010XL-3 FPGA.  I'm using some fairly
> > ancient Xilinx Foundation Series 1.5 software (not even 1.5i.)
> >
> > But I've run into a slight snag.  The CORDIC algorithm is supposed to be
> > 'fast' thanks to a shift/add iterative cycle (no multiplication.)  I
> > synthesized to an Xess XS40-010+ board, and looked at the placement
> > report.  To my surprise, roughly 50% of the CORDIC's area is consumed by
> > the arithmetic-right-shifter.  Is this correct?!?  The CORDIC block
> > works, but the resource-consumption was way way over my estimate.  (I
> > admit I have *no* prior experience with FPGA.)  In short, my 8-bit
> > CORDIC block + VGA-display circuit consume 96% of the XC4010XL's CLBs.
> >
> > My cordic block uses a single 8-bit adder (with muxes on each input to
> > rotate between the X,Y,Z accumulators.)  The inputs and outputs on the
> > adder are registered, of course.  With some pipelining, the adder is
> > never idle.  Here's where the shifter sits :
> >
> > |  X or Y  |                                         | adder input|
> > | register | ---? arithmetic shifter -? XOR-array -? | register   |
> >
> > (The XOR-array is used to implement subtraction.)
> > The shifter itself has 8-bit data input and output.  A 3-bit 'rotate'
> > word specifies the #bits to right-shift.  The upper bits are filled with
> > 0 or 1, depending on the input-data's sign (MSB.)  The shifter is
> > entirely combinational logic.
> >
> > Are FPGA architectures just not efficient at implementing single-cycle
> > (barrel) arithmetic-shifters?
> >
> > I'm about ready to redo the shifter using a shift-register + counter
> > (sequentil logic implementation.)  This maps better, but takes
> > multiple-cycles to compute.
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
Article: 25874
Subject: Xilinx Student Edition 2.1i with "Digital Design:Principles and
From: Guest Internet User <INVALID@INVALID.NET>
Date: Sat, 23 Sep 2000 20:30:46 -0700
Links: << >>  << T >>  << A >>
I was in Irvine ScitechBooks, today, looking for Xilinx Student Edition
2.1i.  (The website www.scitechbooks.com doesn't show it as stocked, but
I've learned from the retail store workers that the website and store
inventory are separate entities.)  I came across Wakerly's "Digital
Design:Principles and Practices" (third edition, ISBN: 0137691912)

The book was bundled with Xilinx Student Edition 2.1i.  I was surprised
to see 2.1i bundled with a book published back in 1999, but the pricetag
sticker showed a date code of '09/00' (meaning Scitech
received/processed it this month.)  The book was shrinkwrapped so I
couldn't even open it, but the back of the book had a blue cardboard
envelope package labeled "Xilinx Student Edition 2.1."

Does anyone know if this is the same software as the standalone Xilinx
Student Edition 2.1i by Prentice Hall?  Seems like the standalone
package is hard to find.


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