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Messages from 25750

Article: 25750
Subject: Re: Safe voltage regulator for Xilinx XC2S150 part?
From: erika_uk@my-deja.com
Date: Tue, 19 Sep 2000 09:47:32 GMT
Links: << >>  << T >>  << A >>
hey,

quiet often, when i read papers from the VLSI field, the power is one
of the big factors taken into account to evaluate the performance of a
design.

I have never seen a technical report taking into account this factor
from the FPGA world designers. They just concentrate on speed and area

why that?

In article <tBox5.16556$Lu3.301835@east7.usenetserver.com>,
  "Gary Watson" <gary2@nexsan.com> wrote:
> I know it's difficult to predict the power requirements of Xilinx
parts, but
> what's a safe 2.5V regulator to use for the internal supply of a
XC2S150?
> The data sheet is most unhelpful in figuring this out.  Since I plan
to roll
> out this product in phases over the next year, I can't say what all my
> internal logic might be doing down the road, so I'm happy to over-
spec the
> regulator to a reasonable degree.
>
> By the way, I'm getting quoted over 10 UK pounds ($14) for the config
prom
> for this puppy (XC18V01S20C).  Is there a cheaper way to do this?
This prom
> increases the cost of using a Spartan II by 50%!
>
> --
>
> Gary Watson
> gary2@nexsan.com
> Nexsan Technologies Ltd.
> Derby DE21 7BF  ENGLAND
> http://www.nexsan.com
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25751
Subject: Re: hardware compatibility and patent infringement
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Tue, 19 Sep 2000 11:49:17 +0200
Links: << >>  << T >>  << A >>

If you use the following axioms:
1) An interrupt must not destroy the CPU context.
2) The processor must not hang due to bus error signals (unless double
fault)
3) The processor must not ignore bus errors and continue execution.
4) MMU page faults must not hang the CPU nor be ignored.

To that you add the following architecture features (which are not patented
by ARM)
* The interrupt handling in performed in S/W instead of hardware
* Use registers to save the return address/PSR

The ARM implementation becomes obvious in my opinion.

-------
Assume that the interrupt vector gets corrupted and points out
in non existing memory.

At the interrupt time, the ARM will save some register in internal
registers,
jump to the bad location and get a bus error.
This happens before the CPU has saved the internal registers on the
interrupt stack.
It is obvious that the CPU cannot save the new pc into the return address
register
because then axiom 1 is violated (context destroyed).
It must take the bus error trap, or violating axiom (2 ,3).
The trap needs to store the current PC/PSR somewhere so additional
resources are needed.
They have basically two alternatives, implement a H/W stack for registers
or dedicate registers for the bus error trap, interrupts or whatever.
I doubt that selecting one of them should be patentable.

--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden



Article: 25752
Subject: Re: Xilinx Web Pack
From: korthner@hotmail.nospam.com (K. Orthner)
Date: 19 Sep 2000 10:51:35 GMT
Links: << >>  << T >>  << A >>
Rick,

Instead of specifying "c:\Program Files",try "c:\progra~1".

Since Win95/98 etc, is still just a hack on top of DOS, it still conforms 
to the 8.3 filename system.  if you open a DOS shell and type DIR, you'll 
see that the "expanded" name is "Program Files", but the real name is 
"Progra~1", or something similar.

Microsoft could of made all of lives a h*ll of a lot easier by choosing a 
default pathname without a space.  Almost every command line tool known to 
Man (and Woman) has problems with spaces in filenames.

-kent


>rickman wrote:
>> The first problem I had was the fact that the install did not seem to
>> handle properly the path in the shortcut as I put it under the "Program
>> files" directory and it needed quotes around it to be able to
>> incorporate the space in the path.

Article: 25753
Subject: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Tue, 19 Sep 2000 11:05:38 GMT
Links: << >>  << T >>  << A >>
Of course, anyone can look at the printouts and analyze the differences.
But what would be nice, as the thread has suggested/concluded, is to have
everything in one easy location, i.e., an app note.  Why search every nook
and cranny of the Xilinx web site looking for every difference when it can
be found in one document?
-Simon Ramirez, Consultant
 Synchronous Design, Inc.

This is my opinion, necessarily my employer.  I also hate spam.

"Hal Murray" <murray@pa.dec.com> wrote in message
news:8q5v5p$dv8@src-news.pa.dec.com...
>
> [Slightly sorry for beating a dead horse.]
>
> If the pintouts were available in raw text, it would be
> simple to run diff on the two canidates and see the differences.
>
> --
> These are my opinions, not necessarily my employers.  I hate spam.
>


Article: 25754
Subject: PCB side of this
From: Hawker <Hawker@connriver.net>
Date: Tue, 19 Sep 2000 09:10:24 -0400
Links: << >>  << T >>  << A >>

Thought I would comment on the PCB layout of things.
I use PADS PCB for all my layout.  I have a fancy package with many options
(READ TIME SAVERS) and a 10 years worth of pre-made libraries with many of the
Xilinx parts already made.  What this means is I can turn a board VERY fast
provided 
my client has his/her shit together and is not changing the design on me, has
all there
part data sheets so I don't have to hunt for them etc.

So that said I can turn a decent size PBC rather fast, esp if I already have
most
of the parts in my library.  Options like Cluster Placement, pre-made client
specs etc also speed things up.  While I don't have the specifics of this PCB
Assuming a large Xilinx with a small CPU/DSP some RAM and a few DACs/ADCs and
associated
op-amps like the client mentioned I could probably turn this PCB (including
schematic) in <20 hours.
So from that point it is realistic.

However not in Protell. Protell is a much slower program as it does not have all
the fancies
of PADS and it has data base integrity problems so one has to watch what they
are doing more.

As for Dan's comments about who eats mistakes that is simple.  Here is my
policy.
I give you all net lists to proof.. (Ya'll know how to have a high-lighter party
with
the engineering team right?)  that is your responsibly so a Netlist error
or an error because you did not give me proper information you eat.
An error that I made (like a library mistake, a CAD violation, manufacturability
issue
etc) I eat that.
So basically whoever made the mistake eats the mistake.
By the way I don't believe in the hack it out and get it right the third time
approach,
I try (and usually do) get it right the first time.  I'm more expensive than
some but
I tend to get it right the first time.  

Enough promoting me.. I intended to make a point not look for work.

Dan wrote:
> Not to mention one simple mistake in the PCB schematic that would require a
> second turn; not uncommon. Who eats it ? - New photo plot + new PCB + some
> new parts + time.
>
Article: 25755
Subject: Re: Virtex-E: LVDS vs LVPECL
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Tue, 19 Sep 2000 11:07:24 -0700
Links: << >>  << T >>  << A >>
I believe that using LVDS would reduce system power (the LVPECL pulldown resistors
burn a fair amount) and also reduce noise and EMI due to the reduced signal swing
(0.35V v.s. ~1V for LVPECL). If the driver slew rate is fixed and the required
signal swing is reduced, faster signaling rates (or better timing margins) should be
possible. You would need to check Xilinx's driver models and suggested termination
schemes to see how significant the differences might be. If it's just a couple
of signals, LVPECL might be easiest, but a wide bus could be something else entirely.

regards, tom

Hal Murray wrote:
> 
> LVDS needs 2.5V on Vcco.  LVPECL uses 3.3.
> 
> Suppose you want to get bits from a Virtex-E on one card
> through a cable to a Virtex-E on another card and you
> control both ends of the design.  Is there any reason
> to prefer LVDS or LVPECL signaling?
> 
> Is there any reason not to use LVPECL and avioid the extra
> power level if you don't have any other need for 2.5V?
> 
> --
> These are my opinions, not necessarily my employers.  I hate spam.

 
Tom Burgess
-- 
Digital Engineer
Dominion Radio Astrophysical Observatory
Penticton, B.C.
Canada V2A 6K3
Article: 25756
Subject: An Online Course for CPLD and FPGA design
From: "Shai Gilat" <shai@chalknet.com>
Date: Tue, 19 Sep 2000 11:36:10 -0700
Links: << >>  << T >>  << A >>
Hey, I just found this cool course for CPLD and FPGA design. It's online and
self-paced. It provides an excellent foundation for experienced engineers
who want to start their first CPLD or FPGA design. Also, engineers who have
done several designs in the past can get valuable knowledge for their
current design methodologies. The name of the course is "Introduction to
CPLD and FPGA Design," and if it sounds interesting, you can find it on
www.chalknet.com. The instructor is an IEEE award winning engineer and
sounds like he knows what he is talking about.

Shai


Article: 25757
Subject: Re: Xilinx Web Pack
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 19 Sep 2000 14:43:12 -0400
Links: << >>  << T >>  << A >>
"Tobias F. Garde" wrote:
> 
> rickman wrote:
> >
> > I am trying to get the Xilinx Web Pack up and running on my machine and
> > am having trouble.
> >
> > The first problem I had was the fact that the install did not seem to
> > handle properly the path in the shortcut as I put it under the "Program
> > files" directory and it needed quotes around it to be able to
> > incorporate the space in the path.
> >
> > The next problem I have is trying to access the help. Many of the items
> > in the help window cause errors like "Can not find or run the program or
> > file 'dkxilinx.hlp'". It also could not find a current version (or any
> > for that matter) of "hhcntl.ocx".
> >
> 
> Rick,
> 
> The problems may still be related to your - very unorthodox :) - choice
> of install path for the Xilinx S/W. Even though the installer accepts a
> path with spaces in it, the S/W does not necessarily support it. I had
> that problem when installing the 3.1i S/W.
> 
> I recommend that you check if the missing files are actually present on
> your system. If this is the case, an uninstall followed by a new install
> to the default path may do the trick. BTW, in my case, the uninstall was
> a bit difficult, because the uninstall info could not be found due to
> the spaces in the path...
> 
> Tobias F. Garde
> ASIC Development Engineer
> Tellabs Denmark A/S

I understand that. In fact I gave up and tried to uninstall the
software, but the uninstaller has the same problem with the path! So I
just deleted it and installed it in the default directory (which I had
to enter since the new default was to the "Program Files" directory! It
is simply amazing how little QC there is in this stuff. 

But the bottom line is that I still could not get the device types to
show up. So I gave up and reinstalled Foundation 1.5i from an old job I
had done a couple years back. That runs, but it won't let me synthesize
my VHDL. So I am back to square one. At least I can syntax check the
code. 

I expect my customer to provide a copy of the current tools at which
point I will be able to get Xilinx involved (assuming they even talk to
you on the phone anymore). 

I guess I could try to talk the customer into using the Lucent parts. At
least I can get the tools to work in less time than it takes to get the
design to work. 

Don't mind me, I am just frustrated. I'll be ok tomorrow.  :-(


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 25758
Subject: Re: Xilinx Web Pack
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 19 Sep 2000 14:45:21 -0400
Links: << >>  << T >>  << A >>
That includes the Windows tools themselves. One of the problems I found
was that the install script entered the shortcut command line with the
spaces. Because they did not enclose the path in quotes, the parser quit
at the space and could not find the program. 


"K. Orthner" wrote:
> 
> Rick,
> 
> Instead of specifying "c:\Program Files",try "c:\progra~1".
> 
> Since Win95/98 etc, is still just a hack on top of DOS, it still conforms
> to the 8.3 filename system.  if you open a DOS shell and type DIR, you'll
> see that the "expanded" name is "Program Files", but the real name is
> "Progra~1", or something similar.
> 
> Microsoft could of made all of lives a h*ll of a lot easier by choosing a
> default pathname without a space.  Almost every command line tool known to
> Man (and Woman) has problems with spaces in filenames.
> 
> -kent
> 
> >rickman wrote:
> >> The first problem I had was the fact that the install did not seem to
> >> handle properly the path in the shortcut as I put it under the "Program
> >> files" directory and it needed quotes around it to be able to
> >> incorporate the space in the path.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 25759
Subject: Re: Safe voltage regulator for Xilinx XC2S150 part?
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 19 Sep 2000 14:48:16 -0400
Links: << >>  << T >>  << A >>
I suspect that is somewhat a cyclic dependancy. No one can get any real
data on power consumption until the circuit is built (if then). So there
are not many designers who use that as a metric. Since it does not show
up as a metric, no one writes software to evaluate it. 

Of course there are some crude tools that will let you enter your
circuit parameters to estimate the power consumption, but none tie into
the design directly. 


erika_uk@my-deja.com wrote:
> 
> hey,
> 
> quiet often, when i read papers from the VLSI field, the power is one
> of the big factors taken into account to evaluate the performance of a
> design.
> 
> I have never seen a technical report taking into account this factor
> from the FPGA world designers. They just concentrate on speed and area
> 
> why that?
> 
> In article <tBox5.16556$Lu3.301835@east7.usenetserver.com>,
>   "Gary Watson" <gary2@nexsan.com> wrote:
> > I know it's difficult to predict the power requirements of Xilinx
> parts, but
> > what's a safe 2.5V regulator to use for the internal supply of a
> XC2S150?
> > The data sheet is most unhelpful in figuring this out.  Since I plan
> to roll
> > out this product in phases over the next year, I can't say what all my
> > internal logic might be doing down the road, so I'm happy to over-
> spec the
> > regulator to a reasonable degree.
> >
> > By the way, I'm getting quoted over 10 UK pounds ($14) for the config
> prom
> > for this puppy (XC18V01S20C).  Is there a cheaper way to do this?
> This prom
> > increases the cost of using a Spartan II by 50%!
> >
> > --
> >
> > Gary Watson
> > gary2@nexsan.com
> > Nexsan Technologies Ltd.
> > Derby DE21 7BF  ENGLAND
> > http://www.nexsan.com
> >
> >
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 25760
Subject: Re: PCB side of this
From: Ray Andraka <ray@andraka.com>
Date: Tue, 19 Sep 2000 19:52:31 GMT
Links: << >>  << T >>  << A >>
Exactly.  Now add the effort to needed to get"his/her shit together", collecting
the data sheets, and preparing the package for you, and yellow-lining the
netlist when you are done.  Now you are over the 30-40 hours and you haven't
accounted for even 1 hour of design time.  Throw in on top of that any board
layout issues for noise, high speed clocks, decoupling etc, and I think for all
but the simplest boards you are going to be pushing the 30-40 hours yourself. 
Don't forget the effort to generate all the gerbers, interfacing to a fab house
etc.   

Hawker wrote:
> 
> Thought I would comment on the PCB layout of things.
> I use PADS PCB for all my layout.  I have a fancy package with many options
> (READ TIME SAVERS) and a 10 years worth of pre-made libraries with many of the
> Xilinx parts already made.  What this means is I can turn a board VERY fast
> provided
> my client has his/her shit together and is not changing the design on me, has
> all there
> part data sheets so I don't have to hunt for them etc.
> 
> So that said I can turn a decent size PBC rather fast, esp if I already have
> most
> of the parts in my library.  Options like Cluster Placement, pre-made client
> specs etc also speed things up.  While I don't have the specifics of this PCB
> Assuming a large Xilinx with a small CPU/DSP some RAM and a few DACs/ADCs and
> associated
> op-amps like the client mentioned I could probably turn this PCB (including
> schematic) in <20 hours.
> So from that point it is realistic.
> 
>
-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25761
Subject: Re: Freelance Designer Needed: Protel & FPGA
From: artaaron@my-deja.com
Date: Tue, 19 Sep 2000 21:13:51 GMT
Links: << >>  << T >>  << A >>
In my experience it takes an incredibly well defined project
to even consider a fixed price contract.  And without some
knowledge of the market and the company itself the revenue off
of sales is a crap shoot. Doesn't seem to make a lot of sense
with the money that can be made elsewhere in this job market but
maybe there's more details that we don't know about.

- Arthur Aaron


In article <39C6C3B8.5F7F1360@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
> There ain't much info here as to what is in the FPGA, or even how big
a device
> it is.  The FPGA design and verification alone could take as much as
10X or more
> of his estimated 30-40hours.  I think the board layout alone, given a
complete
> and verified netlist could be more than the 30-40 hours (check with a
layout
> house if you don't believe me).  For the pricing, I am always leery
of projected
> volumes, especially if such a large percentage of the income is to be
based on
> it.  If the company tanks, or he only manages to sell one or tow
boards or if
> the project gets scrapped, the consultant/contractor is working for
about $50/hr
> (assuming the hours are met), which is quite low (I don't think you
can get warm
> bodies to fill seats on your location for that anymore, and if you
did you'd
> spend more than the 40 hours just getting them up to speed)
>
> That said, the DDS function could easily be incorporated into the
FPGA.
>
> "S. Ramirez" wrote:
> >
> >      Does anyone in this newsgroup realistically think that they
can do the
> > work below in 30-40 hours?  Of course I would have to inquire to
find out
> > the details in order to make an estimate of what is really
required.  But
> > just reading what this company wants, I see four main tasks: 1)
design and
> > schematic capture of the board, 2) design and HDL/schematic capture
of the
> > FPGA, 3) simulation of maybe the board and certainly the FPGA, and
4) lab
> > testing/debug.  I personally do not think that I can do all of the
above
> > tasks in 30-40 hours.
> >     At least they have a detailed block diagram.
> >     How about yous guys/gals?  Can anyone do this work based on
what's
> > written below?
> > -Simon Ramirez, Consultant
> > -Synchronous Design, Inc.
> >
> > "Walt" <walt_white@southwestsoftware.com> wrote in message
> > news:v98x5.31686$I6.182833@news1.rdc1.az.home.com...
> > > Hello,
> > >
> > > We are looking for a freelance designer who can help us develop a
> > > daughterboard module.  This work will involve the schematic
capture and
> > > layout of the PCB in (preferably in Protel), and the programming
of the
> > > SpartonII FPGA.  The hardware design will be based on a detailed
block
> > > diagram of the board that we provide, along with some key part
numbers and
> > > other needed information.   The board includes some A/Ds, D/As
and a DDS.
> > > The work should take between 30 to 40 hrs and can be done at your
> > location.
> > >
> > > The project deliverables will be Protel design files, the FPGA
design
> > files,
> > > and any documentation used to create the design.  All rights and
claims to
> > > any work on this project at all times is unequivocally the
property and
> > > intellectual property in origin and by any extension with all
rights and
> > > privileges reserved to Southwest Software & Systems LLC (3S).
> > >
> > > Payment for the work will be a flat fee of $2000.00 plus a
royalty of 5.0%
> > > of the sale price for each board, and the boards will sell about
$675ea
> > and
> > > volume is expected to be a few hundred (For example, assuming a
200 board
> > > volume, the total payment for the hardware design would be:
$2000.00 +
> > 0.05
> > > x $675.00/Board x 200Boards = $8,750).  Additionally, there could
be
> > similar
> > > follow-up designs.
> > >
> > > If you are interested and qualified to do this work, please
contact me as
> > > soon as possible, we are ready to begin immediately.
> > >
> > > Regards,
> > >
> > > Walt White
> > > Southwest Software & Systems LLC
> > > www.southwestsoftware.com
> > >
> > >
> > >
> > >
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25762
Subject: VHDL to SCHEMATIC
From: erika_uk@my-deja.com
Date: Tue, 19 Sep 2000 21:29:10 GMT
Links: << >>  << T >>  << A >>
hi,

can F2.1i generate the schematic from vhdl (or edif) entry.
If no, is there any tool which does so

Regards

--Erika




Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25763
Subject: Re: VHDL to SCHEMATIC
From: erika_uk@my-deja.com
Date: Tue, 19 Sep 2000 21:31:10 GMT
Links: << >>  << T >>  << A >>
sorry, i wanted to say edif .

In article <8q8lqb$iu3$1@nnrp1.deja.com>,
  erika_uk@my-deja.com wrote:
> hi,
>
> can F2.1i generate the schematic from vhdl (or edif) entry.
> If no, is there any tool which does so
>
> Regards
>
> --Erika
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25764
Subject: GPS design with xilinx board
From: jing_pang@my-deja.com
Date: Tue, 19 Sep 2000 22:09:27 GMT
Links: << >>  << T >>  << A >>
I'm doing GPS design using xilinx board. After modulating C/A code with
navigation data using BPSK technique, I tried to mix the signal with
L1 carrier signal. But in the spectrum analyzer, I observed a big spike
in the center of L1 frequency. Does anybody has some idea how can I get
rid of it?


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25765
Subject: Re: FPGA Express Strikes Again!
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Tue, 19 Sep 2000 15:14:29 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------82C4CA1B62309F0FBF295C33
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Andy,

I just wanted to update you on this FPGA Express bug.
We already filed a CR (Change Request) and Synopsys is looking into this
issue.

If a Spartan/ 4K design is using both rising  and falling edge clocks, the
clock must be inverted using CLB clock muxes CLKX or CLKY. In IOBs, it is
supposed to use OKMUX. Unfortunately
FPGA Express isn't using these muxes, its using a LUT to invert the clock. A
workaround would be to
instantiate negative edge flops like FDC_1, FDCE_1 etc.


This will be fixed in the future versions of the software.

Vikram Pasham
Xilinx Applications

Andy Peters wrote:

> File this under "bug in v3.4."  Or file it under "FPGA Express is too
> stupid to live."  Or file it under "Why haven't they figured out the
> goddamn architecture yet?"
>
> Here's the scenario.  I'm doing a little experiment.  Target
> architecture is Spartan and 4KXLA; the problem is the same for both.
> Most of my flops are clocked on the rising edge.  One of the things I
> did was to have a handful of flops clocked on the falling edge.
> Normally, placing a period constraint on the clock is all that's
> required; map and p&r should go, "Ah! two-phase clock" and do the right
> thing.
>
> p&r runs, and the report at the end complains that there's skew in the
> design due to something not using a global clock net, and the skew
> wasn't analyzed.  OK, run trace with the skew option.  Ooops -- there's
> a bunch of flops with like 4.8 ns clock skew (100 MHz period constraint)
> and clocked from N1964_BUFGed.  Weird.
>
> Poking around with FPGA Editor (which is really useful when you're
> trying to figure out just what the hell the tools did), turns out that
> N1964_BUFGed is the clock net for the falling-edge clocked flops.  Right
> then, I knew exactly what the problem was:
>
> FPGA Express 3.4 is too stupid to realize that the CLB HAS A
> CLOCK-POLARITY MUX RIGHT IN FRONT OF THE FLOP SO IT DOESN'T NEED TO USE
> A CLB TO INVERT THE CLOCK!  At least it knew enough to route the output
> of the CLB inverter to a BUFGLS, but it's still WRONG.
>
> This is a bug that needs to be fixed PRONTO.
>
> I am going to open a support case at Xilinx just as soon as their web
> site decides it wants come back to life.
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u

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Article: 25766
Subject: GPS design with xilinx board
From: jing_pang@my-deja.com
Date: Tue, 19 Sep 2000 22:23:14 GMT
Links: << >>  << T >>  << A >>
I'm doing GPS design using xilinx board. After modulating C/A code with
navigation data using BPSK technique, I tried to  mix the signal with L1
carrier signal. But in the spectrum analyzer, I observed a big spike in
the center of L1 frequency. Does anybody has some idea how I can get rid
of it?


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Article: 25767
Subject: Re: Bluetooth core??
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Tue, 19 Sep 2000 15:29:35 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Jamil,

Check out the Xilinx "Bluetooth" webpage at
http://support.xilinx.com/products/virtex/wireless/bluetooth.htm

Generally FPGAs are used for implementing some of the Bluetooth components
like Memory controllers,
DSP Filters, Peripherals ( PCI, Co-processor, Protocol processor) etc.

You can also find detailed Bluetooth specs at www.bluetooth.com

Hope this helps.

Vikram
Xilinx Applications

khatib@ieee.org wrote:

> Hi,
> Me and some young engineers (students and non-students) like get more
> practice in digital design by doing a real design.
> We found that the bluetooth technology is a new technology and may have
> good future even in a home made systems.
>
> Could you please help us on the following questions:
> 1. Is there any avialable cores for this technology that we can learn
> from?
> 2. how large is this core going to be?
> 3. where can I find information about implementing it?
> 4. can a group of 3 young engineers work on it?
> 5. Is ther any possibility to implement a device at home with this core?
> 6. can we implement it on FPGA?
> 7. Does it worth the time or should we look for another technology to
> learn from?
>
> Thanks in advance
> Jamil Khatib
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

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--------------9B630FF35197B534808B72AD--

Article: 25768
Subject: Re: virtex shape
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 19 Sep 2000 16:27:36 -0700
Links: << >>  << T >>  << A >>
There was some speculation about the Virtex shape.
Here are the facts:
Physically, most Xilinx chips are close to square, a shape that is
desirable for fitting them into a package.
Physically, the Virtex CLB has a rectangular shape, it is roughly 50%
higher than it is wide.
That's why there are 50% more columns than rows.
( Assuming the conventional view of vertical columns and horizontal rows.
)
Each BlockRAM has a height of four CLBs and a width of about 2.5 CLBs.
So the BlockRAM area is equivalent to the area of about 10 CLBs.
If you do the math, the chip size ends up almost square, but XCV405E and
XCV812E with their huge number of BlockRAMs are oblong.

Remember also that a Virtex CLB has four LUTs and flip-flops, while
Spartan, XC4000 and XC3000 have only two LUTs in their CLB.

Just to satisfy the curiosity...

Peter Alfke, Xilinx Applications



Article: 25769
Subject: Re: timing constraints
From: "Kang Liat Chuan" <kanglc@agilis.st.com.sg>
Date: Wed, 20 Sep 2000 10:09:42 +0800
Links: << >>  << T >>  << A >>
> What excactly do the offset = in and offset = out mean. Do they mean
> that a signal must be valid X ns BEFORE the clock signal arives, and
> that a signal is Y seconds AFTER the clock has arived stable?

This could be useful:
http://support.xilinx.com/support/techsup/journals/timing/presentation/timin
g/noframe/index.htm

Regards,
LC


Article: 25770
Subject: Re: Adders in FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Sep 2000 02:53:41 GMT
Links: << >>  << T >>  << A >>
It is very difficult to beat the performance of the dedicated fast carry chains
in Altera and Xilinx FPGAs using any of the conventional fast carry schemes. 
The fast carry chains have dedicated logic and connections that are roughly an
order of magnitude faster than the general interconnect and logic resources. 
Additionally, by using the fast carry chains in xilinx you are getting the carry
function without using an additional LUT, so the adder is half the size of an
otherwise identical ripple carry adder using the LUTs instead of the fast carry.
More area also generally means slower because the connections have to be made
over longer distances.  When you get into very wide adders (more than 30 bits or
so), then you can start improving on the performance by using the fast carry
schemes to combine segments made up of smaller ripple carry adders.

So for Altera and Xilinx FPGAs the built in ripple carry function is the
smallest and pretty much the fastest.  In devices such as the Atmel parts, the
story is different.  I was part of a group that looked at adders in the Atmel6K
and NSC Clay31 several years back.  The conclusion there was that for small
adders, the ripple carry was still better because of the smaller area and
tighter (read faster) routing.  As the number of bits increased, If memroy
serves me correctly, 8 bits was about where ultimate speed made looking at other
carry schemes attractive.  Charle' Rupp had a scheme he called arithmetic
progression that was pretty compact.  It consisted of progressively longer
ripple adders tied together in a carry scheme.  Actel FPGAs fare reasonably well
with a carry select architecture because it maps efficiently into their logic
element. 

shahzad2512@my-deja.com wrote:
> 
> Different types of adders are available that offer different
> advantages. These adders are:
> Ripple Carry Adders
> Carry lookahead adders
> Carry Select adders
> Conditional Sum adders
> These adders when implemented in FPGAs deliver different performance in
> terms of speed and area. Both these things are critical for FPGAs. I
> implemented a Logiblox 4 bit adder and then implemented CLA adder. CLA
> was equivalent in resources to the logiblox and was faster. But bigger
> CLA consumes more resources than the Logiblox adder. Adders are the
> basic units that are extensively used in many designs.
> Has anyone done a thorough research on which adder is the best for say
> Xilinx FPGA, Altera, Atmel FPGAs. If someone has done a thorough work
> on Adders for  say, Altera FPGAS, it will be worth sharing the
> experience. If someone knows that this topic has been discussed it will
> be helpful to mention the relevant site.
> Regards,
> SHAHZAD
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25771
Subject: Re: Freelance Designer Needed: Protel & FPGA
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Wed, 20 Sep 2000 03:04:02 GMT
Links: << >>  << T >>  << A >>
Not to mention that you would have to trust this company to tell you their
sales and pay you accordingly.  I wouldn't trust a company unless I knew the
principles personally.  I've had to police companies in the past, and it
isn't fun.  Besides, policing adds to the 30-40 hours that they defined.
-Simon Ramirez, Consultant
 Synchronous Design, Inc.


<artaaron@my-deja.com> wrote in message news:8q8ktr$hs1$1@nnrp1.deja.com...
> In my experience it takes an incredibly well defined project
> to even consider a fixed price contract.  And without some
> knowledge of the market and the company itself the revenue off
> of sales is a crap shoot. Doesn't seem to make a lot of sense
> with the money that can be made elsewhere in this job market but
> maybe there's more details that we don't know about.
>
> - Arthur Aaron



Article: 25772
Subject: Re: Good FPGA prototyping boards?
From: "default@user.com" <default@user.com>
Date: Tue, 19 Sep 2000 20:25:52 -0700
Links: << >>  << T >>  << A >>
Thanks for the feedback everyone.
I did a little bit of digging around, and concluded that I'll have to
pay real money for a real FPGA board.  The XESS XS-40 board did a very
respectable job these past two months, but my current project requires
more gates.

I checked out the various 'third party vendors' listed under Xilinx's
webstore (click on "prototype platforms".)  After looking at all the
sites, I've narrowed down my search to two contendors :

  1)  AVNET's Xilinx Development System (XCV300-432 FPGA on PCI board)
      prototype board can be used standalone (not plugged into PCI slot)
      $2495 (with Xilinx Foundation Express)

  2)  XESS Virtex-300 (XCV300-240 FPGA on prototype board)
      $799 (no software, so I'd need to buy Foundation Express
elsewhere)

Either way, I need Xilinx's software tool (Foundation Express), so
factoring this as an additional cost to #(2), the total cost of either
choice comes out the same.

(Don't laugh, but these past two months, I 'scraped by' with the Xilinx
Student Edition 1.5 software.  This was only a temporary situation until
I verified FPGA-board was viable for prototyping some work I was doing.)
Article: 25773
Subject: Re: Simulation problem
From: yuryws@my-deja.com
Date: Wed, 20 Sep 2000 04:18:57 GMT
Links: << >>  << T >>  << A >>
You may want to check for a presense of combinatorial loops, which
could be a cause of what you are seeing.

-- Yury Wolf-Sonkin  / RealTime Data LLC /


In article <39C29203.2587E967@xilinx.com>,
  Mujtaba Hamid <mujtaba.hamid@xilinx.com> wrote:
> Your design is going into an infinite loop at that point. You can go
to
> Options > Simulation Options in MTI and increase the iteration limit.
But
> even if hte default iteration limit is reached (5000), it probably
means that
> there is an infinite loop at that time in simulation.
>
> What you might wanna do is to run simulation for maybe 1 ns less than
at the
> time when this error happens. Then step through the simulator and see
which
> line in the source code MTI hangs at.
>
> Mujtaba
>
> Tomasz Brychcy wrote:
>
> > Hello,
> >
> > Simulation of model before synthesis is correct. When i simulate
the same
> > model but after synthesis during simulation in MTI 5.2c occur the
problem:
> >
> > iteration limit reached. Possilbe zero delay oscillation.
> >
> > I do not know what do?
> >
> > Please about help
> >
> > I attach files:
> >
> > file before synthesis: controllogic(synth).v
> > file after synthesis: controllogic.v
> > testbench: tb_controllogic.v
> >
> > P.S I know that the problem occur exactly when signal ReadCn goes
to high
> > state.
> >
> > Tomek
> >
> > --
> > Department of Electrical Metrology
> > Technical University of Zielona Gora
> >
> > T.Brychcy@ime.pz.zgora.pl
>
>


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Article: 25774
Subject: Re: PCI-Tip? (for Xilinx Virtex/-E)
From: yuryws@my-deja.com
Date: Wed, 20 Sep 2000 04:31:19 GMT
Links: << >>  << T >>  << A >>
My experience envolves a design based on PCI 32/33 on Spartan family.
You have to be careful sizing your device. For example, when Xilinx
states that PCI 32/33 should take up only 55% of Spartan 30 XL, what
they really mean that in order to get PCI Master/Slave functional you
need to add some 15%-20% of additional logic on top of the core. That
required logic is extensively described in PCI Logicore Implementation
Guide. Obviously, Xilinx's marketing team minimizes the device
utilization of PCI logicore to make the product more attractive.

-- Yury



In article <39C1EB9F.196D852E@ti.uni-mannheim.de>,
  Lars Rzymianowicz <larsrzy@ti.uni-mannheim.de> wrote:
> Marc Reinert wrote:
> > I'm going to develop a PCI board (33Mhz/32Bit) on one of these
devices.
> > My idea is to have a lot of space left in my FPGA beside the
> > PCI-Interface.
> > Is there a core (or better a complete VHDL-Programming) aviable from
> > Xilinx (or anybody else)? Does it work well and are any features of
the
> > PCI-Bus not supported? Is there a free version aviable on the
internet?
>
> Hi Marc,
>
> Xilinx has the logiCORE PCI macrocell, which is a customizable
> 33/66/32/64 PCI interface. Check the Xilinx website for it, it's
> price is around $5000, i guess.
> Since you are a University, you might consider to join the Xilinx
> Univ. Prg. XUP. There you can also apply for a donation of the core.
> I tried that, but never got any reply on several emails/faxes.
> But maybe you have more luck ;-)
>
> Lars
> --
> Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
> Tel:      +(49) 621 181-2716, Fax: -2713
> email:    larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
> Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
>


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