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Messages from 25825

Article: 25825
Subject: Category : Why CRs are cleared?
From: Tomek <T.Brychcy@ime.pz.zgora.pl>
Date: Thu, 21 Sep 2000 23:21:44 -0700
Links: << >>  << T >>  << A >>
Hello,

I od not know why CRs registers are cleared during simulation after synthesis? Code is below:

always @ (INITIAL_COUNT or CONTROL_WORD or RW_REG or intoCounter) 

	if (INITIAL_COUNT) begin
		if (PULSE_CR1==1'b1) begin
			CR1=D_IN; 
			LOADED_CR=1'b1; 
			FIRST_BYTE_LOADED=1'b0;	 
		end
		else begin
			case (RW_REG) 
				2'b10 : begin CR1=D_IN; ODDnEVEN=1'b0; PULSE_CR1=1'b0; LOADED_CR=1'b1; end 
				2'b01 : begin CR0=D_IN; ODDnEVEN=D_IN[0]; PULSE_CR1=1'b0; LOADED_CR=1'b1; end 
				2'b11 : begin CR0=D_IN; ODDnEVEN=D_IN[0]; PULSE_CR1=1'b1; FIRST_BYTE_LOADED=1'b1; end 
				default: begin CR0=8'bx; CR1=8'bx; PULSE_CR1=1'bx; FIRST_BYTE_LOADED=1'bx; LOADED_CR=1'bx; end
			endcase
		end
	end
	else if (CONTROL_WORD && !INITIAL_COUNT) begin
		CR0=8'b00000000;
		CR1=8'b00000000;
		PULSE_CR1=1'b0;
		FIRST_BYTE_LOADED=1'b0;
	end
	else if (intoCounter)
		LOADED_CR=1'b0;

When INITIAL_COUNT is active and e.g. RW_REG=2'b01 then CR0 is set and even signal CONTROL_WORD is low CR0 is cleared, why?

P.S If you can help me I will send you all files to simulate it.

Please about help

Tomek
Article: 25826
Subject: Category : timinig testbench
From: Tomek <T.Brychcy@ime.pz.zgora.pl>
Date: Thu, 21 Sep 2000 23:24:13 -0700
Links: << >>  << T >>  << A >>
Hello,

How prepare a testbench for timing simulation? When I write testbench for behavioral simulation, the testbench does not work for timing sim.

I request for reply.

Tomek
Article: 25827
Subject: Re: Alliance 3.1i CAE Libs install hangs under Solaris
From: petter@scimba.dolphinics.no
Date: 22 Sep 2000 06:45:44 -0100
Links: << >>  << T >>  << A >>
bob_42690@my-deja.com writes:

> One time, I found that cleaning the CD helped.

I had no problems reading the CD, actually I copied all the files onto
my hard drive and tried to install from there, but it still did not
work.

I got a patch (or actually a new install program with its own java VM)
from Xilinx which worked, although it was pretty slow compared to just
tar tvfz /dev/cdrom.

-- 
Petter
________________________________________________________________________
Petter Gustad       8'h2B | (~8'h2B) - Hamlet      http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 25828
Subject: Re: Category : Why CRs are cleared?
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 22 Sep 2000 09:00:34 GMT
Links: << >>  << T >>  << A >>
On Thu, 21 Sep 2000 23:21:44 -0700, Tomek <T.Brychcy@ime.pz.zgora.pl>
wrote:

>Hello,
>
>I od not know why CRs registers are cleared during simulation after synthesis? Code is below:
>
>always @ (INITIAL_COUNT or CONTROL_WORD or RW_REG or intoCounter) 
>
>	if (INITIAL_COUNT) begin
>		if (PULSE_CR1==1'b1) begin
>			CR1=D_IN; 
>			LOADED_CR=1'b1; 
>			FIRST_BYTE_LOADED=1'b0;	 
>		end
>		else begin
>			case (RW_REG) 
>				2'b10 : begin CR1=D_IN; ODDnEVEN=1'b0; PULSE_CR1=1'b0; LOADED_CR=1'b1; end 
>				2'b01 : begin CR0=D_IN; ODDnEVEN=D_IN[0]; PULSE_CR1=1'b0; LOADED_CR=1'b1; end 
>				2'b11 : begin CR0=D_IN; ODDnEVEN=D_IN[0]; PULSE_CR1=1'b1; FIRST_BYTE_LOADED=1'b1; end 
>				default: begin CR0=8'bx; CR1=8'bx; PULSE_CR1=1'bx; FIRST_BYTE_LOADED=1'bx; LOADED_CR=1'bx; end
>			endcase
>		end
>	end
>	else if (CONTROL_WORD && !INITIAL_COUNT) begin
>		CR0=8'b00000000;
>		CR1=8'b00000000;
>		PULSE_CR1=1'b0;
>		FIRST_BYTE_LOADED=1'b0;
>	end
>	else if (intoCounter)
>		LOADED_CR=1'b0;
>
>When INITIAL_COUNT is active and e.g. RW_REG=2'b01 then CR0 is set and even signal CONTROL_WORD is low CR0 is cleared, why?

You're in the wrong newsgroup - this should be in comp.lang.verilog.
You don't give nearly enough information but, if INITIAL_COUNT and
PULSE_CR1 are 1, then CR0 will hold its previous value, which might
have been 0's. On the other hand, if PULSE_CR1 is 0, and D_IN is 0's,
then CR0 will be 0's. Do you know that you're creating latches on the
signals you're assigning to? Is this the intention? And why are you
assigning x's in synthesisable code?

>P.S If you can help me I will send you all files to simulate it.

Hope this helps, but no files please...

Evan
Article: 25829
Subject: Re: Simon , decoupling caps
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 22 Sep 2000 09:02:44 GMT
Links: << >>  << T >>  << A >>
On Wed, 20 Sep 2000 07:40:26 -0700, Bob Perlman
<bobperl@best_no_spam_thanks.com> wrote:

>Hi - 
>
>On Wed, 20 Sep 2000 09:27:12 GMT, eml@riverside-machines.com.NOSPAM
>wrote:
>
>>On Sat, 16 Sep 2000 12:44:52 -0700, Bob Perlman
>><bobperl@best_no_spam_thanks.com> wrote:
>>
>>>Hi - 
>>>
>>>Some good papers on decoupling can be found at:
>>>
>>>http://www.qsl.net/wb6tpu/si_documents/docs.html
>>
>>Thanks for the link. The fourth paper in the list is "Decoupling
>>capacitor calculations", and its one that I read a couple of years
>>ago; I haven't read the others.
>>
>>However, without wishing to be offensive, I have to say that this
>>paper is just plain wrong. 
>
><technical discussion deleted>
>
>>It would be interesting to hear from anyone else who's read this paper
>>and has a view on it.
>>
>>Evan  
>
>Or you could go to the signal integrity reflector and ask Larry Smith
>directly.  He's been very willing to discuss the things he's written
>and posted.  Post your critique of his article...and stand back.  

Thanks, but my life is too short to get involved in yet another
mailing list argument. I'd also have to re-read a paper I didn't like
and write a criticism of it, which sounds like a job for an academic
with tenure, rather than a humble engineer who's waiting for a kettle
to boil.

On the other hand, you could mail him:

http://x73.deja.com/[ST_rn=ps]/getdoc.xp?AN=671967180&CONTEXT=969612887.657981477&hitnum=0

if you need some extra heat.

Evan
Article: 25830
Subject: Is correct code?
From: "Tomasz Brychcy" <T.Brychcy@ime.pz.zgora.pl>
Date: Fri, 22 Sep 2000 02:33:01 -0700
Links: << >>  << T >>  << A >>
Hello,

I have written a model of tri state data bus:

ports:

inout [7:0] D;
input [7:0] D_IN;
input CNTRL;
output [7:0] D_OUT;

assign D=(CNTRL) ? D_IN ? 8'bz; //write
assign D_OUT=(~CNTRL) ? D ? 8'bz; //read

When I simulate the model (timing simulation) results are not correct. Behavioral simulation (before and after synthesis ) is correct. What I should do? Maybe testbench is wrong?

I request for reply

Tomek
Article: 25831
Subject: Pack I/O Reg/Latches into IOBs
From: Henrik A. =?iso-8859-1?Q?S=F8rensen?= <u2@image.dk>
Date: Fri, 22 Sep 2000 12:14:16 +0200
Links: << >>  << T >>  << A >>
Hey you all.

I have a problem concerning mapping some of my regsters directly into IO
PADS. In my VHDL code, I have declared some registers - by the standard
process form for a register. Xilinx Design manager has also translated
my source edif file right, but implements the registers within CLB, even
though the Flip-flops output is connected directley to a output. I have
tried the Map option: Pack I/O registers/Latches into IOBs for Input and
output. But this option does NOT influence the mapping???? Is there some
way to indicate where a reister should be mapped whitin the source VHDL
code??? Or are there other guidelines??

Thanks in advance

Henrik

Article: 25832
Subject: Virtex: partial reconfiguration
From: "Stephen Ingram" <stepheningram@hotmail.com>
Date: Fri, 22 Sep 2000 04:58:31 -0700
Links: << >>  << T >>  << A >>
Has anyone got any programs that can allow me to use an xchecker cable to reconfigure a virtex device while it is executing a program that was inputted using JTAG programmer?  source code would also be useful (i am using an xcv800)

Does the bitstream need to be different if it is to be used for reconfiguration?
Article: 25833
Subject: Re: Announce: Free HC11 CPU Core
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 22 Sep 2000 12:18:39 GMT
Links: << >>  << T >>  << A >>
On Thu, 21 Sep 2000 10:17:19 -0400, "Scott Thibault"
<thibault@gmvhdl.com> wrote:

>We have a synthesizable HC11 CPU core available for download.  See
>http://www.gmvhdl.com/hc11core.html for details.
>
>--Scott Thibault
>Green Mountain
>Computing Systems, Inc.
>http://www.gmvhdl.com

Very nice. Have you done an FPGA implementation? Do you know how
big/fast it is?

Evan
Article: 25834
Subject: Re: Announce: Free HC11 CPU Core
From: Ray Andraka <ray@andraka.com>
Date: Fri, 22 Sep 2000 12:40:45 GMT
Links: << >>  << T >>  << A >>
Evan, his website tells all.  He's apparently sythesized it to Altera 20K100 and
Virtex400E, both of which ran at about 31-32 MHz.  One could probably double the
speed and cut the size by a considerable amount by tailoring the design to a
specific part, but hey this ain't bad and who's to look a gift horse in the
mouth?  

Nice piece of work, and a substantial amount of effort to give away.  


eml@riverside-machines.com.NOSPAM wrote:
> 
> On Thu, 21 Sep 2000 10:17:19 -0400, "Scott Thibault"
> <thibault@gmvhdl.com> wrote:
> 
> >We have a synthesizable HC11 CPU core available for download.  See
> >http://www.gmvhdl.com/hc11core.html for details.
> >
> >--Scott Thibault
> >Green Mountain
> >Computing Systems, Inc.
> >http://www.gmvhdl.com
> 
> Very nice. Have you done an FPGA implementation? Do you know how
> big/fast it is?
> 
> Evan

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25835
Subject: Re: Announce: Free HC11 CPU Core
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Fri, 22 Sep 2000 13:11:00 GMT
Links: << >>  << T >>  << A >>
Ray,
     I agree that this is a substantial amount of effort, but the site does
say that you need VHDL Studio.  I do not know why it is needed, but this
could explain why the core is free.  This could be an example of bait and
switch.  Depending on the price of VHDL Studio, this could be a "gift
horse," too, as you say.
-Simon Ramriez, Consultant
 Synchronous Design, Inc.



"Ray Andraka" <ray@andraka.com> wrote in message
news:39CB52F5.9DDCB49C@andraka.com...
> Evan, his website tells all.  He's apparently sythesized it to Altera
20K100 and
> Virtex400E, both of which ran at about 31-32 MHz.  One could probably
double the
> speed and cut the size by a considerable amount by tailoring the design to
a
> specific part, but hey this ain't bad and who's to look a gift horse in
the
> mouth?
>
> Nice piece of work, and a substantial amount of effort to give away.
>
>
> eml@riverside-machines.com.NOSPAM wrote:
> >
> > On Thu, 21 Sep 2000 10:17:19 -0400, "Scott Thibault"
> > <thibault@gmvhdl.com> wrote:
> >
> > >We have a synthesizable HC11 CPU core available for download.  See
> > >http://www.gmvhdl.com/hc11core.html for details.
> > >
> > >--Scott Thibault
> > >Green Mountain
> > >Computing Systems, Inc.
> > >http://www.gmvhdl.com
> >
> > Very nice. Have you done an FPGA implementation? Do you know how
> > big/fast it is?
> >
> > Evan
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Article: 25836
Subject: Re: Announce: Free HC11 CPU Core
From: "Scott Thibault" <thibault@gmvhdl.com>
Date: Fri, 22 Sep 2000 09:51:45 -0400
Links: << >>  << T >>  << A >>
Hi Ray,

VHDLStudio is only required to run the included HC11 debugger.  The core is
in standard VHDL which can be simulated and synthesized with any standard
tool.

Regards,
--Scott Thibault
Green Mountain
Computing Systems, Inc.

"S. Ramirez" <sramirez@deleet.cfl.rr.com> wrote in message
news:ETIy5.20208$W45.2292373@typhoon.tampabay.rr.com...
> Ray,
>      I agree that this is a substantial amount of effort, but the site
does
> say that you need VHDL Studio.  I do not know why it is needed, but this
> could explain why the core is free.  This could be an example of bait and
> switch.  Depending on the price of VHDL Studio, this could be a "gift
> horse," too, as you say.
> -Simon Ramriez, Consultant
>  Synchronous Design, Inc.
>
>
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:39CB52F5.9DDCB49C@andraka.com...
> > Evan, his website tells all.  He's apparently sythesized it to Altera
> 20K100 and
> > Virtex400E, both of which ran at about 31-32 MHz.  One could probably
> double the
> > speed and cut the size by a considerable amount by tailoring the design
to
> a
> > specific part, but hey this ain't bad and who's to look a gift horse in
> the
> > mouth?
> >
> > Nice piece of work, and a substantial amount of effort to give away.
> >
> >
> > eml@riverside-machines.com.NOSPAM wrote:
> > >
> > > On Thu, 21 Sep 2000 10:17:19 -0400, "Scott Thibault"
> > > <thibault@gmvhdl.com> wrote:
> > >
> > > >We have a synthesizable HC11 CPU core available for download.  See
> > > >http://www.gmvhdl.com/hc11core.html for details.
> > > >
> > > >--Scott Thibault
> > > >Green Mountain
> > > >Computing Systems, Inc.
> > > >http://www.gmvhdl.com
> > >
> > > Very nice. Have you done an FPGA implementation? Do you know how
> > > big/fast it is?
> > >
> > > Evan
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
> >
>
>


Article: 25837
Subject: Re: Pack I/O Reg/Latches into IOBs
From: Carl Rohrer <crohrer@xilinx.com>
Date: Fri, 22 Sep 2000 09:25:56 -0600
Links: << >>  << T >>  << A >>
Hi Henrik,

You can apply a constraint in your ucf to force registers into the IOB.  The
syntax looks like this:
INST <instance_name> IOB=TRUE;
If you want to embed it directly in your code, it depends on your
synthesizer.  If you're using XST, the attribute will look like this:
~~~~
entity OUT_FLIP_FLOP is
  port (DIN      : in  std_logic;
        CLK, RST : in  std_logic;
        DOUT     : out std_logic);
  attribute IOB  :     string;

end OUT_FLIP_FLOP;

architecture OUTFF_arch of OUT_FLIP_FLOP is

  attribute IOB of DOUT_INT : signal is "TRUE";
....

~~~~
You can also choose to instantiate an OFD, which forces the register into
the IOB.

The map option should have pushed the register into the IOB though.  If you
find that nothing is working, check the polarity of your CE, Reset, and Set
signals.  Take a look at an IOB in FPGA Editor to make sure you're aware of
the hardware available to you.

Regards,
Carl




"Henrik A. Sørensen" wrote:

> Hey you all.
>
> I have a problem concerning mapping some of my regsters directly into IO
> PADS. In my VHDL code, I have declared some registers - by the standard
> process form for a register. Xilinx Design manager has also translated
> my source edif file right, but implements the registers within CLB, even
> though the Flip-flops output is connected directley to a output. I have
> tried the Map option: Pack I/O registers/Latches into IOBs for Input and
> output. But this option does NOT influence the mapping???? Is there some
> way to indicate where a reister should be mapped whitin the source VHDL
> code??? Or are there other guidelines??
>
> Thanks in advance
>
> Henrik

Article: 25838
Subject: Re: Virtex: partial reconfiguration
From: Carl Rohrer <crohrer@xilinx.com>
Date: Fri, 22 Sep 2000 09:31:08 -0600
Links: << >>  << T >>  << A >>
Hi Stephen,

If you haven't already, take a look at app 153:
http://support.xilinx.com/xapp/xapp153.pdf



Stephen Ingram wrote:

> Has anyone got any programs that can allow me to use an xchecker cable to reconfigure a virtex device while it is executing a program that was inputted using JTAG programmer?  source code would also be useful (i am using an xcv800)
>
> Does the bitstream need to be different if it is to be used for reconfiguration?

Article: 25839
Subject: Re: Pack I/O Reg/Latches into IOBs
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Fri, 22 Sep 2000 09:34:19 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------FDB93A4F4D8A2ACBFAF56BDC
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

"Henrik A. Sørensen" wrote:

> Hey you all.
>
> I have a problem concerning mapping some of my regsters directly into IO
> PADS. In my VHDL code, I have declared some registers - by the standard
> process form for a register. Xilinx Design manager has also translated
> my source edif file right, but implements the registers within CLB, even
> though the Flip-flops output is connected directley to a output. I have
> tried the Map option: Pack I/O registers/Latches into IOBs for Input and
> output. But this option does NOT influence the mapping????

The rules for merging FFs into an IOB are discussed at:
http://support.xilinx.com/techdocs/2207.htm

If this particulr FF breaks any of these rules, it can not be merged in the
IOB.  If your particular register does not break any of these rules, the
"-pr b" switch in Map should push the register into the IOB.


> Is there some
> way to indicate where a reister should be mapped whitin the source VHDL
> code??? Or are there other guidelines??

The brute-force method to push a register into an IOB for non-Virtex and
Spartan-II devices is to instantiate an IFD or an OFD in your code.  If you
are targeting a Virtex or Spartan-II device, instead of instantiating the
register, you can add the following constraint to you UCF file:

INST <register_instance_name> IOB=TRUE;

This is supposed to tell the mapper you want this register in the IOB.
Again, the rules specified above need to be observed for this to happen.

--  Brian


>
>
> Thanks in advance
>
> Henrik

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tel;work:1-800-255-7778
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org:Xilinx, Inc.;Software Marketing
adr:;;2300 55th Street;Boulder;CO;80301;USA
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email;internet:brianp@xilinx.com
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Article: 25840
Subject: Re: A Question on Virtex Configuration
From: Carl Rohrer <crohrer@xilinx.com>
Date: Fri, 22 Sep 2000 09:42:56 -0600
Links: << >>  << T >>  << A >>
Kent is on the right track.  Check the bitgen options.  Specifically, open up
the bitgen.ut file.  Make sure your startup clock is JTAG, not CCLK or UCLK.
Your device is probably sitting in the startup sequence waiting for those last
few strobes.

Carl


"K. Orthner" wrote:

> Stephen,
>
> Is there a chance that as soon as configuration is complete, that the JTAG
> clock stops?  (I'm not fmiliar with XChecker.)  After the configuration is
> compelte, the FPGA needs a couple of extra clock cycles to initialize
> itself and set the DONE output.
>
> In the bitstream generation stage, after place and route, you can select
> how many clock cycles until DONE is high.
>
> Hope this helps.
>
> _Kent
>
> stepheningram@hotmail.com (Stephen Ingram) wrote in
> >This problem is very similar to one I am having, but i am using an
> >xchecker.  My problem only occurs with JTAG, the correct bitgen
> >parrameters are used, and the correct mode is selected.  The JTAG
> >programmer software says the programing was succesful, but done does not
> >go high.  (Done does go high if hardware debugger is used).

Article: 25841
Subject: Multi-Arch, Moderately High performance VHDL FPGA Code?
From: Robert Posey <muddy@raytheon.com>
Date: Fri, 22 Sep 2000 11:13:35 -0500
Links: << >>  << T >>  << A >>
Dear Gentle Persons,

Has anyone successfully written VHDL code for large FPGA's that is transportable
without modification between Xlinx, Altera Etc. I looking for someone who
has actually successfully complete the process.  To get reasonable high
performance, its seems almost everyone uses arch. specific components, which
likely won't match up at least between companies.  Has anyone tried this
lately.  By Moderately high performance I mean a FPGA more than 70% utilized,
and operating at speed levels that require one of the faster speed grades for
a given arch.  

Muddy
Article: 25842
Subject: Re: Alliance 3.1i CAE Libs install hangs under Solaris
From: Paul Smith <ptsmith@indiana.edu>
Date: Fri, 22 Sep 2000 11:50:33 -0500
Links: << >>  << T >>  << A >>
petter@scimba.dolphinics.no wrote:
> 
> I'm having trouble installing the CAE Libraries under Solaris. The
> progress indicator has been sitting still for 24 hours, but the
> advertisement banners are running. I hate bloatware stuff like
> netscape/java for installation when a /bin/sh would have done the job.
> All I want is some ASCII files (Synopsys and Cadence libraries) off
> the CD.
> 
> Anybody else experienced similar problems?
> 

I just installed the Alliance 3.1i software under Solaris 8 yesterday
and also had problems.  Xilinx advertisements while installing Xilinx
software!  I bought the software and plan to use the chips, I don't need
or want advertising!!  Bloatware is a much kinder term than I would use.

It seems the installer spawns processes like crazy and runs out of
processes if anything else is going on.  The installer then reports
javascript errors and hangs.  When this happens the adverts still run,
although they change much more often.

I got it to work by installing just one CAE library at a time and not
running anything else on the machine while the install was going.

I wasn't able to get the "tuner" install to work at all.

These problems and more are covered on the Xilinx support web site. 
They have a different installer you can download, and mention they will
not use the web based installer for future versions.   Good!!!!!!

Paul Smith
Indiana University Physics
Article: 25843
Subject: Re: Announce: Free HC11 CPU Core
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Fri, 22 Sep 2000 17:32:33 GMT
Links: << >>  << T >>  << A >>
Thank, Scott.
-Simon Ramirez, Consultant
 Synchronous Design, Inc.


"Scott Thibault" <thibault@gmvhdl.com> wrote in message
news:8qfo69$rf4$1@slb7.atl.mindspring.net...
> Hi Ray,
>
> VHDLStudio is only required to run the included HC11 debugger.  The core
is
> in standard VHDL which can be simulated and synthesized with any standard
> tool.
>
> Regards,
> --Scott Thibault
> Green Mountain
> Computing Systems, Inc.



Article: 25844
Subject: Re: Pack I/O Reg/Latches into IOBs
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Fri, 22 Sep 2000 11:55:37 -0700
Links: << >>  << T >>  << A >>
Henrik,

If you are using FPGA Express 3.4, then by default it does not use IOB
registers. By default FE sets IOB=False and  even if you enable Map option
"Pack I/O registers into IOBs", map does not over right  IOB=False set by
FPGA Express. The two available options are, either set IOB= True in FPGA
Express or specify this constraint in the ucf file.

This is fixed in the next version of FPGA Express and it will have three
options for IOB registers: None, True, False. By default it selects "None"
and does not add any attribute to  IOB registers. This will enable
Map to select IOB registers with the option "Pack I/O registers".

-Vikram
Xilinx Applications


"Henrik A. Sørensen" wrote:

> Hey you all.
>
> I have a problem concerning mapping some of my regsters directly into IO
> PADS. In my VHDL code, I have declared some registers - by the standard
> process form for a register. Xilinx Design manager has also translated
> my source edif file right, but implements the registers within CLB, even
> though the Flip-flops output is connected directley to a output. I have
> tried the Map option: Pack I/O registers/Latches into IOBs for Input and
> output. But this option does NOT influence the mapping???? Is there some
> way to indicate where a reister should be mapped whitin the source VHDL
> code??? Or are there other guidelines??
>
> Thanks in advance
>
> Henrik

Article: 25845
Subject: memory interface trouble...
From: "Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Fri, 22 Sep 2000 21:22:07 +0200
Links: << >>  << T >>  << A >>
Hi,
I have great trouble with our newest design, which
should have data transfer between our Infineon Micro-
controller (SAB C167) and our FPGA (ALTERA EP1K100)
by using the Address/Data Port, ChipSelect and RD/WR
of the Microcontroller. The FPAG should act as standard
memory for the Microcontroller.
Well, I had configured the FPGA in VHDL-Code for Tri-State
on the interface pins (xuC <= (OTHERS => 'Z');), but
every time the FPGA has configured, the microcontroller
would no longer start it's Bootstrap Loader mode...

Do I have to take care of some special things?
I thought, that the Microcontroller shouldn't notice
the FPGA at all, as these Pins are tristated...

Any help is welcome, I have great time pressure and
no idea, where to search for the problem's reason...

TIA, Carlhermann Schlehaus


Article: 25846
Subject: Re: memory interface trouble...
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 22 Sep 2000 13:34:22 -0700
Links: << >>  << T >>  << A >>
Carlhermann Schlehaus wrote:
. . .
> Well, I had configured the FPGA in VHDL-Code for Tri-State
> on the interface pins (xuC <= (OTHERS => 'Z');), but
> every time the FPGA has configured, the microcontroller
> would no longer start it's Bootstrap Loader mode...
> 
> Do I have to take care of some special things?
> I thought, that the Microcontroller shouldn't notice
> the FPGA at all, as these Pins are tristated...
----------------------------



It would help to see your code, 
but if the entire xuC process is 

xuC <= (OTHERS => 'Z');

then synthesis will likely ignore the code
and the place and route may be defaulting
to something other than 'Z'.
Altera place and route sometimes likes to
ground "unused" pins.

If this is the problem, you can
force a Z pin by pin in the place and route
constraints file,
or force the synthesizer using something like:

xuC <= dmux when oe_n = '0' else (OTHERS => 'Z');

--    mike.treseler@flukenetworks.com or
--             tres@tc.fluke.com
Article: 25847
Subject: Re: memory interface trouble...
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 22 Sep 2000 13:46:44 -0700
Links: << >>  << T >>  << A >>
As you knoe, I don't work for Altera, but anyhow:

Most FPGA pins are 3-stated during configuration. What happens right
after the completion of configuration is up to you, the designer.

Even during configuration, the pins may be pulled High ( perhaps
even Low) by a weak internal resistor, since nobody likes floating
inputs. Maybe the uP reacts to these logic levels...

Peter Alfke, from the other end of the alphabet.
==============================================

Carlhermann Schlehaus wrote:

> Hi,
> I have great trouble with our newest design, which
> should have data transfer between our Infineon Micro-
> controller (SAB C167) and our FPGA (ALTERA EP1K100)
> by using the Address/Data Port, ChipSelect and RD/WR
> of the Microcontroller. The FPAG should act as standard
> memory for the Microcontroller.
> Well, I had configured the FPGA in VHDL-Code for Tri-State
> on the interface pins (xuC <= (OTHERS => 'Z');), but
> every time the FPGA has configured, the microcontroller
> would no longer start it's Bootstrap Loader mode...
>
> Do I have to take care of some special things?
> I thought, that the Microcontroller shouldn't notice
> the FPGA at all, as these Pins are tristated...
>
> Any help is welcome, I have great time pressure and
> no idea, where to search for the problem's reason...
>
> TIA, Carlhermann Schlehaus

Article: 25848
Subject: Re: Xilinx Web Pack
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 22 Sep 2000 17:17:35 -0400
Links: << >>  << T >>  << A >>
Carl,

I called the support number and guess what? They actually spoke to me! I
guess I have not had great luck with support over the years and have
become a little pessimistic about things like supporting users out of
maintenance or software two years old. But they did not even ask about
the maintenance. BTW, I gave up on the Webpack and went back to my old
1.5i software. The tool I know and trust ;) At least I know what to
expect...

We don't have a solution yet, but Kamal sounded like he knew what he was
doing and I expect to hear back from him soon. 

Thanks for the prod. 



Carl Rohrer wrote:
> 
> Rick,
> 
> It sounds like you might only have the design entry and synthesis tools
> installed and not the fitter tools.  Once you've installed the fitter tools, the
> default device will still be 'virtual device' but you can right click on it and
> change it.  And yes, we'll still talk to you on the phone. :)  1-800-255-7778.
> 
> Carl

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 25849
Subject: Re: JTAG CPLD FPGA
From: chadlamb@my-deja.com
Date: Fri, 22 Sep 2000 21:19:05 GMT
Links: << >>  << T >>  << A >>
Also, the JTAG pins on the Virtex devices are dedicated to JTAG.  The
JTAG pins on the XC4000 devices are not dedicated, they can also be
used as user IO (with the TDO used as and output only, not an input).


Sent via Deja.com http://www.deja.com/
Before you buy.


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