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Messages from 26450

Article: 26450
Subject: Re: CHES 2001 Workshop
From: Tom St Denis <stdenis@compmore.net>
Date: Mon, 16 Oct 2000 18:18:59 GMT
Links: << >>  << T >>  << A >>
In article <8sfgc1$ra9$1@nnrp1.deja.com>,
  Tom St Denis <stdenis@compmore.net> wrote:
> The TC8 *draft* paper
> (http://www.geocities.com/tomstdenis/tc8_draft.zip) is available.
It's
> one of my "better" papers as I tried to include more background and
> technical information.

Arrg that at

http://www.geocities.com/tomstdenis/files/tc8_draft.zip

Tom


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 26451
Subject: Re: Low power cpld?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 17 Oct 2000 07:21:18 +1300
Links: << >>  << T >>  << A >>
e97bjli@thn.htu.se wrote:
> 
> Hi
> 
> I use a XC9536 CPLD device. I want to change this device to an low power
> cpld -fpga device for a batterie cricute.
> 
> I don't want this low power device to use prom like XC9536.
> 
> Where do I find an device to fitt my problem?

 If static battery Idd dominates ( ie long times are 'off' ),
then the Atmel ATF1502AS has ~ 5uA typ static Idd.
 If Idd at speed ( ie mA/MHz) dominates, then the Coolrunner 
XCR5032 will do, but they have a higher static Idd.
 They are pin compatible, and we have ported XCR5032 designs to
ATF1502, so you can try both.
 -jg

Article: 26452
Subject: Re: Xilinx and CD databooks (rant)
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 16 Oct 2000 11:34:44 -0700
Links: << >>  << T >>  << A >>
Kent,

I did not send any graph to Rick that I recall.

What is it you would like to see a picture of?

Austin

Kent Orthner wrote:

> Hey, Rick.
>
> Do you mind forwarding me the graph you got from Austin, if you can?
>
> Thanks,
> Kent.


Article: 26453
Subject: Re: palasm
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Mon, 16 Oct 2000 18:44:14 GMT
Links: << >>  << T >>  << A >>
Klaus,
     Talk to your Cypress representative about Warp2.  This compiler has
been around for ten years or so, and it allows VHDL design entry for the
peanut parts like the 16L8s, 16V8, 22V10s, etc.  As Warp2 evolved, it now
allows for either VHDL or Verilog entry.  They had to do this, because the
parts were getting bigger and bigger and ...
     Warp2 is both the source compiler and fitter as well as several other
things like a simulator.
     I did my first 22V10 design using ABEL back in 1983.  As much as I
loved ABEL and PALASM and CUPL, I felt that they have been superceded by
VHDL and Verilog.  I decided to switch to these two HDLs back in the early
1990s just so that I wouldn't have to learn and maintain so many programming
languages.  With VHDL and Verilog, I find that I can do any design out
there, all the way down to the lowly 16L8, which is occasionally used and
has a good fit sometimes.
     One good thing about Warp2 is that it allows one to learn VHDL and/or
Verilog with small parts and small designs.  I taught an engineer how to do
a 22V10 design using VHDL about five years ago, and he quickly became a VHDL
expert!
     Good luck and let us know how you fared with Warp2 and your 22V10s.
-Simon Ramirez, Consultant
 Synchronous Design, Inc.


"Klaus Falser" <kfalser@durst.it> wrote in message
news:8se8qg$qcc$1@nnrp1.deja.com...
> In article <o7OF5.75745$O95.6492260@typhoon.tampabay.rr.com>,
>   "S. Ramirez" <sramirez@deleet.cfl.rr.com> wrote:
> >      Then try using VHDL to program your 22V10s!
> > -Simon Ramirez, Consultant
> >  Synchronous Design, Inc.
>
> Which tools can be used to program a 22V10 in VHDL?
> I could not find any compiler and fitter for a PAL.
>
> Thank you.
> --
> Klaus Falser
> Durst Phototechnik AG
> I-39042 Brixen




Article: 26454
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Neil Franklin <neil@franklin.ch.remove>
Date: 16 Oct 2000 21:44:13 +0200
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes:

> Neil Franklin wrote:
> > rickman <spamgoeshere4@yahoo.com> writes:
>
> > Also alternatively I would accept keyboard and video on an separate
> > card, so only RS232, IDE and possibly Ethernet need to be on board.
>
> I expect this will be best done on a separate board. When you say you
> will "accept" this "BAS" video, what exactly does this mean? Are you
> looking to redititize the video or just combine the video with your own
> generated video?

Accept was in the sense of: I will use the design, swapping my VGA
monitor for my BAS video monitor. There do exist advantages of having
6 monitors in this room. :-)


> > > The next board I build will likely have up to 32 MB of SDRAM. But I
> > > don't think anyone makes an 18 bit wide version. If they do, that could
> > > be used.
> >
> > So I will have to go to FP or EDO DRAMs (both of which I have seen in
> > 9bit and 36bit.
>
> No, I would not recommend that. Or you will end up with the same problem
> that you would have trying to build a PDP11 using the original parts. FP
> and EDO DRAM will be all but gone in another year to two.

That could easily happen.


> Actually, I believe I worked on a machine once that had 40 bit memory.
> It used 32 data bits plus an 8 bit ECC.

Fairly common arrangement in better minicomputers.


> They also come in BGAs. But you
> won't want to build your own board with BGAs.

Definitely not.


> > Given how little RAM old computers had, I may end up using SRAM, and
> > saving the work of implementing DRAM refresh.

Actually I will be using SRAM, definitely.

I yesterday went a second time to the Xess website and found out that
the XS4010 now comes in an XS4010+ version with 128k*8bit SRAM and
has an optional expansion board with 2*32k*8bit, which I can easily
modify to 2*128k*8bit (just add 2 address wires to each SRAM chip).
That is enough memory, so long I accept the narrow data bus.

Also they have PS/2 and VGA and LPT on the board, and the LPT can be
converted to RS232 with 2 MAX233 chips, or I used the expansion boards
free wiring area for RS232.

Hard disk can also go on the wire area, or use an Parallel port Zip
drive on the LPT plug.

Enough for my designs for the nearer future (PDP8, PDP11/20, PDP1).

And there is also their XSV, with 2*512k*16bit and all IO I have ever
heard of (exept an hard disk interface, but there are expansion pins
and LPT), if I run out of space (PDP11/70 or PDP10).

With that situation the advantage of one stop shopping (for me and
people copying the project) decides the situation clearly.

And so much for following at least some advice :-).


> > > So I could not fit 16 MB on a PC/104 board with all the other circuitry.
> >
> > Oh, you want it _that_ small. :-)
>
> PC/104 is what we build at Arius, Inc. The processor board I will be

> it is a very full board.

Sounds it.


> If you are trying to tie FPGAs to dense memories, then you will have a
> hard time trying to use wire wrap. I don't think they have put anything
> above 4 Mbit DRAM or 256 Kbit SRAM in DIP. But I am not sure, so keep
> looking. :)

Deciding to use the Xess has made further planning of hardware components
unneccessary.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic

Article: 26455
Subject: Re: ModelSim XE/Starter speed issues
From: "Geezer" <seely@fastq.com>
Date: Mon, 16 Oct 2000 13:14:36 -0700
Links: << >>  << T >>  << A >>
Aldec has a Xilinx only simulator that is unlimited for under $3K in the US.
Available through Aldec or Insight.
Gary
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:39E2BDBC.C378EC18@yahoo.com...
> I think I need to stop asking questions when I really don't want to know
> the answers. According to this web page, not only do they slow down the
> XE starter simulator, but the XE full paid package is also slowed down
> for large designs! This is a little bit amazing that anyone would have
> the balls to do this and then *tell* you that they are doing it.
>
> Unless I am mistaken, the software is being crippled for larger designs
> unless you pay a higher price. I guess I just need to learn a little
> about marketing.
>
> What other simulators are out there that don't have these marketing
> games with the price/performance?
>
>
>
> bob_42690@my-deja.com wrote:
> >
> > Rick,
> > Check out http://www.xilinx.com/products/software/mxe.htm#products
> > At this site, it says the XE version slows down at 8000 lines of code,
> > and the XE starter is appropriate for designs less than 500 lines.
> > Last I looked, the full XE edition cost $995 I believe for a year.
> >
> > Hope this helps,
> >
> > Bob
> >
> > In article <39E24FF1.A0B2EA3E@yahoo.com>,
> >   rickman <spamgoeshere4@yahoo.com> wrote:
> > > This may sound like a dumb question, but is the starter version of
> > > ModelSim XE speed crippled above a certain design size?
> > >
> > > I have been increasing the size of my testbench and all of a sudden
> > the
> > > simulation slowed to a crawl. It had been running very nicely
> > simulating
> > > about 1 us of simulation time in 2 secs. Now it take about 20 or 30
> > secs
> > > for the same amount of simulation.
> > >
> > > At first I thought it was something in my code like an infinite loop
> > or
> > > other very inefficient construct. But I can get it to speed up by
> > > cutting out code (about 10 lines) regarless of where I cut it out.
> > When
> > > I simulate the full size design, I get a message that says,
> > >  "# WARNING: Design size of 513 statements exceeds ModelSim XE-Starter
> > > recommended capacity."
> > >
> > > Am I correct in assuming that this is an intentional limit that they
> > put
> > > in to encourage you to buy the upgraded tools? They don't make it very
> > > easy to figure this out, nor do they make it easy to get info on what
> > it
> > > takes to upgrade. I could not find a link to their web page anywhere.
> > > The "About" box points you to Xilinx. I guess they are afraid of
> > support
> > > calls.
> > >
> > > Of course I found a web page by searching on their name. But they
> > don't
> > > give info on the "starter" package or about a direct upgrade.
> > >
> > > Anyone know if there is a simple upgrade to unlock the speed governor?
> > > Or do you just buy ModelSim XE full package? Anyone know what it
> > costs?
> > >
> > > --
> > >
> > > Rick "rickman" Collins
> > >
> > > rick.collins@XYarius.com
> > >
> > > Ignore the reply address. To email me use the above address with the
> > XY
> > > removed.
> > >
> > > Arius - A Signal Processing Solutions Company
> > > Specializing in DSP and FPGA design
> > >
> > > Arius
> > > 4 King Ave
> > > Frederick, MD 21701-3110
> > > 301-682-7772 Voice
> > > 301-682-7666 FAX
> > >
> > > Internet URL http://www.arius.com
> > >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
>
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com




-----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
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Article: 26456
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Ray Andraka <ray@andraka.com>
Date: Mon, 16 Oct 2000 23:18:54 GMT
Links: << >>  << T >>  << A >>
Errr, if it were easy, believe me the FPGA software folks would be all over it
like fleas on a mongrel.  The problem as I see it is that the people doing the
tools haven't *Done* a design attepting to use partial reconfiguration, and
therefore don't have the slightest clue as to the problems that arise.  The same
can even be said for much of the hardware 'support' for partial configuration. 
I've been there done that several times over, and it ain't a pretty picture,
especially if you need to keep part of the logic alive and clocking while some
other part is being reconfigured.



rickman wrote:
> 
> Zoltan Kocsi wrote:
> >
> > Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk> writes:
> >
> > > >> (Linux people would jump up and down for a GPL'd tool)
> > >
> > > > You can bet your life on that.
> > >
> > > Well would they pay anything?  Get me a big enough wad of cash and I'll
> > > personally put together a team of people and lead the project until it's
> > > a good set of tools.
> >
> > Well, advertise your willingness on the 'net. I think you could
> > find small companies willing to pay for such a tool. You couldn't
> > get much money from any one of them, but if there are enough
> > takers, you could have a reasonable amount in your disposal.
> > I can also imagine that the Linux people who have to
> > struggle with Windows to do HW design would chip in too.
> 
> As long as you are writing software for FPGAs, you can really make a
> name for yourself and maybe a buck or million by developing a true set
> of tools to support the design and configuration of partially
> configurable chips. One of my applications uses four small chips because
> we need to load three of them depending on the hardware attached. Sort
> of a plug-n-play thing. If we could do the same thing within a single
> chip, it would save me a lot of board space and likely a few bucks on
> the chip(s).
> 
> Many vendors support partial reconfiguration in the hardware, but no one
> that I am aware of supports it in the development software. It doesn't
> seem like a hard thing to do. It just isn't done.
> 
> --
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> 
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
> 
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
> 
> Internet URL http://www.arius.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26457
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Ray Andraka <ray@andraka.com>
Date: Mon, 16 Oct 2000 23:27:35 GMT
Links: << >>  << T >>  << A >>
There are problems better suited to a microprocessor, in which case I go hire
the guy who does software for a living.  For hardware designs, there really is a
dearth of hardware designers that understand computer arithmetic and hardware
algorithms, which is why I mentioned training those folks (they presumably
already have a background in digital logic which encapsulates the concurrency
and timing issues, and most have had at least a brush with fixed point computer
arithmetic).

As for 6 months with a hardware designer, I think you'll find that a software
solution of equal complexity will take about the same time to complete, assuming
competency on the part of both designers.  In my experience, it is usually the
software that becomes the long pole in the tent on projects that have a good
measure of both.  That said, if the design is one that will map comfortably into
a single DSP microprocessor, I usually advise the customer to stick with the
microprocessor solution because it is currently much easier to find a software
type knowledgable in algorithms than it is to find a hardware type familiar with
algorithms.

Jamie Lokier wrote:
> 
> Andy Peters writes:
> > Some of us (we call ourselves "hardware designers," or perhaps even
> > "electrical engineers") actually *do* have to deal with the tricky I/Os,
> > and crossing clock domains, and, oh, by the way, get the thing to work
> > in the $15 FPGA, rather than the $150 one.  Throwing expensive hardware
> > at a problem clearly IS a solution, but most customers are not willing
> > to pay that price.
> 
> Ha ha ha ha!!!  Thanks for that, ROTFL etc.
> 
> $135 per chip saving?  Against what, the cost of a capable "hardware
> designer" for 6 months?  For some problems, even 100 bigger FPGAs looks
> like an economic winner.  If they really were just $150 :-)
> 
> But that's not the more important issue.
> 
> Ray Andraka mentioned:
> > Or get the people using FPGAs to the stage where they can find and use
> > 'common computing knowledge', much more possible IMHO.  After all,
> > before microprocessors became common, hardware computation was the
> > only way.
> 
> A nice thought.  Unfortunately my experience with "hardware designer"
> types has made it clear they can be very stubborn about what types of
> problem they will work on, and what techniques they are prepared to use.
> 
> Some FPGA programming problems seem to be out of their domain.  Too
> complex.  Need a TCP stack in hardware?  Wanna try a web server for
> performance trials?  Not us, leave that to software guys and preferably
> on a CPU.  In fact a TCP stack on a mid-size FPGA is feasible (say a
> Flex10KE50), but the hardware designer mindset I've encountered simply
> refuses to work on such a problems.
> 
> At least until they know it can be done.
> 
> I don't want to tar all hardware designers with that brush -- but it is
> my experience with the ones I've worked with.
> 
> As someone once said, there is worrying about picoseconds and there is
> worrying about months.  Me, I strike a happy medium around 10ns :-)
> 
> -- Jamie

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26458
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Ray Andraka <ray@andraka.com>
Date: Mon, 16 Oct 2000 23:31:19 GMT
Links: << >>  << T >>  << A >>


Andy Peters wrote:
> 
> Jamie Lokier wrote:
> >
> > Andy Peters writes:
> > > Some of us (we call ourselves "hardware designers," or perhaps even
> > > "electrical engineers") actually *do* have to deal with the tricky I/Os,
> > > and crossing clock domains, and, oh, by the way, get the thing to work
> > > in the $15 FPGA, rather than the $150 one.  Throwing expensive hardware
> > > at a problem clearly IS a solution, but most customers are not willing
> > > to pay that price.
> >
> > Ha ha ha ha!!!  Thanks for that, ROTFL etc.
> >
> > $135 per chip saving?  Against what, the cost of a capable "hardware
> > designer" for 6 months?  For some problems, even 100 bigger FPGAs looks
> > like an economic winner.  If they really were just $150 :-)
> 
> Um, howzabout you do the following: put your $150 FPGA into a commercial
> product.  How much would that product have to cost the end user?
> 
> Now, put the $15 FPGA in the same product.  How much would THAT product
> cost?
> 
> If the product is too expensive, no one's gonna buy it.
> 
> Think of how much money the company can save if they choose the
> less-expensive component.  Multiply that savings by 100K units, and
> clearly that pays for that capable hardware designer.  A capable
> hardware designer would do it right the first time -- there would be no
> need for the overkill hardware.  Of course, the assumption here is that
> the hardware designer is already on staff being paid a salary.
> 
> If the idea is for researchers to futz about with algorithms that are to
> be implemented in FPGAs, AND there's no "capable hardware designer"
> around, of course the cost of the board (and its FPGA) is in the noise.

And in those research applications, the reason they are considering an FPGA is
because a rack full of DSP processors isn't cutting it.  Programming that rack,
and making all the processors play nice together quickly becomes a daunting task
as the number of processors required increases.  I have seen numerous cases
where an entire rack is replaced by a single board containing no more than 4
FPGAs, and in most of those cases the hardware design time is a small fraction
of the software effort needed to make the equivalent processor based system
work.

> 
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26459
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Ray Andraka <ray@andraka.com>
Date: Mon, 16 Oct 2000 23:38:23 GMT
Links: << >>  << T >>  << A >>
After seeing yet another demonstration of amplify, I am still not convinced that
it is worth the huge premium over the 'amateur' version of Synplify.  The
floorplanning it does is about equivalent to using area constraints in the
graphical floorplanner.  Agreed, it does do some additional optimization on RTL
level coding based on the more accurate timing it gets from floorplanning. 
However, the marketing stuff tells me they get an average of 25% improvement
over a design with __Absolutely_no_floorplanning__.  Thing is you can get that
much improvement pretty easily without the extra optimization, or at most with
an iteration through the timing analyzer to see where the critical path is and
fix it.  If the tool were available for a small additional premium, I could
perhaps justify it, but certainly not for the ransom they demand for a tool that
does not do as well as my current flow.

"Keith R. Williams" wrote:
> 
> On Tue, 3 Oct 2000 05:59:31, Phil Hays
> <spampostmaster@sprynet.com> wrote:
> 
> > "Keith R. Williams" wrote:
> >
> > > ..Amplify is another issue altogether. I'd like some information
> > > from anyone with experience with it.
> >
> > I had written a longer response to this, and was cut off by Dr. Watson.  Joy.
> >
> > I have used Amplify.  I would recommend it if you writing HDL that pushes the
> > silicon for speed.  Amplify will allow for clock rate improvement by improvement
> > of mapping and by placement information.  I think it is a good tool.
> 
> Note that I'm now told I need a Synplify-Pro license as a *base*
> for Amplify (-pro is *not* a subset of Amplify).  I've been
> re-thinking my process and timing.  At this cost, $30K for
> Amplify on top of the $20K (plus maintenance) I've spent for
> Synplify makes this an expensive proposition indeed! ...and they
> want $3K for an upgrade to -pro from Synplify.  ...when is that
> IPO?
> 
> This was an *ouch* when I got a call from my rep this week. We'll
> see what my bean-counters say, but there isn't an infinite cash
> drawer.  This *is* a spendy tool indeed, if Synplify is not part
> of it (forget -pro).  The process in their PowerPoint-ware has no
> mention that -pro is required.
> 
> Confusion abounds.
> 
> ----
>   Keith

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26460
Subject: Re: 5V compatible Virtex
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 17 Oct 2000 11:44:37 +0900
Links: << >>  << T >>  << A >>
"Grumps" <grumps@here.com> writes:

> Thanks Ray & Kent. It'll be the XC2S50FG256 then. I know about the core
> voltage issues, but thanks for the reminder.

Just a warning, (I forget why you were originally looking for the Virtex and 
the Spartan-II to be the same, and I'm too lazy to check.)

The XC2S50 won't be compatable with the Virtex, becuase the smallest virtex 
is the '150.  The V150 and the 2S150 are compatable, and the V200 and 2S200 
are compatable.  Above that, it's virtex-only area.

The 2S50 is, I think, pin compatable with larger devices, but you have to 
be careful about which pins you use.

-Kent.

Article: 26461
Subject: Re: Xilinx and CD databooks (rant)
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 17 Oct 2000 11:56:55 +0900
Links: << >>  << T >>  << A >>


Austin Lesea <austin.lesea@xilinx.com> writes:
> I did not send any graph to Rick that I recall.
> What is it you would like to see a picture of?
> 
> Austin

Hi, Austin.

Rick mentioned a graph that illustrated the current draw during startup.

I'm hoping to figure out exactly how the V150 & S2150 behave with 
different power supply rise times.  We're having a problem involving 
current draw during live insertion; I'd like to see how much the 
Xilinx parts are contributing.

Thanks.

-Kent


Article: 26462
Subject: Re: ordered list
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 17 Oct 2000 12:00:18 +0900
Links: << >>  << T >>  << A >>
Hi, Jorg.

Jörg Ritter <ritter@informatik.uni-halle.de> writes:
> how would you implement an ordered list with
>   i) 8bit-integers as elements
>   ii) operations a)append, b)delete element i and c) foreach i { ... }
> 
> in an Fpga (XC4000) ?
> Foreach list a maximal length is given.
> Any idea ?

My first stab would be to use a RAM block.  Use 8 bits of the block as
data, and the rest to point to the next entry in the list.  Operations 
are then essentially the same as a linked list for software.  The 
control logic might get a bit heavy.

-Kent


Article: 26463
Subject: Re: 5V compatible Virtex
From: Ray Andraka <ray@andraka.com>
Date: Tue, 17 Oct 2000 04:19:09 GMT
Links: << >>  << T >>  << A >>
Virtex goes down to XCV50.  THe XCV50 and XC2S50 are pin and voltage compatible
with the exception of the temp diode pin (and if you tie that off correctly
there is no problem).  Same is true for the XCV100 and XC2S100.

Kent Orthner wrote:
> 
> "Grumps" <grumps@here.com> writes:
> 
> > Thanks Ray & Kent. It'll be the XC2S50FG256 then. I know about the core
> > voltage issues, but thanks for the reminder.
> 
> Just a warning, (I forget why you were originally looking for the Virtex and
> the Spartan-II to be the same, and I'm too lazy to check.)
> 
> The XC2S50 won't be compatable with the Virtex, becuase the smallest virtex
> is the '150.  The V150 and the 2S150 are compatable, and the V200 and 2S200
> are compatable.  Above that, it's virtex-only area.
> 
> The 2S50 is, I think, pin compatable with larger devices, but you have to
> be careful about which pins you use.
> 
> -Kent.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26464
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 17 Oct 2000 01:05:31 -0400
Links: << >>  << T >>  << A >>
I was trying to be "tongue in cheek". I know that it is not so simple. I
was responding to the tones of confidence that I hear from some of the
people suggesting that open source FPGA tools be developed. 

I can not say that I have ever tried to do a partial design. This is
mainly because there are no tools. So it is a bit of a chicken and the
egg problem. If no one works on these designs, there is no feedback on
how to make a tool. But if no one makes a tool, there will be no one
doing designs and providing feedback. 

As long as we are making a wish list for tools... it would be sooooo
nice if there were some sort of usable tool for development of partial
reconfiguration bitmaps. 


Ray Andraka wrote:
> 
> Errr, if it were easy, believe me the FPGA software folks would be all over it
> like fleas on a mongrel.  The problem as I see it is that the people doing the
> tools haven't *Done* a design attepting to use partial reconfiguration, and
> therefore don't have the slightest clue as to the problems that arise.  The same
> can even be said for much of the hardware 'support' for partial configuration.
> I've been there done that several times over, and it ain't a pretty picture,
> especially if you need to keep part of the logic alive and clocking while some
> other part is being reconfigured.
> 
> rickman wrote:
> >
> > Zoltan Kocsi wrote:
> > >
> > > Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk> writes:
> > >
> > > > >> (Linux people would jump up and down for a GPL'd tool)
> > > >
> > > > > You can bet your life on that.
> > > >
> > > > Well would they pay anything?  Get me a big enough wad of cash and I'll
> > > > personally put together a team of people and lead the project until it's
> > > > a good set of tools.
> > >
> > > Well, advertise your willingness on the 'net. I think you could
> > > find small companies willing to pay for such a tool. You couldn't
> > > get much money from any one of them, but if there are enough
> > > takers, you could have a reasonable amount in your disposal.
> > > I can also imagine that the Linux people who have to
> > > struggle with Windows to do HW design would chip in too.
> >
> > As long as you are writing software for FPGAs, you can really make a
> > name for yourself and maybe a buck or million by developing a true set
> > of tools to support the design and configuration of partially
> > configurable chips. One of my applications uses four small chips because
> > we need to load three of them depending on the hardware attached. Sort
> > of a plug-n-play thing. If we could do the same thing within a single
> > chip, it would save me a lot of board space and likely a few bucks on
> > the chip(s).
> >
> > Many vendors support partial reconfiguration in the hardware, but no one
> > that I am aware of supports it in the development software. It doesn't
> > seem like a hard thing to do. It just isn't done.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26465
Subject: Re: Asynchronous pulse generation with Spartan.
From: Eric Montreal <ervNOSPAM@sympatico.ca>
Date: Tue, 17 Oct 2000 06:17:15 GMT
Links: << >>  << T >>  << A >>
Hi,


rickman wrote:

> This will likely work. But it all depends on how you are using the part.
> This circuit depends as much (or more) on how you will be using it as it
> does on the internal construction of the circuit.
>
> So beware of async resets, even it they work the way they are intended!

Your answer is interesting to me, because you both state that there are no reasons
why it would not work, but at the same time, you suggest that I should better stay
away from it.
Looks like a kind of race condition between reason and doubt, and it's what most
peoples (including me, else I would not have asked !) seem to think about such designs.

This is not unlike the discussions about metastability.
Metastability could prevent anything that's not perfectly synchronous across the whole
system to work, but given appropriate measures (added delay tolerance, double latching,
etc ...) and by using probability analysis, it can be made manageable and reliable
within reasonable limits.

In facts what I'm searching are some rules that would apply to this kind of circuit
and would drive it from a "gray" (should work, but ...) area to a more defined area
(Will work if [whatever] rules are observed).

---------

A point in your answer that I don't completely get what you mean by "it all depends on
how you are using the part" ?

Do you refer to variable conditions such as voltage, temperature, lot to lot variation or
to routing delays or large output loads degrading the pulse waveform ?

reminder of the proposed schematic diagram: http://www3.sympatico.ca/erv/pulse.gif

From what I saw in the data sheet published timing, it should be safe, since the minimum
time through the "Delay" element is as long or longer than the published reset pulse
length even excluding the other elements used in the loop.

I can't see how it could *not* work since the output stays high as long as the CLR
have not been applied long enough to reset the FDC.
In the FDC, clear pulse length is around the same as propagation from CLR to Q, thus,
when the Q output goes low, the pulse needed to safely reset the FDC should be near
completion.
After that, the FDC output goes low and must trip through the loop, but, according to
the published timing, in the delay element inserts a minimum additional 4 ns that, in
itself should be enough to reset the FDC, thus adding a safety margin.

Also, unless I get it wrong, it seems that routing delay can only add to the loop time,
and thus the pulse width so it can not jeopardize the function.

Would this minimum timing be enough to get away from the "grey" area and be *sure* it
can be reliably used over the whole range of operating conditions ?

Am I missing something ?

-------------------

BTW, I could not find any data about the *maximum* delay from pin to ILD output when
the delay element is used, (since no maximum value is specified for it).

If more data is available on these delay elements, it would be very welcome !

best regards,

Eric.



Article: 26466
Subject: Re: ModelSim XE/Starter speed issues
From: "Dines Justesen" <dcj_k@rescom.dk>
Date: Tue, 17 Oct 2000 09:05:56 +0200
Links: << >>  << T >>  << A >>
I was told by the distributor that they stoped making that, so they only
have the standard versions now. Even if they do still sell it try comparing
the versions to ModelSim:

ModelSim XE Starter - AHDL Eval
ModelSim XE         - AHDL XE/SE
ModelSim PE         - AHDL PE
ModelSim SE         - AHDL EE

So just like ModelSim several versions are available, and unless you pay
quite a bit of money what you get is a "slow" version.

Dines
--
--------------------------------------------
Dines Justesen // dcj@rescom.dk
--------------------------------------------


"Geezer" <seely@fastq.com> wrote in message
news:39eb6126$1_3@goliath2.newsfeeds.com...
> Aldec has a Xilinx only simulator that is unlimited for under $3K in the
US.
> Available through Aldec or Insight.
> Gary
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:39E2BDBC.C378EC18@yahoo.com...
> > I think I need to stop asking questions when I really don't want to know
> > the answers. According to this web page, not only do they slow down the
> > XE starter simulator, but the XE full paid package is also slowed down
> > for large designs! This is a little bit amazing that anyone would have
> > the balls to do this and then *tell* you that they are doing it.
> >
> > Unless I am mistaken, the software is being crippled for larger designs
> > unless you pay a higher price. I guess I just need to learn a little
> > about marketing.
> >
> > What other simulators are out there that don't have these marketing
> > games with the price/performance?
> >
> >
> >
> > bob_42690@my-deja.com wrote:
> > >
> > > Rick,
> > > Check out http://www.xilinx.com/products/software/mxe.htm#products
> > > At this site, it says the XE version slows down at 8000 lines of code,
> > > and the XE starter is appropriate for designs less than 500 lines.
> > > Last I looked, the full XE edition cost $995 I believe for a year.
> > >
> > > Hope this helps,
> > >
> > > Bob
> > >
> > > In article <39E24FF1.A0B2EA3E@yahoo.com>,
> > >   rickman <spamgoeshere4@yahoo.com> wrote:
> > > > This may sound like a dumb question, but is the starter version of
> > > > ModelSim XE speed crippled above a certain design size?
> > > >
> > > > I have been increasing the size of my testbench and all of a sudden
> > > the
> > > > simulation slowed to a crawl. It had been running very nicely
> > > simulating
> > > > about 1 us of simulation time in 2 secs. Now it take about 20 or 30
> > > secs
> > > > for the same amount of simulation.
> > > >
> > > > At first I thought it was something in my code like an infinite loop
> > > or
> > > > other very inefficient construct. But I can get it to speed up by
> > > > cutting out code (about 10 lines) regarless of where I cut it out.
> > > When
> > > > I simulate the full size design, I get a message that says,
> > > >  "# WARNING: Design size of 513 statements exceeds ModelSim
XE-Starter
> > > > recommended capacity."
> > > >
> > > > Am I correct in assuming that this is an intentional limit that they
> > > put
> > > > in to encourage you to buy the upgraded tools? They don't make it
very
> > > > easy to figure this out, nor do they make it easy to get info on
what
> > > it
> > > > takes to upgrade. I could not find a link to their web page
anywhere.
> > > > The "About" box points you to Xilinx. I guess they are afraid of
> > > support
> > > > calls.
> > > >
> > > > Of course I found a web page by searching on their name. But they
> > > don't
> > > > give info on the "starter" package or about a direct upgrade.
> > > >
> > > > Anyone know if there is a simple upgrade to unlock the speed
governor?
> > > > Or do you just buy ModelSim XE full package? Anyone know what it
> > > costs?
> > > >
> > > > --
> > > >
> > > > Rick "rickman" Collins
> > > >
> > > > rick.collins@XYarius.com
> > > >
> > > > Ignore the reply address. To email me use the above address with the
> > > XY
> > > > removed.
> > > >
> > > > Arius - A Signal Processing Solutions Company
> > > > Specializing in DSP and FPGA design
> > > >
> > > > Arius
> > > > 4 King Ave
> > > > Frederick, MD 21701-3110
> > > > 301-682-7772 Voice
> > > > 301-682-7666 FAX
> > > >
> > > > Internet URL http://www.arius.com
> > > >
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> >
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> >
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com
>
>
>
>
> -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> -----==  Over 80,000 Newsgroups - 16 Different Servers! =-----



Article: 26467
Subject: Re: ModelSim XE/Starter speed issues
From: "Dines Justesen" <dcj_k@rescom.dk>
Date: Tue, 17 Oct 2000 09:06:05 +0200
Links: << >>  << T >>  << A >>
I was told by the distributor that they stoped making that, so they only
have the standard versions now. Even if they do still sell it try comparing
the versions to ModelSim:

ModelSim XE Starter - AHDL Eval
ModelSim XE         - AHDL XE/SE
ModelSim PE         - AHDL PE
ModelSim SE         - AHDL EE

So just like ModelSim several versions are available, and unless you pay
quite a bit of money what you get is a "slow" version.

Dines
--
--------------------------------------------
Dines Justesen // dcj@rescom.dk
--------------------------------------------


"Geezer" <seely@fastq.com> wrote in message
news:39eb6126$1_3@goliath2.newsfeeds.com...
> Aldec has a Xilinx only simulator that is unlimited for under $3K in the
US.
> Available through Aldec or Insight.
> Gary
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:39E2BDBC.C378EC18@yahoo.com...
> > I think I need to stop asking questions when I really don't want to know
> > the answers. According to this web page, not only do they slow down the
> > XE starter simulator, but the XE full paid package is also slowed down
> > for large designs! This is a little bit amazing that anyone would have
> > the balls to do this and then *tell* you that they are doing it.
> >
> > Unless I am mistaken, the software is being crippled for larger designs
> > unless you pay a higher price. I guess I just need to learn a little
> > about marketing.
> >
> > What other simulators are out there that don't have these marketing
> > games with the price/performance?
> >
> >
> >
> > bob_42690@my-deja.com wrote:
> > >
> > > Rick,
> > > Check out http://www.xilinx.com/products/software/mxe.htm#products
> > > At this site, it says the XE version slows down at 8000 lines of code,
> > > and the XE starter is appropriate for designs less than 500 lines.
> > > Last I looked, the full XE edition cost $995 I believe for a year.
> > >
> > > Hope this helps,
> > >
> > > Bob
> > >
> > > In article <39E24FF1.A0B2EA3E@yahoo.com>,
> > >   rickman <spamgoeshere4@yahoo.com> wrote:
> > > > This may sound like a dumb question, but is the starter version of
> > > > ModelSim XE speed crippled above a certain design size?
> > > >
> > > > I have been increasing the size of my testbench and all of a sudden
> > > the
> > > > simulation slowed to a crawl. It had been running very nicely
> > > simulating
> > > > about 1 us of simulation time in 2 secs. Now it take about 20 or 30
> > > secs
> > > > for the same amount of simulation.
> > > >
> > > > At first I thought it was something in my code like an infinite loop
> > > or
> > > > other very inefficient construct. But I can get it to speed up by
> > > > cutting out code (about 10 lines) regarless of where I cut it out.
> > > When
> > > > I simulate the full size design, I get a message that says,
> > > >  "# WARNING: Design size of 513 statements exceeds ModelSim
XE-Starter
> > > > recommended capacity."
> > > >
> > > > Am I correct in assuming that this is an intentional limit that they
> > > put
> > > > in to encourage you to buy the upgraded tools? They don't make it
very
> > > > easy to figure this out, nor do they make it easy to get info on
what
> > > it
> > > > takes to upgrade. I could not find a link to their web page
anywhere.
> > > > The "About" box points you to Xilinx. I guess they are afraid of
> > > support
> > > > calls.
> > > >
> > > > Of course I found a web page by searching on their name. But they
> > > don't
> > > > give info on the "starter" package or about a direct upgrade.
> > > >
> > > > Anyone know if there is a simple upgrade to unlock the speed
governor?
> > > > Or do you just buy ModelSim XE full package? Anyone know what it
> > > costs?
> > > >
> > > > --
> > > >
> > > > Rick "rickman" Collins
> > > >
> > > > rick.collins@XYarius.com
> > > >
> > > > Ignore the reply address. To email me use the above address with the
> > > XY
> > > > removed.
> > > >
> > > > Arius - A Signal Processing Solutions Company
> > > > Specializing in DSP and FPGA design
> > > >
> > > > Arius
> > > > 4 King Ave
> > > > Frederick, MD 21701-3110
> > > > 301-682-7772 Voice
> > > > 301-682-7666 FAX
> > > >
> > > > Internet URL http://www.arius.com
> > > >
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> >
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> >
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com
>
>
>
>
> -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> -----==  Over 80,000 Newsgroups - 16 Different Servers! =-----



Article: 26468
Subject: Re: 5V compatible Virtex
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 17 Oct 2000 16:15:37 +0900
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:
> Virtex goes down to XCV50.  THe XCV50 and XC2S50 are pin and voltage compatible
> with the exception of the temp diode pin (and if you tie that off correctly
> there is no problem).  Same is true for the XCV100 and XC2S100.

I sit corrected.

-Kent

Article: 26469
Subject: Re: Asynchronous pulse generation with Spartan.
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 17 Oct 2000 09:22:16 -0400
Links: << >>  << T >>  << A >>
Eric Montreal wrote:
> Your answer is interesting to me, because you both state that there are no reasons
> why it would not work, but at the same time, you suggest that I should better stay
> away from it.
> Looks like a kind of race condition between reason and doubt, and it's what most
> peoples (including me, else I would not have asked !) seem to think about such designs.
>
> A point in your answer that I don't completely get what you mean by "it all depends on
> how you are using the part" ?
> 
> Do you refer to variable conditions such as voltage, temperature, lot to lot variation or
> to routing delays or large output loads degrading the pulse waveform ?

My caution of using a design like this is not in the ability of such a
design to mimic the behavior of the chip, but rather a caution in how
you use the design just as I would caution you in how you use the chip. 

Part of the problem is the uncharacterized elements that you are working
with which will prevent you from having good data on the maximum width
of the generated reset pulse. This will prevent you from knowing the
maximum frequency of operation. After all, the internal FF reset pulse
must be gone a certain amount of time before you can set it again with
the clock. 

But I have not done a detailed analysis of your circuit or of any of the
timing issues. I will leave that to you since you seem capable. In
general you seem to understand the issues (temp, voltage, etc...). 

My main concern is that this circuit will be hard to test, simulate and
may give unexpected results depending on just how you use it in the
larger circuit. It not only has limitations in how you implement it, but
it has limitations in how you can use it. I guess my main concern is the
recovery time from rising edge of OExx to the rising edge of CPx when
CEx is asserted (tREC in the data sheet). This will be very poorly
characterized in your FPGA since this is determined by the max width of
the reset pulse which is determined by all the unknown stuff like the
routing, etc...

So if you are running slow and your other circuits are synchronous, you
can likely work with this.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26470
Subject: Re: ordered list
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 17 Oct 2000 09:13:05 -0700
Links: << >>  << T >>  << A >>
You are better off with Virtex, Virtex-E or Spartan-II, where you have many
4-k bits of BlockRAM to play with. ( And in Virtex-II you will get four
times larger Blocks...)

Peter Alfke, Xilinx Applications
=============================
Kent Orthner wrote:

> Hi, Jorg.
>
> Jörg Ritter <ritter@informatik.uni-halle.de> writes:
> > how would you implement an ordered list with
> >   i) 8bit-integers as elements
> >   ii) operations a)append, b)delete element i and c) foreach i { ... }
> >
> > in an Fpga (XC4000) ?
> > Foreach list a maximal length is given.
> > Any idea ?
>
> My first stab would be to use a RAM block.  Use 8 bits of the block as
> data, and the rest to point to the next entry in the list.  Operations
> are then essentially the same as a linked list for software.  The
> control logic might get a bit heavy.
>
> -Kent


Article: 26471
Subject: Has anyone done a biquad filter in xilinx FPGAs?
From: Tom <tom@antarestech.com>
Date: 17 Oct 2000 17:12:13 GMT
Links: << >>  << T >>  << A >>
Hi,

I know this is probably a shot in the dark but here goes.

I have a IIR filter function that I wish to implement in a Xilinx FPGA
with Parallel Distributed Arithmetic (PDA). I could, if I had to,
develop my own verilog module from scratch, but that would be time
consuming and I need to shave off a little development time. Xilinx has
FIR PDF and SDF cores available but not a Biquad, although I am told
that they are working on one (no release date). Converting one of their
FIR modules to an IIR module would be quite a "schlepp".

Does anyone know where I can find a verilog model of a PDA biquad or
IIR?

Thank You
Tom Cipollone
tom@antarestech.com




Article: 26472
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Neil Franklin <neil@franklin.ch.remove>
Date: 17 Oct 2000 22:41:18 +0200
Links: << >>  << T >>  << A >>
Andy Peters <"apeters <"@> n o a o [.] e d u> writes:

> Neil Franklin wrote:
> > Since
> > then I instinctively believe Assimov, that any sufficiently advanced
> > technology is indistinguishable from magic.
>
> Wasn't it Arthur C. Clarke who said that?

Now that you point it out, that could have been Clarke.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic

Article: 26473
Subject: VHDL vs Verilog
From: Neil Franklin <neil@franklin.ch.remove>
Date: 17 Oct 2000 22:57:42 +0200
Links: << >>  << T >>  << A >>
This is most likely newbie question no. <single-digit>.

In the various texts, posts here, listings of tools, etc I see
references to two languages: VHDL and Verilog. Both roughly the same
amount of references, so both seem to be widely used.

I assume these two to both be HDLs, just like there exist multiple
software programming languages (C, Fortran, Lisp, ...).

What are the differences? What the relative strenghts? What types of
jobs is one or the other best used for?

I know I could ask comp.lang.[vhdl|verilog], but I suspect the anser
there to be: ours is best. So what do you here on neutral ground think
of the two?


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic

Article: 26474
Subject: Re: VHDL vs Verilog
From: Ray Andraka <ray@andraka.com>
Date: Tue, 17 Oct 2000 21:35:29 GMT
Links: << >>  << T >>  << A >>
I don't think there is such a thing as neutral ground when it comes to that
subject.  It is more like religion.  That said, I use VHDL because it gives me
more control for getting the design to exactly what I want.  It is more verbose
than verilog, and can be more difficult to master (according to some).  However,
it has the controls I need to be able to do placement from within the code, and
use it as a generator as opposed to for synthesis.  As of last year, you
couldn't do everything I needed with verilog.

Outside of the US, VHDL is pretty much the standard.  In the US, verilog use is
fairly widespread, but then so is VHDL.  Comes down to what you are comforatble
with, and if it does what you need.

Neil Franklin wrote:
> 
> This is most likely newbie question no. <single-digit>.
> 
> In the various texts, posts here, listings of tools, etc I see
> references to two languages: VHDL and Verilog. Both roughly the same
> amount of references, so both seem to be widely used.
> 
> I assume these two to both be HDLs, just like there exist multiple
> software programming languages (C, Fortran, Lisp, ...).
> 
> What are the differences? What the relative strenghts? What types of
> jobs is one or the other best used for?
> 
> I know I could ask comp.lang.[vhdl|verilog], but I suspect the anser
> there to be: ours is best. So what do you here on neutral ground think
> of the two?
> 
> --
> Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
> Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com



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