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Messages from 26325

Article: 26325
Subject: Re: Xilinx, Altera stocks take dumps!
From: Netscape User <your_namel@email_address.net>
Date: Wed, 11 Oct 2000 20:18:36 -0700
Links: << >>  << T >>  << A >>
You think that's bad, check out Lucent's stock (NASDAQ:LU)
21 1/4    -32.27%  

Motorola almost dropped 20% today (Wednesday)

> At market close on Tuesday, both were down about 20%.  Something about
> "unable to meet demand."
> 
> Ooops.  Glad I didn't buy Xilinx stock a week ago, when I was talking to
> the Schwab guy about it.

Article: 26326
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Oct 2000 23:24:37 -0400
Links: << >>  << T >>  << A >>
Neil Franklin wrote:
> rickman <spamgoeshere4@yahoo.com> writes:
> > What exactly do you do with FPGAs?
> 
> Emulate historical CPUs. PDPs for the beginning.

I would be very interested in working on a PDP-8 or PDP-11 design. I
have been looking for a good processor to fit inside an FPGA and I think
the PDP-11 would do very well. I have no idea of the size. I also have
little idea of where to get the proper documentation. Do you have info
on this?

I am also toying with the idea of a Forth processor. My goal is to have
a processor which will work in on chip memory for small programs to
perform DMA and other board control functions. A simple 16 bit processor
could fit very well into the main FPGA on my board. 


> > Are you currently using any of the
> > low cost tools available?
> 
> As said: complete newbie to FPGAs, still trying to comprehend the
> field from not very friendly vendor web sites. A nice "Howto" in the
> Linux tradition would be really nice. Momental state of investigation
> seems to be: no Linux tools.

That is totally true except for some of the smaller chip vendors. I know
I have heard of tools for Linux, but they are not free (beer or speech). 


> > What background do you have with digital hardware?
> 
> EE BSc degree 11 years ago. TTL/74(LS)xx and 8051 level stuff with
> wire wrapping. Since then worked in software and sysadmin, so a bit
> rusted.
> 
> > Xilinx
> > may read this newsgroup, but I don't think these types of posts make
> > much of a dent.
> 
> What I fear to be the case. They are after all tech, and managment
> seems to ignore tech in every firm I know.

You can say that they ignore "tech". But they have to consider a lot
more than just "tech". While the tech people don't have to consider the
other issues. 

When I said that these types of posts do not make much of a dent, I
meant that companies like Xilinx don't pay a lot of attention to what
three guys say in a newsgroup. But if they hear 20% of their *paying*
customer base all say they want something, you can bet that both the
company and their competitors will have it available as soon as
possible. 

 
> > toolset under Linux and we still don't have that yet. People even run
> > the tools using WINE, but still no formal support from Xilinx.
> 
> I suppose I will have to do that then.
> 
> Or get the tools for Sun (if they are also in the free (beer)
> license). In what size are, say, 20x20 to 32x32 CLB parts
> netlists and bitstreams as files (my Sun access is over modem and
> metered telephone line).

I am not clear as to what you are asking. Are you saying that you are
worried about the download time for a completed bitstream file over a
phoneline? I think you will find the place and route time on even the
fastest Sparc to take a lot longer than the download time for a
configuration file. The file in binary is about 100K bytes for an XCV100
which is 20 x 30 CLB (quad LUTs and FFs). 

I can't say if the Sparc tools are free (beer) or not. But I believe
that Xilinx offers design software over the web. I think it is free for
smaller designs, but don't know for sure. You might think about checking
some of this stuff out for yourself, http://www.xilinx.com. Download
some datasheets and check out the tools. 

If you are working over a phone line, what happens if you try to run a
tool that is inherently graphical, like a chip editor? One of these
programs does not update the screen all that fast on a dedicated PC. You
might be much better off biting the bullet and working on a local PC. 

 
> rickman <spamgoeshere4@yahoo.com> wrote in <39E0F8B0.651932C1@yahoo.com>
> >
> > Neil Franklin wrote:
> > > >
> > > rickman <spamgoeshere4@yahoo.com> writes:
> > >
> > > > intermediate format is EDIF
> > >
> > > What is that? I have not seen that mentioned yet.
> >
> > EDIF is a standard file format for describing chip/board designs. The
> > format is limited to components and interconnects, to the best of my
> > knowledge.
> 
> > vendors. In a nutshell, you have two main parts, the front end and the
> > back end. The front end is used to capture a design either in schematic
> > form or in an HDL. A tool is used to generate FFs and gates in the
> > intermediate format, either a vendor specific format such as XNF
> > (Xilinx) or EDIF.
> >
> > The back end tools accept the gate level design and figure out how to
> > put that into the vendor's FPGA. This is by definition, vendor specific.
> 
> So generating EDIF or XNF ASCII files by some means and then compiling
> them to bitstreams on a Sun or WINE is all the tools I need?

You make that sound so simple, but yes. 

 
> > BTW, a tool like this will probably be used for many different chips
> > including CPLDs. I beleive many of those have published formats for the
> > programming data.
> 
> Unfortunately they have too few FFs for emulating CPU register sets
> (exeption seems to be Alteras MAX9000, but is that info available?).

I understand that that may not fit your immediate need. But if you are
planning on rolling your own VHDL compiler or any other significant part
of the tool chain, you won't be generating any FPGA bitstream for quite
a while. It might be easier to start with the parts you can get
documented and then add the FPGAs later after the vendors can take you
seriously or someone has spent the time and energy to reverse engineer
the bitstream formats. 

 
> > > > So where are all the open source VHDL compilers?
> > >
> > > Lack of people who know they can be made? Need to have the vendors
> > > back end, so why not just use their VHDL compiler?
> >
> > You tell me. Why do you want open source tools?
> 
> So I can run them on this box here, which implies being able to
> compile them, as the vendors don't seem to be offering them for it.
> 
> That is why I asked about if it was free beer or speach. I need the
> second for this.

What is "this box here"? Do the chip vendors offer tools for it? 

 
> > Are you saying that an
> > open source compiler is no good without an open souce back end?
> 
> If you have no back end, the front end is no use. IIf I have change my
> setup (install WINE, use remote Sun) to use a vendors back end, I
> can just as good use their front end, so why then spend time making
> an own front end.
> 
> At least that was my thought 2 days ago. Of course avoiding front end
> cost may make such a development still worth it.

If your design is not too complex, you will be able to use the free
(beer) tools when they come out later this month assuming you are
willing to use WINE and the tools work under WINE. That will definintely
be the path of least resistance assuming that you want to do chip
designs rather than change the way chips are designed. 

 
> > > > If GPL'd tools are so good, why aren't there more of them in the FPGA
> > > > world?
> > >
> > > Lack of the info needed to make the stuff?
> >
> > We are going in circles now. All the info you need to make an open
> > source compiler is in the VHDL LRM.
> 
> That I now understand, thanks to our post.
> 
> > That is the place to start
> > regardless of the status of the back end tools.
> 
> OK, if doing front end only development.

Even if you have the info you need to do a backend tool, the front end
tool will give you something you can work with using free (beer) backend
tools. But if you are writing the back end tools, you will still need
something to generate the EDIF files. The front end tools are only free
(beer) if you are willing to live with the sometimes severe limitations.
I just found out a couple of days ago that the WebPack ModelSim XE
simulator has a 500 line code limitation. Above that the thing slows to
a crawl. Even if you pay $1000, it has an 8000 line limitation. How's
that for justifying the need for free (speech) tools? 

 
> > An open source back end
> > is of no value with out the front end. The vendor's back end tools are
> > free (beer) or nearly so. The front end tools can be very expensive at
> > $5,000 and up! That's a lot of beer!!!
> 
> Actually after getting the point that the front ends are just VHDL or
> Verilog ASCII to EDIT of XNL ASCII, I may just look into what direct
> working with EDIF or XNL is like, or generating them by some own
> means. And then just compiling the bitstreams with vendor tools.
> 
> Do I get this right tht VHDL : EDIF = C : Assembler, sort of?

This is valid only in a limited, crude way. EDIF is just a way of
discribing a netlist. That netlist is very close to the hardware. So in
that sense, it is similar to assembly language. But EDIF is also
hardware independent. The tailoring is done by the specific elements
that are linked together. They are the basic blocks within the FPGA. 

You can generate EDIF from VHDL or C or even Forth if you have the mind
to do that. But others are working in that area (not the Forth... yet).
You should do some searching on the web to get info. Or if you ask
direct questions you will likely get some direct answers. I know that
there are tools to generate hardware from C. It may use VHDL as an
intermediate form however. 

The real trick to all this is to learn how to describe hardware in *any*
language. I have been designing digital hardware for twenty years. I
have been working with VHDL for about three. I still do not find it so
easy to write good VHDL that gives me just the hardware that I want. I
know that C would be worse and I'm not sure about Forth.  ;)

To get an idea of what you are up against, you can download, right now,
the WebPack tools that work with the CPLDs. The front end is independent
of the chip. I am currently designing a XCV100 using the VHDL tools
until I can get the full Foundation toolset. So far I am doing well and
expect to be fully simulated later this week. Then when the correct
tools are in, I can just pickup with my existing source and place and
route for the correct chip. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26327
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Oct 2000 23:43:41 -0400
Links: << >>  << T >>  << A >>
Neil Franklin wrote:
> > > Hmm, VHDL doesn't seem to me to have any of the above atributes.
> > > Sure, you can code hardware in VHDL as if it's a schematic (i.e.
> > > a markup language), but trust me. you soon learn that isn't the
> > > way to go.
> 
> Could you expand on this? What is the problem? What the better method?

The "better" method is to describe your design as an RTL (register
transfer level) or even behavioral description. The VHDL compiler will
then generate (synthesize) the logic to make it happen. Somewhat like
magic, but only until you learn what the compiler does with your code.
Until you learn, it is a PITA! You don't get at all what you wanted.
Example:

  TrxDataInit <= '1'  when SPIFSM = INIT else '0';

This sets TrxDataInit to a 1 when the state machine, SPIFSM, is in the
INIT state. I expect the FSM to be one-hot encoded. That will make this
line a simple connection between the two signals. If I don't tell VHDL
to use one-hot encoding, I get a binary encoded 6 bit field that
requires a lot of logic to generate TrxDataInit. 

  RcvDataRegister: process (SysClk, AsyncReset) begin
    if (AsyncReset = '1') then
      RcvDataReg <= (others => '0');
    elsif (rising_edge (SysClk)) then
      if (SPIRiseClkEn = '1') then
        if (SPI_CSNot = '0') then
          RcvDataReg <= RcvDataReg(14 downto 0) & SP_DOut; 
        else
          CTS <= RcvDataReg(9);
        end if;
      end if;
    end if;
  end process RcvDataRegister;

This is a 16 bit shift register with a clock enable and a load signal.
Oh, and I add a one bit register that gets loaded with the output of bit
9 when the register is not being shifted. Does this look anything like a
language you have seen before? It doesn't to me! This is logic
"synthesis"! 

I don't know that the concurancy issues are really that hard to live
with. That is the easy part for me. The hard part is getting the tools
to give you the logic you want the way you want. 

So download the free (beer) tools and try a few simple designs. What do
you have to lose???


-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26328
Subject: Re: Analogue FPGAs ?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Oct 2000 23:53:51 -0400
Links: << >>  << T >>  << A >>
"K. C. Lee" wrote:
> I told my sales rep that I hated the registration and asked for a CDROm
> instead.
> As for the semiconductor companies (eg. IDT) that SPAMED me, I told them
> I would
> not use their parts.

What did IDT do that you consider SPAM?


-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26329
Subject: Re: Analogue FPGAs ?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Oct 2000 23:55:57 -0400
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> Project I'm working on: Classified.
> When am I going to buy parts: 2010.
> How many I am going to buy: one.

Andy, you are just *not* a fun guy!!!

Ya' know, reps are people too! It doesn't really hurt to talk to them
once in awhile does it? You might be surprised at what they can do for
you sometime.


-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26330
Subject: Re: palasm
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Wed, 11 Oct 2000 21:26:33 -0700
Links: << >>  << T >>  << A >>
On Wed, 11 Oct 2000 09:34:10 +0200, "news tin" <rinux@iternet.it>
wrote:

>hi at all
>anyone use palasm???
>

yeah, I still use it once in a while. It's fast and simple, good for
simple 22V10 or 18CV8 things.

John


Article: 26331
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Phil Hays <spampostmaster@sprynet.com>
Date: Wed, 11 Oct 2000 22:58:33 -0700
Links: << >>  << T >>  << A >>
Phil Hays wrote:

> What I remember for the earlier comparison was that Synplify -Pro did a better
> job dealing with logic around IOB FFs, and the clock rate of the design was
> higher.  I'm still going to try to get a recent comparison.

Ok, I did it.

Synplify now correctly handles my test case logic around IOB FFs.


http://www.gmvhdl.com/hc11core.html

With a test design of the HC11 into a XCV200E-8-FG256 with the clocks inverted
(to avoid a bug), Synplify (version 5.3.1) output (using by Xilinx (3.1.01i)) is
a little slower that the output of Synplify-Pro (version 6.0).

29.630ns for the plain, 28.388ns for the -Pro (running a 28ns constraint on
everything).  Slowest path on both was clock to data bus out, with no DLL.  Yes,
I know I should have used the DLL.  I did not try to dig into the differences
between the designs to find out why there is difference.  No, I have not tried
to use Amplify or any other method to floorplan this.

Your mileage will vary, your design is different, some restrictions apply, next
release will make this all wrong...


-- 
Phil Hays

Article: 26332
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Phil Hays <spampostmaster@sprynet.com>
Date: Wed, 11 Oct 2000 23:10:26 -0700
Links: << >>  << T >>  << A >>
rickman wrote:

> I am also toying with the idea of a Forth processor. My goal is to have
> a processor which will work in on chip memory for small programs to
> perform DMA and other board control functions. A simple 16 bit processor
> could fit very well into the main FPGA on my board.

Might look at:

http://www.cs.cuhk.edu.hk/~phwl/msl16/msl16_vhdl.zip


-- 
Phil Hays

Article: 26333
Subject: Re: LUT to CLB assignment
From: "Dines Justesen" <dcj_k@rescom.dk>
Date: Thu, 12 Oct 2000 09:22:25 +0200
Links: << >>  << T >>  << A >>
Have a look at http://support.xilinx.com/techdocs/8055.htm and
http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/place1.htm

Dines

--
--------------------------------------------
Dines Justesen // dcj@rescom.dk
--------------------------------------------


"Lars" <Lotzen@intersci.com> wrote in message
news:ee6e421.-1@WebX.sUN8CHnE...
> Hi folks!
>
> I want to assign my LUTs to certain CLBs in the Virtex chip in my VHDL
code, e.g. LUT1 to CLBR1C3.S0.
> How can I do that?
>
> Thank you in advance!!!
>
> Lars


Article: 26334
Subject: Category : Subject:Floorplanning
From: "anand kuriakose" <anandkuriakose@yahoo.com>
Date: Thu, 12 Oct 2000 01:09:59 -0700
Links: << >>  << T >>  << A >>
I am a new user of Xilinx products(FPGA & CPLD).
Can somebody explain me what floorplanning is? And
whether floorplanning is applicable to FPGA and CPLD? Thanks in advance.

Article: 26335
Subject: Re: Category : Subject:Floorplanning
From: Lars Rzymianowicz <larsrzy@ti.uni-mannheim.de>
Date: Thu, 12 Oct 2000 10:23:51 +0200
Links: << >>  << T >>  << A >>
anand kuriakose wrote:
> I am a new user of Xilinx products(FPGA & CPLD).
> Can somebody explain me what floorplanning is? And
> whether floorplanning is applicable to FPGA and CPLD? Thanks in advance.

Well, basically you plan the chip 'floor' ;-)
Means, you assign regions on the chip to specific functional blocks.
This guides the Placement of cells and can result in better utilization
of FPGA/CPLD resources.
Yes, you can floorplan ASICs and FPGAs. For ASICs, it's normally
done inside the P&R tool. For FPGAs, there is a special Floorplan
tool, e.g. the Floorplan Editor of Xilinx.

Lars
-- 
Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713
email:    larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/

Article: 26336
Subject: Category : Subject
From: alten <alten2001@yahoo.fr>
Date: Thu, 12 Oct 2000 02:18:31 -0700
Links: << >>  << T >>  << A >>
I'm workind on a CCD video and a FPGA. I used a ILX718K from Sony. 

Is there someone who works on this sony device.

thanks

Article: 26337
Subject: Re: Xilinx, Altera stocks take dumps!
From: "EKC" <NOSPAMalpha3.1@ix.netcom.com>
Date: Thu, 12 Oct 2000 09:22:08 GMT
Links: << >>  << T >>  << A >>
    In that case, now would be a great time to load-up on Xilinx and Altera.

    The reason the stocks tanked is that two analysts downgraded the stocks.
However, judging from an interview of one of those analysts on CNBC, I think
that the analysts are lumping Xilinx and Altera in with Intel -- a great
fallacy not only because Intel follows a different business model but also
because the PLD market is still in its infancy.

-EKC


Andy Peters <"apeters <"@> n o a o [.] e d u> n o a o [.] e d u>> wrote in
message <8s2up1$203a$1@noao.edu>...
>At market close on Tuesday, both were down about 20%.  Something about
>"unable to meet demand."
>
>Ooops.  Glad I didn't buy Xilinx stock a week ago, when I was talking to
>the Schwab guy about it.
>
>-- a
>----------------------------
>Andy Peters
>Sr. Electrical Engineer
>National Optical Astronomy Observatory
>950 N Cherry Ave
>Tucson, AZ 85719
>apeters (at) n o a o [dot] e d u



Article: 26338
Subject: Re: Xilinx and CD databooks (rant) re: startup I
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 12 Oct 2000 07:59:25 -0700
Links: << >>  << T >>  << A >>
Rick,

I'd love to tell you that then next Spartan II part would have no start up
current, but I can't.  Spartan II is a shrink and process change to Virtex.
Some things were improved, but overall, the animal makes the same noises.

It is a project in the FPGA Lab to characterize all 'corners' of the process
(samples from different intentional splits) to determine if we can lower the
minimum startup current requirement for Spartan II.

We have made some changes to improve things, but the only way to be sure is to
measure lots of silicon,

Austin

rickman wrote:

> rk wrote:
> >
> > rickman wrote:
> > >
> > > This issue was covered a month or two ago and Peter Alfke indicated that
> > > pinout text files would be provided. I think he even made these files
> > > available for the Spartan II series.
> > >
> > > Now if he could do something about the high startup current of the
> > > parts.
> >
> > I've noted the high startup current in the Virtex parts.  What is the
> > mechanism for the high current?
> >
> > rk
>
> This is still a mystery to me. I have asked, here is the answer I got...
>
> ***************************************
> The current is a consequence of the race to power the memory cells that
> are
> used for the pass gate muxes vs. the memory cells used for everything
> else, so
> there is no way to affect it.  It all happens internally.  A slower ramp
> (e.g. 10
> ms vs 1 ms) has lower startup I.  Smaller parts can actually have worse
> turn on
> current that the largest parts (by 3:1, i.e. 500 mA worst case was for
> the smallest
> Virtex, not the largest).
> ***************************************
>
> I guess the pass gates are turned on until the memory is reset. Don't
> know...
>
> The part that bothers me is the higher current for the smaller parts!
> This is very counter intuitive. But since I don't understand the
> mechanism, I can't say anything about the effects.
>
> It just makes the parts very hard to use in small, power limted designs.
> I have to design my power supply for 500 mA per chip when I only expect
> to use half that power (or less) in normal operation. I wonder why
> Xilinx thinks this is not a problem?
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com


Article: 26339
Subject: Re: LUT to CLB assignment
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 12 Oct 2000 15:09:54 GMT
Links: << >>  << T >>  << A >>

>http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/place1.htm
>
>Dines

I hadn't realised that anyone was still looking at this - I've put in
a minor update and a couple of links in celebration. The top level is
actually:

http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/top.htm

Evan

Article: 26340
Subject: Re: Category : Subject:Floorplanning
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 12 Oct 2000 15:10:40 GMT
Links: << >>  << T >>  << A >>
On Thu, 12 Oct 2000 10:23:51 +0200, Lars Rzymianowicz
<larsrzy@ti.uni-mannheim.de> wrote:

>anand kuriakose wrote:
>> I am a new user of Xilinx products(FPGA & CPLD).
>> Can somebody explain me what floorplanning is? And
>> whether floorplanning is applicable to FPGA and CPLD? Thanks in advance.
>
>Well, basically you plan the chip 'floor' ;-)

Or you plan the chip *on* the floor. Really. I never saw it myself,
but a friend of mine had to visit a fab occasionally (in 1987, I
think) where they were laying out his chip. They stuck tape on a big
floor, and then took a photograph of it from the ceiling. Hence a
'floorplan'.

Evan

Article: 26341
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk>
Date: 12 Oct 2000 17:20:04 +0200
Links: << >>  << T >>  << A >>
rickman  writes:
> If you are working over a phone line, what happens if you try to run a
> tool that is inherently graphical, like a chip editor? One of these
> programs does not update the screen all that fast on a dedicated PC. You
> might be much better off biting the bullet and working on a local PC. 

Agree, however you can get a long way without doing anything graphical,
and the rest is painful but possible over compressed X or VNC.

These days I always run Maxplus2 via the command line and "make".
However, if I need to read some documentation, or search for some option
to tick, I'll need to pull out the GUI.
 
>> Unfortunately they have too few FFs for emulating CPU register sets
>> (exeption seems to be Alteras MAX9000, but is that info available?).

The bigger FPGAs have enough internal RAM to emulate CPU register sets.
Generally you get a more registers than you wanted, and not as wide as
you wanted though :-)

>> > You tell me. Why do you want open source tools?
>> 
>> So I can run them on this box here, which implies being able to
>> compile them, as the vendors don't seem to be offering them for it.
>> 
>> That is why I asked about if it was free beer or speach. I need the
>> second for this.

> What is "this box here"? Do the chip vendors offer tools for it? 

Fwiw, _my_ interest in open source tools has nothing to do with being
able to run them on my box, which runs Linux.  On the whole, the vendor
tools work ok under Wine.  Not that my box has enough RAM or MHz, so I
still use the big Sparc in the computer centre :-)
 
>> > An open source back end
>> > is of no value with out the front end. The vendor's back end tools are
>> > free (beer) or nearly so. The front end tools can be very expensive at
>> > $5,000 and up! That's a lot of beer!!!
>> 
>> Actually after getting the point that the front ends are just VHDL or
>> Verilog ASCII to EDIT of XNL ASCII, I may just look into what direct
>> working with EDIF or XNL is like, or generating them by some own
>> means. And then just compiling the bitstreams with vendor tools.
>> 
>> Do I get this right tht VHDL : EDIF = C : Assembler, sort of?

> This is valid only in a limited, crude way. EDIF is just a way of
> discribing a netlist. That netlist is very close to the hardware. So in
> that sense, it is similar to assembly language. But EDIF is also
> hardware independent. The tailoring is done by the specific elements
> that are linked together. They are the basic blocks within the FPGA. 

You can, however, write EDIF and XNF by hand or using Perl scripts.

It's worse than writing assembler for a CPU, but for small circuits
where you're designing all the logic explicitly, translating a
home-brewn language of equations into EDIF is plausible.

> You can generate EDIF from VHDL or C or even Forth if you have the mind
> to do that. But others are working in that area (not the Forth... yet).
> You should do some searching on the web to get info. Or if you ask
> direct questions you will likely get some direct answers.

> I know that there are tools to generate hardware from C. It may use
> VHDL as an intermediate form however.

EDIF in the case of Handel-C, which I use.

> The real trick to all this is to learn how to describe hardware in *any*
> language. I have been designing digital hardware for twenty years. I
> have been working with VHDL for about three. I still do not find it so
> easy to write good VHDL that gives me just the hardware that I want. I
> know that C would be worse and I'm not sure about Forth.  ;)

I've compared the performance of an application written in Handel-C,
which is similar to C, with the same application written by someone else
in AHDL, which is Altera's VHDL-like language.

Handel-C came out slower, as in 2/3 of the clock rate, but I was able to
write a more sophisticated pipeline to make up for that.  I don't have
an explanation for the lower clock rate.  Circuit area came out
identical -- that surprised me.

Interestingly, place & route was much faster with the Handel-C output,
for the same level of resouce utilisation.

On the whole my experience with Handel-C has been good.  I find it much
easier to write good Handel-C than good VHDL -- mainly because I can
read what I wrote and understand what it does!

I'm in a privileged position though -- most Handel-C users don't know
how the source is translated into logic.  I do have a very good idea,
and just like writing C for a CPU, I bear it in mind when coding.

enjoy,
-- Jamie

Article: 26342
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk>
Date: 12 Oct 2000 17:26:39 +0200
Links: << >>  << T >>  << A >>
Keith R Williams writes:
> My comrades are software types and think in C++.  There is a chasm
> here.  Neither is wrong.  Both are needed.  To think the programmers
> can design hardware is simply nuts.

You're aware of attempts to translate Java into hardware aren't you? :-)

-- Jamie

Article: 26343
Subject: Re: Category : Subject:Floorplanning
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 12 Oct 2000 11:43:59 -0400
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:
> 
> On Thu, 12 Oct 2000 10:23:51 +0200, Lars Rzymianowicz
> <larsrzy@ti.uni-mannheim.de> wrote:
> 
> >anand kuriakose wrote:
> >> I am a new user of Xilinx products(FPGA & CPLD).
> >> Can somebody explain me what floorplanning is? And
> >> whether floorplanning is applicable to FPGA and CPLD? Thanks in advance.
> >
> >Well, basically you plan the chip 'floor' ;-)
> 
> Or you plan the chip *on* the floor. Really. I never saw it myself,
> but a friend of mine had to visit a fab occasionally (in 1987, I
> think) where they were laying out his chip. They stuck tape on a big
> floor, and then took a photograph of it from the ceiling. Hence a
> 'floorplan'.
> 
> Evan

I think it comes from the way room and building layouts are planned.
They call that a floorplan. You move around the blocks that represent
the furniture and rooms much like we move the logic in a chip. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26344
Subject: Re: Xilinx and CD databooks (rant) re: startup I
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 12 Oct 2000 11:53:46 -0400
Links: << >>  << T >>  << A >>
Austin,

No one is blaming you personally, but I just don't understand how Xilinx
thinks they can sell these parts into a market that is pushing for lower
power consumption. Most of my designs until now have not had a problem
with the startup power. But all of my new products are very power
conscious. 

My understanding is that people like to use these smaller parts in
products like PCMCIA cards. In fact I thought, perhaps incorrectly, that
the TQ and VQ packages were mainly developed for the PCMCIA market. I
expect USB devices will also be a common use for smaller FPGAs. But
neither of these products will do well if they demand over 500 mA of
current at startup. 

I know that there is little you can do about it now. But it would be
nice if Xilinx made it a priority to greatly reduce this initial power
consumption in future products. After all, to the best of my knowledge,
this is not a problem I have using the Lucent parts. I know they are not
considered to be your main competitor, but they have some new, very
impressive parts coming out. Competition can come from all corners. 


Austin Lesea wrote:
> 
> Rick,
> 
> I'd love to tell you that then next Spartan II part would have no start up
> current, but I can't.  Spartan II is a shrink and process change to Virtex.
> Some things were improved, but overall, the animal makes the same noises.
> 
> It is a project in the FPGA Lab to characterize all 'corners' of the process
> (samples from different intentional splits) to determine if we can lower the
> minimum startup current requirement for Spartan II.
> 
> We have made some changes to improve things, but the only way to be sure is to
> measure lots of silicon,
> 
> Austin
> 
> rickman wrote:
> > The part that bothers me is the higher current for the smaller parts!
> > This is very counter intuitive. But since I don't understand the
> > mechanism, I can't say anything about the effects.
> >
> > It just makes the parts very hard to use in small, power limted designs.
> > I have to design my power supply for 500 mA per chip when I only expect
> > to use half that power (or less) in normal operation. I wonder why
> > Xilinx thinks this is not a problem?

-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26345
Subject: Re: Category : Subject:Floorplanning
From: "Walter Haas" <walter_haas@pmc-sierra.com>
Date: Thu, 12 Oct 2000 09:21:07 -0700
Links: << >>  << T >>  << A >>
Hi Anand,

Floorplanning is the way you place modules of your design inside the FPGA to maintain good data flow.

For instance, if you have a large design, Xilinx will start placing components without any knowledge of how the data is supposed to flow through the design. It only has timing and I/O constraints, and will try and place according to those constraints. Unfortunately, this leads to the "shotgun" effect, which, when you look the placement of all the components of your FPGA, looks like someone has let all your components fall like lego onto the floor.

As the designer, you already know (or should have a good idea) of how you want data to physically flow in the device. As in, take the inputs from one corner of the device, do computation in the middle, and then output on one of the other corners. Floorplanning is the method of telling Xilinx you want all the logic of the input block(s) to be in one corner, the computational stuff in the middle, and then the output block logic in another corner. For large designs, this is VERY advantageous, because routing delays (which are really the headache here) can be enormous, and thus kills your design.

I've used the AREA_GROUP constraints with success, so you could use those. Also, Xilinx has a modular design flow (so does Synplicity) that also might help. 

This generally isn't worth it unless you have tight margins,  or a large design. 

Hope this helps....

Walter

Article: 26346
Subject: Re: Analogue FPGAs ?
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 12 Oct 2000 10:00:33 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> Andy Peters wrote:
> > Project I'm working on: Classified.
> > When am I going to buy parts: 2010.
> > How many I am going to buy: one.
> 
> Andy, you are just *not* a fun guy!!!
> 
> Ya' know, reps are people too! It doesn't really hurt to talk to them
> once in awhile does it? You might be surprised at what they can do for
> you sometime.

Actually, I spoke to ours last week!  She gave me some good leads on the
fast ethernet stuff I've been looking for.

I think most of us would agree, though, that if we're just "surfing" for
potential parts, we'd rather not be bothered by salespersons.  

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26347
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 12 Oct 2000 10:08:30 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> That is totally true except for some of the smaller chip vendors. I know
> I have heard of tools for Linux, but they are not free (beer or speech).

I don't understand. Why should a tool be free, just because it runs on
Linux?

(I wouldn't MIND free tools, if they work, as much of the networking
stuff for Linux/Unix does.  I just haven't figured out how a programmer
can afford to eat if (s)he's giving away all of her work.)

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26348
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 12 Oct 2000 10:15:23 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
 
>   RcvDataRegister: process (SysClk, AsyncReset) begin
>     if (AsyncReset = '1') then
>       RcvDataReg <= (others => '0');
>     elsif (rising_edge (SysClk)) then
>       if (SPIRiseClkEn = '1') then
>         if (SPI_CSNot = '0') then
>           RcvDataReg <= RcvDataReg(14 downto 0) & SP_DOut;
>         else
>           CTS <= RcvDataReg(9);
>         end if;
>       end if;
>     end if;
>   end process RcvDataRegister;
> 
> This is a 16 bit shift register with a clock enable and a load signal.
> Oh, and I add a one bit register that gets loaded with the output of bit
> 9 when the register is not being shifted. Does this look anything like a
> language you have seen before? It doesn't to me! This is logic
> "synthesis"!

Well, you forgot the async reset for CTS. :)

And I would have written separate processes, which would be less
confusing (at the expense of more keystrokes).  To wit:

	RcvReg : process (clk, reset) is
	begin
	    if reset = '1' then
		RcvDataReg <= (others => '0');
	    elsif rising_edge(clk) then
		if (clken = '1') and (csnot = '0') then
		    RcvDataReg <= stuff;
		end if;
	    end if;
	end process RcvReg;

	CTSReg : process (clk, reset) is
	begin
	    if reset = '1' then
		CTS <= '0';
	    elsif rising_edge(clk) then
		if (clken = '1') and (csnot = '1') then
		    CTS <= whatever;
		end if;
	    end if;
	end process CTSReg;

The point, of course, is that the synth tool may or may not do what you
expect regarding the flop's clock enable.  And it probably doesn't
matter, assuming the logic is correct.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26349
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk>
Date: 12 Oct 2000 20:09:32 +0200
Links: << >>  << T >>  << A >>
Andy Peters writes:
>> That is totally true except for some of the smaller chip vendors. I know
>> I have heard of tools for Linux, but they are not free (beer or speech).

> I don't understand. Why should a tool be free, just because it runs on
> Linux?

> (I wouldn't MIND free tools, if they work, as much of the networking
> stuff for Linux/Unix does.

> I just haven't figured out how a programmer can afford to eat if
> (s)he's giving away all of her work.)

That's free as in beer (or as I prefer, alcohol-free cocktails :-)

"Free beer" tools are already available -- those are the tools that
FPGA vendors give away for zero $$$.

Free as in speech is another issue entirely, and is a reason why some
people would like access to open source tools.

It's possible to make money with free beer -- that works for FPGA
vendors, with the food coming from elsewhere (FPGA sales).

It is also possible to have free speech without free beer, as it were.
Companies like Red Hat do this.  Everything they write is given away,
and they make money selling support and pretty boxes.

enjoy :-)
-- Jamie



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