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Messages from 26300

Article: 26300
Subject: Re: Delay locked loop in a Spartan II
From: George Koukouras <gkouk@intracom.gr>
Date: Wed, 11 Oct 2000 12:10:14 +0300
Links: << >>  << T >>  << A >>
More explanation in the above problem
Suppose that the minimum delay which I can have in a Spartan II is 1 ns
My clock is 35.84 MHz which is about 28 ns period
That means my resolution is 1/28 *360 in degrees
So if I use a 32 to 1 multiplexer I can select delays of 1 ns.
if I select binary 3 of the mux the clock output would be 3ns delayed.
In other words 3/28 * 360 in degress different in phase.
Can anyone suggest me a vhdl code which does this and the delay
is independent of the temperature (suppose a take a differential delay)
Thanks


Article: 26301
Subject: Re: Testing embedded RAMs
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Wed, 11 Oct 2000 11:21:09 +0200
Links: << >>  << T >>  << A >>
Adrian Dunn wrote:
> 
> A quick search on Altavista for idempotent and BIST came up with these two
> good links:
> 
> http://www.amis.com/datasheets/2page/memory_bist.html
> http://www.eecs.harvard.edu/cs245/papers/Davidb.html
> 
> Idempotent Coupling Faults -> transition on cell A causes fixed value on
> cell B
> 
> Not sure what a k-coupling fault is though....
> 
> "Patrick Schulz" <schulz@rumms.uni-mannheim.de> wrote in message
> news:39E1D3B7.15759446@rumms.uni-mannheim.de...
> > Hi there,
> >
> > sorry for being maybe off-topic to FPGAs, but there is a good chance for
> > an answer in this group as far as I prize the contents of the posted
> > messages.
> > I posted this message already to comp.arch. Unfortunately without
> > response.
> >
> > Does anyone know a good online source for information about RAM-BIST
> > algorithms and their impact on the different fault classes?
> > What I want to know is for example what k-coupling faults or linked
> > idempotent coupling faults are.
> >
> > Any help appreciated.

Dear Adrian,

thanks for the help. I found the second page via Google already, but
there was
no description of the fault classes.
The first page describes the fault classes, but I miss the information
about the test algorithm. 

If you find some more information, I would be happy to hear from you.

Thanks for the help

Patrick
-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713

Article: 26302
Subject: Constraints in FPGA Comp. II
From: Georg Heinrich <georg@eas.iis.fhg.de>
Date: Wed, 11 Oct 2000 11:44:12 +0200
Links: << >>  << T >>  << A >>
Has anybody expiriences with the setting of timing constraints with the
FPGA Compiler II
from Synopsys.
I want to set the Input delay to 10 ns after clk, but it generates 10 ns
before clk e.g. ...
Can anybody help me ?
with regards

Georg Heinrich

--

mail from: Georg Heinrich
mailto:georg@eas.iis.fhg.de
http://www.xgeorg.de




Article: 26303
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk>
Date: 11 Oct 2000 12:14:37 +0200
Links: << >>  << T >>  << A >>
Andy Peters writes:
> Some of us (we call ourselves "hardware designers," or perhaps even
> "electrical engineers") actually *do* have to deal with the tricky I/Os,
> and crossing clock domains, and, oh, by the way, get the thing to work
> in the $15 FPGA, rather than the $150 one.  Throwing expensive hardware
> at a problem clearly IS a solution, but most customers are not willing
> to pay that price.

Ha ha ha ha!!!  Thanks for that, ROTFL etc.

$135 per chip saving?  Against what, the cost of a capable "hardware
designer" for 6 months?  For some problems, even 100 bigger FPGAs looks
like an economic winner.  If they really were just $150 :-)

But that's not the more important issue.

Ray Andraka mentioned:
> Or get the people using FPGAs to the stage where they can find and use
> 'common computing knowledge', much more possible IMHO.  After all,
> before microprocessors became common, hardware computation was the
> only way.

A nice thought.  Unfortunately my experience with "hardware designer"
types has made it clear they can be very stubborn about what types of
problem they will work on, and what techniques they are prepared to use.

Some FPGA programming problems seem to be out of their domain.  Too
complex.  Need a TCP stack in hardware?  Wanna try a web server for
performance trials?  Not us, leave that to software guys and preferably
on a CPU.  In fact a TCP stack on a mid-size FPGA is feasible (say a
Flex10KE50), but the hardware designer mindset I've encountered simply
refuses to work on such a problems.

At least until they know it can be done.

I don't want to tar all hardware designers with that brush -- but it is
my experience with the ones I've worked with.

As someone once said, there is worrying about picoseconds and there is
worrying about months.  Me, I strike a happy medium around 10ns :-)

-- Jamie

Article: 26304
Subject: Re: Computer Architecture emulator on a Xilinx chip
From: Utku Ozcan <ozcan@nortelnetworks.com>
Date: Wed, 11 Oct 2000 13:41:32 +0300
Links: << >>  << T >>  << A >>
Mark Rawlings wrote:

> I am a final year Engineering undergraduate student at Bristol
> University. I have a project which is concerned with emulating computer
> architecture on an FPGA (Xilinx). I am researching methods of
> accelerating the computers performance.
>
> I will be exploring register file structures, instruction pipeline and
> instruction queue, and memory interleaving.
>
> I would be grateful for any sources of information on these areas (and
> maybe others). As I am just starting the project it doesn't matter how
> basic they are! Any basic computer architecture structures would be
> usefull.
>
> Many thanks
> Mark Rawlings
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Hennessy-Patterson's book "Computer Architecture" might be helpful.

Utku

--
I feel better than James Brown.




Article: 26305
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: murray@pa.dec.com (Hal Murray)
Date: 11 Oct 2000 10:54:16 GMT
Links: << >>  << T >>  << A >>


> Some FPGA programming problems seem to be out of their domain.  Too
> complex.  Need a TCP stack in hardware?  Wanna try a web server for
> performance trials?  Not us, leave that to software guys and preferably
> on a CPU.  In fact a TCP stack on a mid-size FPGA is feasible (say a
> Flex10KE50), but the hardware designer mindset I've encountered simply
> refuses to work on such a problems.

A common way to implement complex tasks (like TCP) in hardware is
to build a small CPU and turn it into a software problem.

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 26306
Subject: Re: Modular Exponentiation
From: "bubba" <Scott.Duplichan@compaq.com>
Date: Wed, 11 Oct 2000 07:44:46 -0500
Links: << >>  << T >>  << A >>
Here is one to look at:
ftp://ftp.rsasecurity.com/pub/pdfs/tr201.pdf


"Steve Su" <su@wiliki.eng.hawaii.edu> wrote in message
news:Pine.HPX.4.03.10010101408020.9531-100000@wiliki.eng.hawaii.edu...
> I'm trying to implement modular exponentiation on an FPGA (specifically
> targetting a Xilinx Virtex V300) as part of a hardware implementation of
> a public-key encryption system. I'm trying to find an area efficient
> implementation of modular exponentiation.  I've come across several
> algorithms which should help make my design more efficient, including the
> square-and-multiply and Montgomery's multiplication algorithms.
>
> While both methods seem fairly straight-forward, there are some parts
> which aren't too clear to me.  This may be because I lack a background in
> modular arithmetic.
>
> The thing that I need help with right now is the algorithm for Montgomery
> reduction of an integer.  The algorithm I've found is:
>
>    Given a prime M, and a radix R > M, m = bit-length of M
>    MRED(T), T < RM, R=2^m, gcd(M,R) = 1
>      U = TM' mod R
>      t = (T + UM) / R
>      IF t >= M RETURN t - M
>      ELSE      RETURN t
>
>    t = TR' mod M
>
> One of the conditions for the reduction is that:
> RR' - MM' = 1
>
> What I want to know is, where does M' and R' come from? (i.e. How do I
> calculate M' and R'?)  I've also noticed that some papers use R' while
> others use the notation R^-1.  Is there a difference?
>
> I've tried looking at the Montgomery's paper, "Modular Multiplication
> without Trial Division" as well as other papers on Montgomery
> multiplication, but I haven't found anything particularly helpful.
>
> Also, is the use of Montgomery multiplication and the square and multiply
> algorithm the best (resource-wise) approach to use when attempting to
> implement modular exponentiation in hardware?
>
> If anyone could provide with some help on this, I would really appreciate
> it.  Seeing someone's VHDL implementation would be nice, but I really want

> a good grasp of the fundamentals rather than just to copy code.  If anyone
> could recommend any good resources (books, websites, papers, etc) on this
> stuff, that would be a great help.
>
> If you could e-mail any responses to me that would be terrific.  Thanks in
> advance.
>
> -Steve
> su@wiliki.eng.hawaii.edu
>
>
>
>



Article: 26307
Subject: LUT to CLB assignment
From: Lars <Lotzen@intersci.com>
Date: Wed, 11 Oct 2000 07:46:34 -0700
Links: << >>  << T >>  << A >>
Hi folks!

I want to assign my LUTs to certain CLBs in the Virtex chip in my VHDL code, e.g. LUT1 to CLBR1C3.S0.
How can I do that?

Thank you in advance!!!

Lars

Article: 26308
Subject: Re: palasm
From: "Dan Kuechle" <dan_kuechle@i-tech.com>
Date: Wed, 11 Oct 2000 15:20:43 GMT
Links: << >>  << T >>  << A >>
Many, many years ago.  Then I switched from 22V10's to Xilinx 9500 series
for my PAL / CPLD needs and have never looked back.

news tin <rinux@iternet.it> wrote in article
<8s14si$2io$1@nslave2.tin.it>...
> hi at all
> anyone use palasm???
> 
> 
> 

Article: 26309
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk>
Date: 11 Oct 2000 17:37:00 +0200
Links: << >>  << T >>  << A >>
Hal Murray writes:
>> Some FPGA programming problems seem to be out of their domain.  Too
>> complex.  Need a TCP stack in hardware?  Wanna try a web server for
>> performance trials?  Not us, leave that to software guys and preferably
>> on a CPU.  In fact a TCP stack on a mid-size FPGA is feasible (say a
>> Flex10KE50), but the hardware designer mindset I've encountered simply
>> refuses to work on such a problems.

> A common way to implement complex tasks (like TCP) in hardware is
> to build a small CPU and turn it into a software problem.

A common variation is to design a custom processor with funky
instructions especially for the job.  Either way though, the hardware
guys don't finish the job.  It is of course ideal if you can get all the
complementary skills to work together in the same room.

-- Jamie

Article: 26310
Subject: FPGA PCB design examples
From: Jon Seddon <js297@ecs.soton.ac.uk>
Date: Wed, 11 Oct 2000 16:39:41 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm going to have to design my own PCB with a Xilinx 4000 series FPGA on
it. I was wondering if anyone knew of example designs on the web?


Many thanks,


Jon

=====================
Jon Seddon
js297@ecs.soton.ac.uk




Article: 26311
Subject: Re: LUT to CLB assignment
From: Steven Derrien <sderrien@irisa.fr>
Date: Wed, 11 Oct 2000 17:39:41 +0200
Links: << >>  << T >>  << A >>


Lars wrote:
> 
> Hi folks!
> 
> I want to assign my LUTs to certain CLBs in the Virtex chip in my VHDL code, e.g. LUT1 to CLBR1C3.S0.
> How can I do that?

Location constraints can only be applied to instanciaed modules, to do
it you have to use ATTRIBUTE in vhdl, see support.xilinx.com in answer
database ask for LOC and VHLD you should find all the details.


regards,

steven

> 
> Thank you in 
> 
> Lars

Article: 26312
Subject: Xilinx FDN Express vs. Base Express ??
From: sja@world.std.com (Stuart J Adams)
Date: Wed, 11 Oct 2000 16:06:17 GMT
Links: << >>  << T >>  << A >>
 Is it worth the extra $$ for Foundation/ISE
 Express vs. Base Express ?? I am doing 
 Spartan II designs so the only added features
 would be the FPGA Express graphical constraints 
 editor, Time Tracker and Vista GUIs. Are these
 worth the extra $$ (about $2000 extra) ?? 

 (So far I've just been putting my constraints
  in the UCF files - does FPGA Express do anything
  useful during synthesis with the constraints 
  if you put them in with the FPGA Express GUI ??)

-- Stuart


Article: 26313
Subject: Re: Analogue FPGAs ?
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 11 Oct 2000 10:05:33 -0700
Links: << >>  << T >>  << A >>
rk wrote:
> 
> > Rich,
> >
> > Two things:
> >
> > 1) They don't get much info from cookies.  Go through the anonymizer and
> > they won't get your IP address.
> >
> > 2) Give false info when you fill out the form.  It's not YOUR problem
> > that their database gets degraded!  And maybe they'll learn a lesson, or
> > three.
> 
> OK, I am computer illiterate.  Where would I find an anonymizer and how
> do I get one?  

http://www.anonymizer.com/

> Giving out false information is a pain in the butt, too.  I don't mind
> if a form pops up but there shouldn't be mandatory fields.  It's a
> pain.  It's a pain! IT'S A PAIN! YOU VENDORS HEAR THIS?  TELL YOUR
> SALESCRITTERS TO LEAVE US ALONE.  ESPECIALLY WHEN THEY DON'T EVEN READ
> THE DATA SHEET!!!!  I DON'T NEED TO BE QUIZZED ON WHAT PROJECT I AM
> WORKING ON, WHEN I AM GOING TO BUY PARTS, AND HOW MANY I AM GOING TO
> BUY.

Project I'm working on: Classified.
When am I going to buy parts: 2010.
How many I am going to buy: one.

> Now I shall eat dessert.

Now I shall eat some Cap'n Crunch.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26314
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 11 Oct 2000 10:24:11 -0700
Links: << >>  << T >>  << A >>
Jamie Lokier wrote:
> 
> Andy Peters writes:
> > Some of us (we call ourselves "hardware designers," or perhaps even
> > "electrical engineers") actually *do* have to deal with the tricky I/Os,
> > and crossing clock domains, and, oh, by the way, get the thing to work
> > in the $15 FPGA, rather than the $150 one.  Throwing expensive hardware
> > at a problem clearly IS a solution, but most customers are not willing
> > to pay that price.
> 
> Ha ha ha ha!!!  Thanks for that, ROTFL etc.
> 
> $135 per chip saving?  Against what, the cost of a capable "hardware
> designer" for 6 months?  For some problems, even 100 bigger FPGAs looks
> like an economic winner.  If they really were just $150 :-)

Um, howzabout you do the following: put your $150 FPGA into a commercial
product.  How much would that product have to cost the end user?

Now, put the $15 FPGA in the same product.  How much would THAT product
cost?

If the product is too expensive, no one's gonna buy it.

Think of how much money the company can save if they choose the
less-expensive component.  Multiply that savings by 100K units, and
clearly that pays for that capable hardware designer.  A capable
hardware designer would do it right the first time -- there would be no
need for the overkill hardware.  Of course, the assumption here is that
the hardware designer is already on staff being paid a salary.

If the idea is for researchers to futz about with algorithms that are to
be implemented in FPGAs, AND there's no "capable hardware designer"
around, of course the cost of the board (and its FPGA) is in the noise.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26315
Subject: Re: palasm
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 12 Oct 2000 07:41:43 +1300
Links: << >>  << T >>  << A >>
news tin wrote:
> 
> hi at all
> anyone use palasm???

 PALASM was one of the historical 'milestones', and can still
be used quite well for SPLD.
 ( Even it's predecesor, PLPL, is still out there )

 For CPLD's, the PALASM .PLA support is a little non std, 
( so you can't feed into many fitters ) and it lacks some of the
structure controls expected these days.

 For more up to date PLD tools, look at CUPL or ABEL.
There are free versions for SPLD.

 CUPL has a preprocessor, which I find very usefull.

Jim G.

-- 
= http://www.DesignTools.co.nz

Article: 26316
Subject: Re: Analogue FPGAs ?
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Wed, 11 Oct 2000 18:44:22 GMT
Links: << >>  << T >>  << A >>
Thanks Andy!!!!!!!!!!!!!!!!!!!!!


"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
news:8s26nk$uv3$1@noao.edu...
> rk wrote:
> >
> > > Rich,
> > >
> > > Two things:
> > >
> > > 1) They don't get much info from cookies.  Go through the anonymizer
and
> > > they won't get your IP address.
> > >
> > > 2) Give false info when you fill out the form.  It's not YOUR problem
> > > that their database gets degraded!  And maybe they'll learn a lesson,
or
> > > three.
> >
> > OK, I am computer illiterate.  Where would I find an anonymizer and how
> > do I get one?
>
> http://www.anonymizer.com/
>
> > Giving out false information is a pain in the butt, too.  I don't mind
> > if a form pops up but there shouldn't be mandatory fields.  It's a
> > pain.  It's a pain! IT'S A PAIN! YOU VENDORS HEAR THIS?  TELL YOUR
> > SALESCRITTERS TO LEAVE US ALONE.  ESPECIALLY WHEN THEY DON'T EVEN READ
> > THE DATA SHEET!!!!  I DON'T NEED TO BE QUIZZED ON WHAT PROJECT I AM
> > WORKING ON, WHEN I AM GOING TO BUY PARTS, AND HOW MANY I AM GOING TO
> > BUY.
>
> Project I'm working on: Classified.
> When am I going to buy parts: 2010.
> How many I am going to buy: one.
>
> > Now I shall eat dessert.
>
> Now I shall eat some Cap'n Crunch.
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>



Article: 26317
Subject: Re: palasm
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Wed, 11 Oct 2000 19:05:49 GMT
Links: << >>  << T >>  << A >>
It gets even better!  If you want to program a 22V10, why not use VHDL?
That way you program EVERYTHING in either Verilog or VHDL.
-Simon Ramirez, Consultant
 Synchronous Design, Inc.

P.S.  Palasm is now defined as the sensation I get when I'm with my wife!


"Dan Kuechle" <dan_kuechle@i-tech.com> wrote in message
news:01c03396$d11e2aa0$bcf262d1@Dan.i-tech.com...
> Many, many years ago.  Then I switched from 22V10's to Xilinx 9500 series
> for my PAL / CPLD needs and have never looked back.
>
> news tin <rinux@iternet.it> wrote in article
> <8s14si$2io$1@nslave2.tin.it>...
> > hi at all
> > anyone use palasm???
> >
> >
> >
>



Article: 26318
Subject: LCELL in MAX+plusII
From: "Igal K." <igalk1@unisor.com>
Date: Thu, 12 Oct 2000 00:21:00 +0200
Links: << >>  << T >>  << A >>
In the *.rpt file (report file) of MAX+plusII I saw that in implementation
of HDL
logic there are endless use of LCELL.
What is LCELL and how it can be useful for me?

Thanks in advance,
Vovo4ka.



Article: 26319
Subject: Re: Analogue FPGAs ?
From: de351@freenet.carleton.ca (K. C. Lee)
Date: Wed, 11 Oct 2000 19:53:50 -0400
Links: << >>  << T >>  << A >>
"S. Ramirez" wrote:
> 
> Rickman,
>      Lattice is going a little bit farther than most semiconductor
> companies.
>      When you fill out all that garbage to get into their web site, it DOES
> go somewhere!  It goes to many places, but one very important place it goes
> to, as far as you are concerned, is the local sales office.  They get a
> printout of everything you wrote.  Do not be surprised if a salesperson
> calls you nonchalantly just asking how you are doing, what are you working

A good/aggressive/helpful (depending on you see them) sales rep already
do 
that with or without you having to register. The whole point of the web
is 
that you get the info quick. It is a first screening before talking to
the rep.
I can get CPLD/FPGA info from Xilinx or Altera etc without registering.

If every time I have to spend 15 minutes on a new web site to register
and 
give out my blood type just to see if a part would do what I want, then
I 
am better off just calling the sales rep getting samples, CDROM and
databooks 
in the first place. A good sales rep would be able to tell you what your 
_other_ options might be and the availibility and pricing of the parts.

>      You might want to play along with his nonchalant approach and then ask
> him where he got his information.

I told my sales rep that I hated the registration and asked for a CDROm
instead.
As for the semiconductor companies (eg. IDT) that SPAMED me, I told them
I would 
not use their parts.

> -Simon Ramirez, Consultant
>  Synchronous Design, Inc.

K. C. Lee

Article: 26320
Subject: Xilinx, Altera stocks take dumps!
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 11 Oct 2000 16:55:51 -0700
Links: << >>  << T >>  << A >>
At market close on Tuesday, both were down about 20%.  Something about
"unable to meet demand."

Ooops.  Glad I didn't buy Xilinx stock a week ago, when I was talking to
the Schwab guy about it.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26321
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: krw@attglobal.net (Keith R. Williams)
Date: Thu, 12 Oct 2000 00:38:52 GMT
Links: << >>  << T >>  << A >>
On Tue, 3 Oct 2000 05:59:31, Phil Hays 
<spampostmaster@sprynet.com> wrote:

> "Keith R. Williams" wrote:
> 
> > ..Amplify is another issue altogether. I'd like some information
> > from anyone with experience with it.
> 
> I had written a longer response to this, and was cut off by Dr. Watson.  Joy.
> 
> I have used Amplify.  I would recommend it if you writing HDL that pushes the
> silicon for speed.  Amplify will allow for clock rate improvement by improvement
> of mapping and by placement information.  I think it is a good tool.

Note that I'm now told I need a Synplify-Pro license as a *base* 
for Amplify (-pro is *not* a subset of Amplify).  I've been 
re-thinking my process and timing.  At this cost, $30K for 
Amplify on top of the $20K (plus maintenance) I've spent for 
Synplify makes this an expensive proposition indeed! ...and they 
want $3K for an upgrade to -pro from Synplify.  ...when is that 
IPO?  

This was an *ouch* when I got a call from my rep this week. We'll
see what my bean-counters say, but there isn't an infinite cash 
drawer.  This *is* a spendy tool indeed, if Synplify is not part 
of it (forget -pro).  The process in their PowerPoint-ware has no
mention that -pro is required.

Confusion abounds.  

----
  Keith

Article: 26322
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: krw@attglobal.net (Keith R. Williams)
Date: Thu, 12 Oct 2000 01:28:31 GMT
Links: << >>  << T >>  << A >>
On Tue, 10 Oct 2000 03:13:50, Kent Orthner 
<korthner@hotmail.nospam.com> wrote:

> Keith?  
> 
> I'm confused.  You're saying I'm wrong, and then agreeing 
> with almost everything I say. I think.

Well, this thread is confusing, but it may be me.  I've been 
doing 7-day weeks and am burnt.  It looks like good weather this 
weekend, so I promised the wife I'd take her leaf-peeping. :-)

> krw@attglobal.net (Keith R. Williams) writes:
> > Well, it is a programming language.  The intention is certainly 
> > to abstract hardware, but it is a programming language.  The 
> > interesting thing about VHDL and Verilog (remember I'm a relative
> > newbie here) is the concurrancy.  Things one learns in 
> > "programming" simply don't work when things happen concurrenty.  
> > Trust me.  
> 
> I absolutely agree with you (And Andy).  "Programming" and "FPGA/ASIC/Hardware 
> design" are completely different.  One consists of a series of steps for a 
> CPU (A program!), and the other describes how hardware should work.  The
> thing is, I didn't thing that VHDL or Verilog (Or ABEL, etc.) ws called a 
> "programming language".  But that's just semantics.

It is a programming language.  All programming languages have 
their targets.  VHDL and Verilog are optomized for hardware 
simulation and synthesis.  Each are *very* different than what a 
programmer would consider a "programming language".  

As I pointed out the concurrancy issue is a biggie (the concept 
of time is the other).  Most programmers can't deal with 
multi-threading effectively, yet hardware is *always* 
"multi-treaded".

> Ah!  Maybe I posted out of order and that's confusing the whole thing?

Not really.
 
> > > Just like a netlist isn't a programming language, HTML isn't a programming
> > > language, (The 'M' doesn't stand for Programming!), SVF (Serial Vector Format) 
> > > isn't a programming language.
> > 
> > Hmm, VHDL doesn't seem to me to have any of the above atributes. 
> > Sure, you can code hardware in VHDL as if it's a schematic (i.e. 
> > a markup language), but trust me. you soon learn that isn't the 
> > way to go.  HDLs are a very different beast.  I've found (any) 
> > assembler trivial by comparison.
> 
> 
> I didn't mention any attributes, but that's besides the point.  I still 
> think we're agreeing, no?

We are.

> > > > > Anyone who can learn C can learn VHDL. 
> > > > 
> > > > ARRRGH!
> >  
> > > <shrug>  You're probably right there.  But anybody that can learn C can 
> > > learn electronics, too.  And spanish.
> > 
> > Good grief.  You are a nut!  ...or are you a troll?  No matter, 
> > you are *so* wrong!
> 
> Huh?  think of all your friends that know C.  Do you think that most of 
> them couldn't learn hardware if they wanted to?  Of course they could.  
> That in no way implies that it's the same as knowing software, just
> that it's learnable.

No.  I don't buy that at all.  There are many things about 
software that I don't grok, and there are many things about 
hardware they just can't get.  There is a very different mindset 
between hardware types and programmers.  Yes, I can program, but 
I think hardware, so program in assembler.  My comrades are 
software types and think in C++.  There is a chasm here.  Neither
is wrong.  Both are needed.  To think the programmers can design 
hardware is simply nuts.  

> > > Yup.  FPGAs are *just like* CPU's.  'cept they're not 'central'  and they
> > > don't 'process'.  They *are* units, though.  Saying an FPGA is like a CPU 
> > > is the same as taking a whole pile of 74HCxx series chips in your left 
> > > hand and calling *it* a CPU.  Or pieces of Lego!  Until you *make* 
> > > something with it, it's still nothing.
> 
> Oops.  i forgot the <Sarcasm> </Sarcasm> delimiters. My bad.

Well...  ;-)

> > Well, I see you have experience on "nothing".  Sorry, but you 
> > have not the first clue how to get to first base!  
> 
> I'll just ignore this bit.

..thank you.

> > I think it's rather arrogant for a "C programmer" to think they 
> > understand hardware.  "C programmers" don't need to know about 
> > concurrancy, and if you did you would sh!t.  ...and that's only 
> > the start of your problems.
> 
> I'm not a C programmer.  Once again, I think this rant was aimed 
> at someone else!  Besides that, I agree with you.  Software design
> and Logic design are *completely different*.

Hmmm, my aim may indeed be off.

----
  Keith


Article: 26323
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: krw@attglobal.net (Keith R. Williams)
Date: Thu, 12 Oct 2000 01:32:41 GMT
Links: << >>  << T >>  << A >>
On Tue, 10 Oct 2000 18:20:33, Andy Peters <"apeters <"@> n o a o 
[.] e d u> wrote:

> Ray Andraka wrote:
> > 
> > Perhaps it is a disservice calling it PROGRAMMABLE logic.  Seems to evoke
> > thoughts of cpus to the uninitiated.  I suppose it doesn't help by spreading the
> > gospel that FPGAs can significantly outperform a CPU for a given task.
> 
> Ray,
> 
> "configurable logic"?
> 
> New acronym: FCGA.  Start spreadin' the news.

Naw, then we're going to confuse FPGA and FCPGA and all that crud
with Intel's "invention", the "Flip-Chip Pin-Grid-Array".  
..still not good enough.

I prefer to call it magic.  ;-)

----
  Keith

Article: 26324
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 12 Oct 2000 11:12:30 +0900
Links: << >>  << T >>  << A >>


krw@attglobal.net (Keith R. Williams) writes:
> <korthner@hotmail.nospam.com> wrote:
> Well, this thread is confusing, but it may be me.  I've been 
> doing 7-day weeks and am burnt.  It looks like good weather this 
> weekend, so I promised the wife I'd take her leaf-peeping. :-)

The "little woman" convincd me to go "Dam-peeping" this weekend.  
We leave sat'day night, spend the night on a bus, see the 
Dam & the Dam's tourist shop, get back on the bus, and be back 
in time for supper sunday night.  Envious, anyone?

> It is a programming language.  All programming languages have 
> their targets.  VHDL and Verilog are optomized for hardware 
> simulation and synthesis.  Each are *very* different than what a 
> programmer would consider a "programming language".  
> 
> As I pointed out the concurrancy issue is a biggie (the concept 
> of time is the other).  Most programmers can't deal with 
> multi-threading effectively, yet hardware is *always* 
> "multi-treaded".

Maybe I have my definitions mixed up.  But if nobody objects, in my mind, 
I'm going to go ahead and consider C++ a programming language and VHDL 
something else, a 'modeling language' or somewhat.  Although I'll admit 
<grudgingly> that it *does* fit the requirements of a programming language.

As I see it, designing hardware/ASICs/FPGA's, etc, is so considerably 
different than designing  software (Although there are similarities),
that it's a bit of a disservice to ourselves to call them both 
programming languages.  Although I use the 'programming language' VHDL,
I certainly don't consider myself a programmer.

> > > > > > Anyone who can learn C can learn VHDL. 
> > > > > 
> > > > > ARRRGH!
> > >  
> > > > <shrug>  You're probably right there.  But anybody that can learn C can 
> > > > learn electronics, too.  And spanish.
> > > 
> > > Good grief.  You are a nut!  ...or are you a troll?  No matter, 
> > > you are *so* wrong!
> > 
> > Huh?  think of all your friends that know C.  Do you think that most of 
> > them couldn't learn hardware if they wanted to?  Of course they could.  
> > That in no way implies that it's the same as knowing software, just
> > that it's learnable.
> 
> No.  I don't buy that at all.  There are many things about 
> software that I don't grok, and there are many things about 
> hardware they just can't get.  There is a very different mindset 
> between hardware types and programmers.  Yes, I can program, but 
> I think hardware, so program in assembler.  My comrades are 
> software types and think in C++.  There is a chasm here.  Neither
> is wrong.  Both are needed.  To think the programmers can design 
> hardware is simply nuts.  

You don't grok.  But that doesn't mean that you couldn't grok if 
you wanted to.

I'll clarify what I meant, so nobody thinks I'm nuts.  <grin>

I'm not saying that a programmer can design hardware.  I am saying 
that most programmers (Any that i have known) can, given the time 
and desire, become hardware designers and design hardare.  
Similarly, hardware designers don't necessarily know how to 
program, but can learn given the time and desire.

I never said a programmer could program VHDL.  I only said 
they could learn.

<stupid pun>
Personally, I poke around in Perl a bit, but I like to keep C++
away with my ten-foot-pole object.
</stupid pun>

-Kent



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