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spam , can you please refer me to this reference design ( their number will be fine ) . the only two reference designs that can be related to DDR SRAM , that I've found are : QDR SRAM controller and DDR SDRAM controller. thanks , Eyal spam_hater_7@email.com (Spam Hater) wrote in message news:<3cd933cf.3018963@64.164.98.7>... > Xilinx has two DDR reference designs available for free. > > And (almost) worth every penny. > > > > On 8 May 2002 00:45:00 -0700, eyals@hywire.com (Eyal Shachrai) wrote: > > >Hi , > > > >I'm working on a project which involves a xilinx's virtex-ii fpga. > >the core of this fpga will run with a 125 MHz clock and interface with > >a 250 MHz data rate DDR SRAM. > >I would like to know whether xilinx have a reference design of a DDR > >SRAM controller. and if not , would it be smart to use the QDR > >referance design (xapp 262) with some modifications , as a DDR > >controller? > > > >Thanks > > Eyal.Article: 43001
Phil Connor and others wrote: [snip] Thanks everyone for your help. It turned out my problem was much simpler than it seemed. Fundamental to my design was the counter which sequences things. Unfortunately, I didn't think of the counter as part of the "state", and thus wasn't registering it. Once I changed the design to do that, the rest fell into place. So, memo to self - anything that is part of the state of the machine, such as counters etc must be registered, not just the current_state and next_state signals! Now I've got a reasonably generic framework for these kinds of state machines, they're so much easier to design. Thanks again, Regards, JohnArticle: 43002
I have a design which hardly fits in the device I'm implementing it on. I intend to eliminate the heirarchy on some of the modules of the design for better optimization. The option in XST only allows to preserve/eliminate hierarchy on the top level. Is there a way in XST to preserve/eliminate the hierachy or "dont_touch" on some of the modules only, just like the express constraints editor in FPGA Express? I've tried using the XST Constraints File but not all of the modules that I indicated were flattened. Some of the modules' hierarchy still exists...worst, the implementation tools report an error in EDF generation. Can anyone provide an example as how to use Constraints File? The constraints manual from xilinx doesn't help much because it lacks examples. I'd really appreciate any info regarding this matter.Article: 43003
<hamish@cloud.net.au> wrote in message news:3cd92e0f$0$15472$afc38c87@news.optusnet.com.au... > H.L <alphaboran@yahoo.no-spam.com> wrote: > > Hello all, > > in the ucf file I have some signals LOC constrained, some of them I want to > > be of LVDS standard. During PAR I get the following: > > > WARNING:Place:1866 - The IOB output XXXXX needs an another > > associated output to complete the LVDS pair requirement. > > > ERROR:Place:1868 - The IOB component YYY has an IO standard > > of LVDS which must be placed with locate constraints to specific IOB > > locations that support this standard. The current location AJ11 is not a > > possible differential signal location. > > > AJ11 is a IO pin in the Virtex-E I use. > > Does it have a differential name like IO_VREF_L122N_YY? No in the datasheet AJ11's description is just IO > > > AN23 is a IO_VREF_L122N_YY pin > > > Can someone tell me why these messages appear? > > Do you have both the P and N pins of the pair location constrained > to the appropriate pins? I think you need to. > Hmm, yes you are right.Thank you, I looked in the datasheet again and says that if you want a LVDS output you must instantiate a LVDS OBUF and then pass the signal from the P side and its inverted one from the N side of the pin. I have about 30 outputs in my FPGA (2 buses and some control signals), do I have to port map these signals in my code one by one ? > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 43004
This is a multi-part message in MIME format. --------------5E4F267B470D96AFAC89D069 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Austin Lesea wrote: > Slight modification: > > Anything is tolerant with 100 ohms (ie Virtex E and Virtex II with 100 > ohms are 5V tolerant). > Does it mean that it is better to provide 100 ohms resistors for SpartanII too? -- Regards, Pawel J. RajdaArticle: 43005
> 25 X 10 = violates the min freq in for HF mode, or the max freq out for LF mode > (not allowed). What's the range in each mode ? Philippe.Article: 43006
In article <20020508194554.00572.00010781@mb-md.aol.com>, Mikeandmax
<mikeandmax@aol.com> writes
>Jonathan!!!
wrote...
>
>>Lattice Semi have the ispPAC family which they acquired from a
>>small, now defunct startup whose name I've forgotten. It's a
>>configurable bag of gain blocks, filter blocks and suchlike
>>useful things.
>
>ispPAC is an all LATTICE development, begun in 1995 - lot of work and effort
>into making a digital CMOS process behave well enough for the designs to go.
>Devices have been in production and shipping since summer of 1999.
My apologies are in order, it seems.
There WAS an earlier effort - I STILL can't remember the name of the
startup company; they were offering product around 1995 - and when I
saw the Lattice parts I was convinced they had basically the same
architecture.
To make amends, I'll mention that ispPAC has the same straightforward
electrically-erasable programming interface as most other Lattice
CPLDs - which is certainly a Good Thing.
Interesting stuff, anyhow. Thanks for the clarification.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
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Article: 43007Hi All, Can anybody please tell me where can I get the information regarding the FPGAs,for which the "Power" Pins can be reconfigured. Please point me to the corresponding links. Thanks in advance. Regards - satyaArticle: 43008
Yesterday I discuss my Thesis regarding a QPSK modulator for space
application implemented on XCV1000, it have the maximum of the score
and this is also due to your help, I would want to say thanks to all
of you but expecially to:
Allan Herriman for the initial idea on the architecture of the
modulator,
Ray Andraka for the support in the implementation on FPGA
Brian Philopsky for its precision answering to unusual questions
Jacky Renaux for its support using Blockram
Peter Afke for its short answers
but I repeat, thanks to all of you 'cause I produced my Thesis and at
the same time I work for a software company so you were my only
technical reference, thanks to the newsgroup institution
Antonio D'Ottavio
Article: 43009"Petter Gustad" <newsmailcomp1@gustad.com> wrote in message news:m3u1pjrl1t.fsf@scimul.dolphinics.no > For volumes like that I would go for an ASIC using a PCI core where > you can get the HDL source (Synopsys, RaviCAD etc.). You can of course > make a FPGA prototype using the same core which will let you test your > design with all the various host bridges available. > > Petter Hi Petter, Would you have any links for info on the host bridges or other test techniques? Many thanks Phil -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 43010
I need some help, I'm designing and coding a PCI Ethernet adapter using the verilog language. Its something I want to do as a personel project and its not work related so I can't get any help there. The adapter will comply with PCI rev 2.2 and 802.3 standards. I have looked at both specs but they as you can expect neither spec make no reference to interfacing to the other. I have run into a few problems. 1) I need to know what happens when the ethernet card receives packets from another ethernet station? How is the data transfered to the CPU or Memory? I don't know if I need both a Master and a Target PCI state machine. All I know is that I think there are only two possible ways this can be achieved. a) See I'm trying to figure out if I need a master state machine in the PCI interface to initiate the transaction i.e. it would request the bus and perform a merory write. or b) The ethernet adapther receives the packet and notifies the pci core. The PCI core then aserts its INTC to the Interupt router would then assert its IRQ to the CPU. The CPU then initiates and interrupt acknowlegedment and the interrupt router then forwards an interruot vector fot the PCI card. This informs the CPU of the ISR (Interupt service routine) and it then initiates a read to the ethernet card. In this case the adapter card only needs to have a target state machine. Here's were I need help. Your responce is appreciated...... Shane Mulligan.Article: 43011
i wish people that double post will be reincarnated as the Spam they areArticle: 43012
i wish people that double post will be reincarnated as the Spam they areArticle: 43013
Take your pick. There are existing PCI ethernet cards fitting both of those descriptions. Generally, the simpler PCI cards incorporate a fairly small amount of RAM which they manage as a circular buffer into which packets are inserted. Most of the more sophisticated cards use memory structures in main (PCI) memory to store packets. Having the card write directly into main memory can result in a more efficient system since it avoids one entire copy of the data. I say "can be more efficient" because whether it actually is more efficient will depend on many factors, some beyond the control of the PCI card. -cd "Shane Mulligan" <mememeiii@hotmail.com> wrote in message news:c25fdd8.0205090442.50ba0b4@posting.google.com... > I need some help, I'm designing and coding a PCI Ethernet adapter using > the verilog language. Its something I want to do as a personel project > and its not work related so I can't get any help there. > > The adapter will comply with PCI rev 2.2 and 802.3 standards. I have > looked at both specs but they as you can expect neither spec make no > reference to interfacing to the other. > > I have run into a few problems. > 1) I need to know what happens when the ethernet card receives packets > from another ethernet station? How is the data transfered to the CPU or > Memory? I don't know if I need both a Master and a Target PCI state machine. > All I know is that I think there are only two possible ways this can be > achieved. > > a) See I'm trying to figure out if I need a master state machine in the PCI > interface to initiate the transaction i.e. it would request the bus and > perform a merory write. > > or > > b) The ethernet adapther receives the packet and notifies the pci core. > The PCI core then aserts its INTC to the Interupt router would then assert > its IRQ to the CPU. The CPU then initiates and interrupt acknowlegedment > and the interrupt router then forwards an interruot vector fot the PCI > card. This informs the CPU of the ISR (Interupt service routine) and it > then initiates a read to the ethernet card. In this case the adapter > card only needs to have a target state machine. > > Here's were I need help. Your responce is appreciated...... > > Shane Mulligan.Article: 43014
I think you also need to compile the supplied files (220pack.vhd and then 220model.vhd) into the lpm library (after doing the mapping). Ciao, Robert "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0205060752.2ec72f38@posting.google.com... > hi, > You need to map the simulation libraries in the modelsim directory to > your work library. Do the following in modelsim: > > vmap lpm <work library> > vmap altera_mf<work library> > > This should fix it. > > bye, > Prashant > > shenyun78@sohu.com (strong) wrote in message news:<8fb33227.0205050404.22acd6ad@posting.google.com>... > > I use Altera's LPM in my project,and I want to stimulate it by > > modelsim, > > but I do not know how to do because modelsim can not interpret the > > LPM?please help me,thanks.Article: 43015
Hello all, some questions for the LVDS pins in Virtex-E FPGAs.. For the LVDS inputs must I use only one pin? For example if I have a one-bit input the only rule is to constrain it in a IO_L#P or a IO_L#N pin? If I constrain a one-bit input to IO_L0P for example, can I assign the IO_L0N pin to another bit that is input in my design or this pin must be unused? For a one-bit LVDS output must I use 2 pins (the IO_L#P and IO_L#N)? So if I have a 16-bit bus that is output must I use 16x2=32 pins for it and instantiate the bus-bits one by one in my code in the way described in Xilinx Datasheet? The above are my main questions I hope somebode help me :) Thanks and Best Regards, HarrisArticle: 43016
Rick, The one thing you should not do is assume if you run an I grade part at C grade temps, you get one more speed grade. Just use the I or C grade parts with the speed grade as marked, and don't assume the I grade will be a n+1 C grade part. The I grade program tests to compliance with a particular speed grade set of specs for AC at 100 C, so it is guaranteed to be fast enough at 85C. It is also functionally tested at 100C. As the technologies get vastly more complex we may eventually have to have separate I and C grade speeds files for future families. We are not there yet. This may well prevent you from doing what you are trying to do (use I grade as C grade) -- right now, it is a big unknown what this separate speeds filing of I and C would have on the resulting designs. Austin rickman wrote: > That was what I was hoping. I have a broker offering to sell me a > number of these devices from a manufacturer's overstock, but they are > industrial temp. To make it worthwhile, I would need to use them on > both the comm and ind versions of the board. I just wanted to make sure > I would not have any problems. > > Now to see if I can get a better price than what disti will give. > > Peter Alfke wrote: > > > > Good question, and here comes the good anwer: > > There is only one speeds file for any part. The ac parameters are identical > > for the commercial and industrial part. Because it has to guarantee the same > > performance over a wider temperature range, the I part is better (faster), > > but all performance numbers are the same. > > This has been the rule in Xilinx since times immemorial, i.e. since 1985. > > > > Peter Alfke, Xilinx Applications > > =========================================== > > rickman wrote: > > > > > Can anyone say with any certainty that the timing of an XC2S200E-6FG456I > > > will be the same as the XC2S200E-6FG456C? I need to do a design for > > > both versions and we will be building boards with both versions of the > > > FPGA. Some will actually be industrial boards, but sometimes we will > > > use the industrial versions of the FPGA on the commercial temp boards if > > > that is the FPGA we have on hand. > > > > > > Will I expect to see any differences in timing between the three > > > verisons of the board (comm chips run at comm temps, ind chips run at > > > comm temps and ind chips run at ind temps)? I know the ind chips will > > > run better if kept within the comm temp range, but are the timing files > > > the same? If I do a design that meets timing for the comm temp chip, > > > can I expect that to meet timing in the ind temp chip at either temp > > > range? > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43017
Pawel, No need, Spartan II is 5V tolerant on those inputs so indicated (ie no clamp diodes). Austin "Paweł J. Rajda" wrote: > Austin Lesea wrote: > > > Slight modification: > > > > Anything is tolerant with 100 ohms (ie Virtex E and Virtex II with 100 > > ohms are 5V tolerant). > > > > Does it mean that it is better to provide 100 ohms resistors for SpartanII > too? > > -- > Regards, > Pawel J. RajdaArticle: 43018
Philippe, The ClKIN min and max must be met for the mode (LF or HF), the M and D must be met, and the CLKFX output must be within its min and max limits. Look at the datasheet, get out your calculator, and plug in the numbers, and if you meet all CLKIN, M, D, and CLKFX, you are OK. In this particular case, 10/1 times a 25 MHz input yields a 250 MHz output on paper, but the minimum CLKIN frequency in the datasheet for the HF mode is 50 MHz. No go. Austin Philippe Robert wrote: > > 25 X 10 = violates the min freq in for HF mode, or the max freq out for LF > mode > > (not allowed). > > What's the range in each mode ? > > Philippe.Article: 43019
"Paweł J. Rajda" wrote: > Austin Lesea wrote: > > > Slight modification: > > > > Anything is tolerant with 100 ohms (ie Virtex E and Virtex II with 100 > > ohms are 5V tolerant). > > > > Does it mean that it is better to provide 100 ohms resistors for SpartanII > too? No, not needed for Spartan-II or Virtex. 100 Ohm would do neither good nor harm... Peter AlfkeArticle: 43020
Falk Brunner wrote: > > "Paweł J. Rajda" <pjrajda@uci.agh.edu.pl> schrieb im Newsbeitrag > news:3CD8FD3A.C1616C09@uci.agh.edu.pl... > > Hallo, > > > > Are the TAP pins 5V tollerant in SpartanII/Virtex/VirtexII devices? > > SpartanII and Virtex are direct 5V tolerant. > Virtex-II needs a >100 OHm series resistor. > > -- > MfG > Falk Everyone seems to forget the VirtexE and the Spartan2E. They are NOT 5 volt tolerant. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43021
--------------1070BB63C6A9F01BBD84F02E Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Rick, We didn't forget. I thought it was already clear (but what do I know?). Virtex E and Spartan IIE also require a 100 ohm resistor for 5V tolerance. Oh, and to add another interesting note, some chips (not ours) claim to require external clamp diodes to 3.3 volts AND a 100 ohm resistor for 5V tolerance before configuration is complete. That is not the case with any Xilinx FPGA. If a clamp diode it is required, it is always provided by the Xilinx FPGA (ie Virtex II, Virtex II Pro), or the stress before configuration is well within the reliability of the process (Virtex E, Spartan IIE) before the diode is programmed to be connected, or the stress forever is well within process limitations (Virtex, Spartan II) when there is no diode, and thus it is of no concern whatsoever. Austin rickman wrote: > Falk Brunner wrote: > > > > "Paweł J. Rajda" <pjrajda@uci.agh.edu.pl> schrieb im Newsbeitrag > > news:3CD8FD3A.C1616C09@uci.agh.edu.pl... > > > Hallo, > > > > > > Are the TAP pins 5V tollerant in SpartanII/Virtex/VirtexII devices? > > > > SpartanII and Virtex are direct 5V tolerant. > > Virtex-II needs a >100 OHm series resistor. > > > > -- > > MfG > > Falk > > Everyone seems to forget the VirtexE and the Spartan2E. They are NOT 5 > volt tolerant. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43022
Shane Mulligan wrote:
>
> I need some help, I'm designing and coding a PCI Ethernet adapter using
> the verilog language. Its something I want to do as a personel project
> and its not work related so I can't get any help there.
>
I was just going to say, why design yet another PCI-to-Ethernet
bridge considering that there are already so many low cost (and low
quality ones using only 2-layer PCB.), but okay, it's a personal
project, then that's fine.
> The adapter will comply with PCI rev 2.2 and 802.3 standards. I have
> looked at both specs but they as you can expect neither spec make no
> reference to interfacing to the other.
>
> I have run into a few problems.
> 1) I need to know what happens when the ethernet card receives packets
> from another ethernet station? How is the data transfered to the CPU or
> Memory? I don't know if I need both a Master and a Target PCI state machine.
> All I know is that I think there are only two possible ways this can be
> achieved.
>
If you are going to implement a master (initiator) state
machine, it must be independent of a target state machine.
That's written under PCI 2.2 Specification 3.2.5.1's implementation note
mentions that. (P. 41)
It sounds like you don't own the actual PCI specification, but if you
are serious about doing a PCI interface, you better get one.
I find it a lot more helpful than PCI System Architecture or PCI
Hardware and Software.
Unfortunately, PCI Specification now costs $100 for non-PCISIG members.
It used to cost only $25, so I don't know why they have to charge more.
> a) See I'm trying to figure out if I need a master state machine in the PCI
> interface to initiate the transaction i.e. it would request the bus and
> perform a merory write.
>
If you are doing a PCI-to-Ethernet bridge, it should be able to
do initiator (bus master) transfer considering that most PCI-to-Ethernet
bridges sold right now do so.
> or
>
> b) The ethernet adapther receives the packet and notifies the pci core.
> The PCI core then aserts its INTC to the Interupt router would then assert
> its IRQ to the CPU. The CPU then initiates and interrupt acknowlegedment
> and the interrupt router then forwards an interruot vector fot the PCI
> card. This informs the CPU of the ISR (Interupt service routine) and it
> then initiates a read to the ethernet card. In this case the adapter
> card only needs to have a target state machine.
>
> Here's were I need help. Your responce is appreciated......
>
> Shane Mulligan.
The problem of a target only design is that, you will only get
fraction of the maximum performance (1/5 to 1/6 at the most. That means
less than 20MB/s for the regular 32-bit 33MHz PCI.), because the CPU
will have to be involved in every transfer, but also the CPU cannot
handle burst transfers well. (It doesn't burst read cycles at all.)
Also, how are you going to implement this chip?
If you are doing to use an FPGA, I will recommend using Xilinx
Spartan-II over other solutions considering that you can use the free
ISE WebPACK and ModelSim-XE Starter, and the availability of a low cost
PCI prototype board. (Insight Electronics Spartan-II PCI Development Kit
costs only $225.)
I have never had a good luck with Altera FPGAs when I ported my PCI IP
core, and since Altera FLEX10KE/ACEX1K have only one IOE FF per IOE
(Spartan-II has three IOB FFs per IOB.), you will likely have harder
times meeting timings with them.
Regards,
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 43023
Edzel wrote:
>
> I have a design which hardly fits in the device I'm implementing
> it on. I intend to eliminate the heirarchy on some of the modules
> of the design for better optimization. The option in XST only allows
> to preserve/eliminate hierarchy on the top level. Is there a way
> in XST to preserve/eliminate the hierachy or "dont_touch" on some
> of the modules only, just like the express constraints editor in
> FPGA Express?
>
> I've tried using the XST Constraints File but not all of the modules
> that I indicated were flattened. Some of the modules' hierarchy still
> exists...worst, the implementation tools report an error in EDF
> generation. Can anyone provide an example as how to use Constraints
> File? The constraints manual from xilinx doesn't help much because
> it lacks examples.
>
> I'd really appreciate any info regarding this matter.
Assume that you got 4 modules, module_a.v, module_b.v, and
module_c.v, module_d.v.
To prevent module_b and module_c from being flattened, the following
constraint file should prevent it.
___________________________________________________________________________
begin module_b
attribute keep_hierarchy of module_b : entity is "yes";
end module_b;
begin module_c
attribute keep_hierarchy of module_c : entity is "yes";
end module_c;
___________________________________________________________________________
To get the rest of the design flattened, just uncheck the Keep Hierarchy
option under Synthesize -> Properties -> Xilinx Specific Options or
Synthesis Options.
In this case, module_a and module_d should be flattened automatically.
Note that if you use a lot of blackboxes in your design (i.e.,
Using netlisted IP cores.), it might be better not to flatten the design
at all because I have seen XST dropping valid FFs from a design.
It took me 2 days to track down the problem, and the only way I solved
it was by looking at the EDIF file, and play around with synthesis
options.
Eventually, I notice that if I didn't flattening the design, the problem
didn't occur.
I believe this was a bug of XST, and if there is any doubt, always check
the EDIF file XST generates. (If you are using XST Ver. D or older. The
latest XST Ver. E generates only an encrypted .ngc file.)
Regards,
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 43024
Hello All,
The TimingAnalyzer Update Info
Version 0.71
New Features and Improvements
1 The 1st Release of a Processsor Support Package.
You can automatically draw read and write cycles for
the processors that are included in the package.
The first 2 are the MC68LC302 Microcontroller and
the MC68000 Microprocessor. Using scripts you can
add new processors or modify existing ones to extend the
capabilities. For example, Interrupt or DMA cycles
could be added to both models. See the application note
on the website for more information.
2 The 1st Release of the Delay-Path Editor. The feature
is not completely functional. The schematic like
editor that is used to build the delay-path is
operational. I included this feature as is to get
feedback from the user community on the user
interface and the concept itself.
When this feature in completely functional, a saved delay-path
could be added to a the timing diagram the same way a
Delay or Constraint is now.
This simplifies some of the time consuming work when doing
timing analysis and eliminates the need to draw intermediate
signals for each Delay and Constraint in the timing diagram.
3 You can now save Image Diagrams in Encapsulated
Postscript (EPS) file format.
4 New website
5 New application note for the Processor Support Package
www.timinganalyzer.net
info@timinganalyzer.net
------------------------------------------------------------------------
TimingAnalyzer Introduction
------------------------------------------------------------------------
The TimingAnalyzer can be used to draw timing diagrams of
digital interfaces and check for timing problems in
digital systems. Signals, clocks, buses, delays,
constraints, and states are easily added from the gui.
The diagrams can be saved as JPG, GIF, and EPS images.
Scripts can written in a Java like scripting language to
generate test vectors, input stimulus for simulators,
test benches, the timing diagram itself, or new features.
Minimum, typical, and worst case analysis can be performed to check
for timing problems in the design. Delays and constraints can be user
defined or specified from part libraries in text files. All files are
text formatted so the user can easily add, modify, or create new
libraries.
Changing clock frequencies, signal parameters, or library parts
allows the user to quickly check functionality with slower parts or higher
frequencies.
Written in Java, it runs on any platform that supports the
java runtime enviroment (JRE1.2.2) or JRE1.3.
It is being tested on Windows, Linux, and Solaris. Using JRE1.3
decreases memory requirements and improves performance.
FREE to everyone while in Beta Testing
Regards,
Dan Fabrizio
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