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Messages from 43200

Article: 43200
Subject: Virtex-E interconnection
From: "H.L" <alphaboran@yahoo.no-spam.com>
Date: Thu, 16 May 2002 14:18:51 +0300
Links: << >>  << T >>  << A >>
Hello all,
I have 2 Virtex-EM XCV800 (speed grade:6, BG560 package) FPGAs that I want
to interconnect. They have 4 buses in their interface at 155MHz, do you
think that using LVTTL pins is OK or must I use LVDS pins.. their connector
cable is pretty small (<10 cm).

Best Regards,
Harris



Article: 43201
Subject: Nios 32bit - simulation problem
From: "Matjaz Finc" <matjaz.finc@fe.uni-lj.si>
Date: Thu, 16 May 2002 14:30:39 +0200
Links: << >>  << T >>  << A >>
I have a problem with Nios (2.0) simulation in Modelsim Altera 5.5e. After
the SOPC builder configuration (and simulation contents setup of
peripherals) and generation I tried to simulate the original Altera 32bit
Nios vhdl example (standard_32). Modelsim seems to do the initialization ok
but when I tried to execute run command it terminates with the message:

# ** Fatal: Value -1742495648 is out of range 0 to 2147483647
#    Time: 0 ps  Iteration: 0  Instance:
/test_bench/dut/the_boot_monitor_rom/boot_monitor_rom_lane0
# Fatal error at
C:/vhdl/excalibur/nios2/examples/vhdl/standard_32/ref_32_system_sim/boot_mon
itor_rom_lane0_module.vhd line 50
#

I did everything step by step as required in the Altera's app note (app189 -
simulating nios embedded processor designs) but it worked only with 16bit
Nios configurations. None of 32bit functioned. I used the same settings in
both 16 and 32bit configurations: no flash, uart with divisor 2, RAM (int or
ext) with the same build file (e.g. hello_world.c), ... In all cases just
the equivalent 16bit version could be simulated.

What to do? Is it Nios or Modelsim problem?

Please help.

My OS: Win98 (I know Nios isn't 100% compatible but it fuctions ok with some
minor workarounds - but is it relevant in this case?)

Regards,

Matjaz




Article: 43202
Subject: Re: SPARTAN II - Master serial mode configuration problem
From: "C.W. THomas" <cwthomas@bittware.com>
Date: Thu, 16 May 2002 09:20:42 -0400
Links: << >>  << T >>  << A >>


I'd try messing with the pullup/pulldown settings for TDI and TCLK and maybe
TMS.

Good Luck;



"Joze Dedic" <joze.dedic@email.si> wrote in message
news:ac0163$dva$1@planja.arnes.si...
> I am trying to configure XC2S200 (FG456) 5C in master serial mode (M(2:0)
> all 0) from PROM XC18V02 - but the problem is that configuration does not
> succeed every time.
> FPGA DONE signal stays low and CCLK is running at 5 MHz whenever the cofig
> fails - but nPROGRAM and nINIT signals are high. I have even monitored the
> bitstream (DIN) of succeded and failed config - it started in the same
way.
> FPGA is located on PCI evaluation board (6 layers - one for 3.3 and one
for
> GND). On this EVB fits platform with SA1110. Thing is that config succeeds
> every time whenever I hold SA1110 in reset. This indicates on some noisy
> enviroment problem. I think...
> I have monitored core supply (2.5) and it is clean and stabile. There are
8x
> 10n, 8x 100n, 2x 1u, and 3x 10u F capacitators around FPGA.
>
> Are there any config setings that I should change - or it is just lack of
> blocking C and poor supply condition.
>
> I would like to mention that one board (luckily the first one) works fine.
I
> have no ideas more. Thanks for any advice.
>
> jOc
>
>



Article: 43203
Subject: Re: Virtex-E interconnection
From: Ray Andraka <ray@andraka.com>
Date: Thu, 16 May 2002 13:57:00 GMT
Links: << >>  << T >>  << A >>
155 MHz is pushing it for LVTTL for on-board connections, and pretty much out
of the question for going off board through a cable.  If this is a connection
on the board, you might look at some of the other single ended flavors, some of
them are a bit faster.  Also, consider signal integrity modeling software to
verify your layout.  For off-board, you probably should be using a differential
signal.

"H.L" wrote:

> Hello all,
> I have 2 Virtex-EM XCV800 (speed grade:6, BG560 package) FPGAs that I want
> to interconnect. They have 4 buses in their interface at 155MHz, do you
> think that using LVTTL pins is OK or must I use LVDS pins.. their connector
> cable is pretty small (<10 cm).
>
> Best Regards,
> Harris

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43204
Subject: extend jtag downloadcable
From: peeters_wim@hotmail.com (Wim Peeters)
Date: 16 May 2002 07:08:40 -0700
Links: << >>  << T >>  << A >>
Hello,

HAs anyone ever extended a jtag download cable up to 1-2 metres. What
I want to archieve is to doewload at a reasonable speed but without
using any buffers in the cable. I was thinking of using a "better"
cable than the standard flatcable.
My interface is a JTAG Technologies BV USB adapter JT3710. My device
is an Altera 3128.

What i have now is a clabel of approx. 1 metre but I have to adjes the
download speed from 25kHz to 5KHz. My target is to go back to 25kHz by
using a better quality cable.

Thanks in advance for your advise!

Wim Peeters

Article: 43205
Subject: Re: PCI Board Project
From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange)
Date: 16 May 2002 07:24:25 -0700
Links: << >>  << T >>  << A >>
Thank you all, the information you gave is very valuable.
The only reason I am dealing with the 4K line is economical (at least
by now, I hope so...). The XS40 eval boards use the XC4010XL.

Other question:
To get the FGPA configured, I will need to wire in the board a PROM
with the bitstream, right?

Thank you very much again, the promptness in the answers have
surprised me!
(Excuse my English, I am trying to improve it)

Mauricio Lange

Article: 43206
Subject: XC95108+XC4036EX
From: "Philippe Robert" <PhilippeR@sundance.com>
Date: Thu, 16 May 2002 15:34:16 +0100
Links: << >>  << T >>  << A >>
Hi,

Few years ago, we designed a board with an XC95108 and an XC4036ex. On that
board, the CPLD sends data to the FPGA. At that time the board was working
very well and we have never had any problems since. We have recently built
some more boards (nothing changed). The CPLD is from a different batch. The
boards, tested the same way, fail from time to time. It sounds like some
timings are too close to the tolerance and sometimes goes over it and makes
the system fail.
Does anyone know if the die of these devices have recently changed and what
influence it has on their behaviour ?

Thanks.
Philippe.



Article: 43207
Subject: Got to get those decimals in the right place on the slide rule .....
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 16 May 2002 07:44:20 -0700
Links: << >>  << T >>  << A >>
Oops.

Datasheet is right, my math is wrong.

150 mAHr button cell will last its lifetime (~15 years) at 100 nA per the
datasheet.  It turns out that we have even less current drain, but we can test
100 nA!

So the 1F supercap doesn't last as long as I (mis)calculated, but it does let
you change batteries, or sit around for a little while (231 days -- obviously
less due to leakage of the supercap, and the pcb).

Austin



Austin Lesea wrote:

> Rick,
>
> I'll see why the datasheet has this number....
>
> Austin
>
> Rick Filipkiewicz wrote:
>
> > Austin Lesea wrote:
> >
> > > The current drain is 0.1 nA, max (was not tested on early ES ... <snip>
> >
> > The Jan 2002 V-2 data sheet shows IBATT (max) = 100nA ?


Article: 43208
Subject: Re: Virtex-E interconnection
From: "H.L" <alphaboran@yahoo.no-spam.com>
Date: Thu, 16 May 2002 17:48:29 +0300
Links: << >>  << T >>  << A >>
Hmm I see, thanks Ray for you help :)
I will check the other single-ended pins, is there a free signal integrity
modeling software that I can download from the web?

Greetings,
Harris

"Ray Andraka" <ray@andraka.com> wrote in message
news:3CE3BB32.59217FF1@andraka.com...
> 155 MHz is pushing it for LVTTL for on-board connections, and pretty much
out
> of the question for going off board through a cable.  If this is a
connection
> on the board, you might look at some of the other single ended flavors,
some of
> them are a bit faster.  Also, consider signal integrity modeling software
to
> verify your layout.  For off-board, you probably should be using a
differential
> signal.
>
> "H.L" wrote:
>
> > Hello all,
> > I have 2 Virtex-EM XCV800 (speed grade:6, BG560 package) FPGAs that I
want
> > to interconnect. They have 4 buses in their interface at 155MHz, do you
> > think that using LVTTL pins is OK or must I use LVDS pins.. their
connector
> > cable is pretty small (<10 cm).
> >
> > Best Regards,
> > Harris
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 43209
Subject: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 16 May 2002 07:54:30 -0700
Links: << >>  << T >>  << A >>
Theron,

I won't then.

Austin


PS:  regular customers who need a "what if" can open a case on the hotline,
and request an IBIS simulation be run for just such a case.  University
customers are supported through a different system and program.  I would
hope that the university sponsering this would be at the cutting edge, and
have IBIS simulation tools available.  I will check on that.  I have run
the simulation, and the overshoot and undershoot is terrible, and the rise
and fall times are 1.4 ns for the fast corner, and 3.7 ns for the slow
corner.

Email me directly if you wish to receive the .jpg of the simulation.




"Theron Hicks (Terry)" wrote:

> Hi,
>     I am considering using a Spartan2E to generate a clock signal
> (amongst other things).  The clock will probably be driven by a slow
> LVTTL signal with a 12 mA drive current.  I am trying to decide whether
> to terminate this output and if so how to do so (source vs load
> termination, etc.)  To do so, I need to know what the rise and fall
> times of the output signal are.  Please do not tell me to use IBIS.  I
> am quite competent with SPICE and PSPICE but I have no experience with
> IBIS models and no availability to the software.  For this simple
> calculation I really don't need to use such tools anyway.  FYI the
> transmission line will be less than 0.3 meters
> (> 1 foot).  Load is one Spartan2E LVTTL input.  Frequency is 100MHz.
>     Alternatively, I could use the differential LVPECL capacity of the
> Spartan2E, but it appears to be overkill and would add an additional
> connector pair to the system.
>
> Theron Hicks


Article: 43210
Subject: Re: extend jtag downloadcable
From: "Luis Cupido" <cupido@mail.ua.pt>
Date: Thu, 16 May 2002 16:09:23 +0100
Links: << >>  << T >>  << A >>
I using one with 2.5m and it works ok.
Had no special care, just plug the cable and hit the button...

(On altera MAX 7000s using MAXIIplus and byteblaster,
can't say about others... but would imagine it to be
ok also)

LC.


"Wim Peeters" <peeters_wim@hotmail.com> wrote in message
news:8f00e675.0205160608.771e20f9@posting.google.com...
> Hello,
>
> HAs anyone ever extended a jtag download cable up to 1-2 metres. What
> I want to archieve is to doewload at a reasonable speed but without
> using any buffers in the cable. I was thinking of using a "better"
> cable than the standard flatcable.
> My interface is a JTAG Technologies BV USB adapter JT3710. My device
> is an Altera 3128.
>
> What i have now is a clabel of approx. 1 metre but I have to adjes the
> download speed from 25kHz to 5KHz. My target is to go back to 25kHz by
> using a better quality cable.
>
> Thanks in advance for your advise!
>
> Wim Peeters



Article: 43211
Subject: Re: Architecture for high-level reconfigurable computing
From: "Bryan" <bryan@srccomp.com>
Date: Thu, 16 May 2002 09:09:51 -0600
Links: << >>  << T >>  << A >>
www.srccomp.com



"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:abug8b$4al@gap.cco.caltech.edu...
> "Steve Casselman" <sc.nospam@vcc.com> writes:
>
> >Yes the other way in C is to have functions that run in parallel like
> >threads. The compiler must be smart enough to infer real parallel
hardware.
> >Also if you take the list operator and define the behavior as fully
parallel
> >then C does not seem sequential.
>
> Say I take an FFT algorithm from Numerical Recipes in C.
>
> What is the chance that I will find a compiler that can generate
> a reasonable FPGA implementation of that algorithm, say in the
> next 5 years to give someone a chance?
>
> -- glen
>



Article: 43212
Subject: Re: Bidirectional DONE?
From: "Joze Dedic" <joze.dedic@email.si>
Date: Thu, 16 May 2002 17:21:30 +0200
Links: << >>  << T >>  << A >>
FPGA does not work until it is fully configured (i.e. until DONE is high) -
until then all the output drivers are off, and all FFs are held in
reset...This pin is used (probably only) because of (programmed) timing
sequence after DONE is high (enable outputs, release set or reset...)
have a nice day, jOc


"Stephanie McBader" <mcbader@neuricam.com> wrote in message
news:3CE3B080.CBAB2AEC@neuricam.com...
> Hi,
>
> Xilinx FPGA datasheets (both Virtex & Spartan) indicate that the DONE
> pin is bidirectional. Does that mean that the logic configured inside
> the FPGA will be able to read it?
>
> i.e., would a controller implemented in the FPGA be able to read the
> value of DONE & say, remains in reset until DONE is asserted?
>
> Thanks!
>
> Stephanie McBader
> Researcher/Design Engineer
> NeuriCam S.p.A
> Via S M Maddalena 12
> 38100 Trento TN, Italy
> Tel: +39-0461-260552
> Fax: +39-0461-260617
>
>



Article: 43213
Subject: Re: Bidirectional DONE?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 16 May 2002 08:41:33 -0700
Links: << >>  << T >>  << A >>
Stephanie,

Internally, when in chains of FPGAs, the DONE pin of the master waits to
see the DONE pin of the last slave go high (hence it is an input in that
mode).

Basically, no user logic can operate until DONE goes high, so I don't see
why you need this.  As soon as DONE goes high, all initial register
values, FF states, BRAM contents, etc are all present, and on the next
user supplied system logic clock, everything starts marching along.

Austin

Stephanie McBader wrote:

> Hi,
>
> Xilinx FPGA datasheets (both Virtex & Spartan) indicate that the DONE
> pin is bidirectional. Does that mean that the logic configured inside
> the FPGA will be able to read it?
>
> i.e., would a controller implemented in the FPGA be able to read the
> value of DONE & say, remains in reset until DONE is asserted?
>
> Thanks!
>
> Stephanie McBader
> Researcher/Design Engineer
> NeuriCam S.p.A
> Via S M Maddalena 12
> 38100 Trento TN, Italy
> Tel: +39-0461-260552
> Fax: +39-0461-260617


Article: 43214
Subject: Re: SPARTAN II - Master serial mode configuration problem
From: Thorsten Trenz <ng@trenz-electronic.de>
Date: Thu, 16 May 2002 17:48:18 +0200
Links: << >>  << T >>  << A >>
Hi,

> I am trying to configure XC2S200 (FG456) 5C in master serial mode (M(2:0)
> all 0) from PROM XC18V02 - but the problem is that configuration does not
> succeed every time.


have a look at the cclk. Try to terminate it with 100 Ohm - 150 Ohm.


Best regards
Thorsten Trenz



-- 
Dipl.-Ing. Thorsten Trenz, Trenz Electronic
Tel.: +49 (0) 5223 41652, Fax.: +49 (0) 5223 48945
Mailto:ng@trenz-electronic.de
http://www.trenz-electronic.de





Article: 43215
Subject: What properties has FPGA?
From: ziakjan@host.sk (Jan Ziak)
Date: 16 May 2002 08:50:13 -0700
Links: << >>  << T >>  << A >>
Hi. I would like to know what exact properties a programmable array
has. More precissely, I want to know whether it allows to represent
any algorithm, that is whether a programmable array includes:

1. causality (i.e. conditional execution in general)
2. stability (i.e. some sort of memory)

I was searching for this information in the internet but have found
nothing.

I would like to know whether such PA exists.

Thanks in advance.

Article: 43216
Subject: Re: Frequency synthesiser
From: John_H <johnhandwork@mail.com>
Date: Thu, 16 May 2002 15:57:00 GMT
Links: << >>  << T >>  << A >>
John_H wrote:

> I'll see if I can find my book on digital frequency synthesis for a reference

The book I bought in '96 proved very interesting at the time when I was doing some
DDS design.  I referred back to the text when I was doing Fractional-N investigations
though the treatment of Fractional-N wasn't as clean as I hoped.  Most of the
Fractional-N work I did was from a rare data sheet or two, some papers on Delta-Sigma
D/A converters, and a bunch of Mathcad analysis of spurs.

Digital Techniques in Frequency Synthesis
Bar-Giora Goldberg
McGraw-Hill 1996
ISBN 0-07-024166-X


Having thought more about your envisioned application, I've guessed you're trying to
get the VCXO (or VCO) to tune precisely by dithering between two DAC values since the
values of X and X+1 you mentioned would be too fast or too slow for a phase lock.
This is where the Delta-Sigma converters came in to my development.  Very high
resolution converters with excellent linearity can be realized with reasonable
frequencies (often below 50kHz) by using what some early papers referred to as a
"1-bit DAC" controlled by very fast dithering, the output of which is lowpassed.  By
using more than just an accumulator output which would provide strong beat
frequencies showing up as jitter in a synthesizer, the Delta-Sigma technique
supresses the error by adding digital filtering to explicitly remove the error in the
low frequency band.  While ther have been "multi-bit DACs" used in Delta-Sigma
converters, the linearity issues limited the results in the work I saw in the early
'90s.  The beauty of the frequency synthesizer is that the output of a phase
comparator is the rough equivalent of the DAC in a Delta-Sigma converter.

As long as you figure out where your spurs will be for the reference and output
frequency combination and do your filtering right, the analog phase comparator in a
Fractional-N synthesizer can produce exceptional results.  The increased signal
agility allowed by the technique comes at a small cost of a slightly increased phase
noise floor - still very good compared to the alternatives - in the frequencies near
and a bit above the PLL filter cutoff frequency.


Article: 43217
Subject: Re: PCI Board Project
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 16 May 2002 18:05:11 +0200
Links: << >>  << T >>  << A >>
"Mauricio Lange" <weirdo@bbs.frc.utn.edu.ar> schrieb im Newsbeitrag
news:2f938098.0205160624.1b86ef5a@posting.google.com...
> Thank you all, the information you gave is very valuable.
> The only reason I am dealing with the 4K line is economical (at least
> by now, I hope so...). The XS40 eval boards use the XC4010XL.

Its NOT more economical. Go to

www.nuhorizons.com

and compare the price of  Spartan-II againgst 4K (or Spartan(XL), you will
be scared!

--
MfG
Falk





Article: 43218
Subject: Articles on FPGA-based design validation / verification?
From: "Don Teeter" <spam.not.allowed@intel.com>
Date: Thu, 16 May 2002 09:59:43 -0700
Links: << >>  << T >>  << A >>
Validation of VLSI designs using FPGA-based hardware is pretty common.
Anyone know of a not-too-old article on the industry as a whole?  A web
search turns up a lot of companies that do this (Quickturn etc.), but I'd
prefer not to use any one company as my source.  I need a sense of the scale
of the industry, is it growing, how's it changing etc. from an objective
source.

This is not for internal use but for research of a personal nature.  Quick
replies appreciated.  Thanks!

--
Don Teeter
* Not speaking for Intel Corp. *



Article: 43219
Subject: Re: SPARTAN II - Master serial mode configuration problem
From: "jakab tanko" <jtanko@ics-ltd.com>
Date: Thu, 16 May 2002 15:56:06 -0400
Links: << >>  << T >>  << A >>
I had a similar problem with a Spartan2 (xc2s150), this is
what I did to fix the problem:
  - pull up "DONE" to 3.3V with ~6.8K resistor
  - replace 4.7K pull up resistor on "INIT" with 10K res.
  - connect a 10uF Cap between "INIT" and GND

The problem was that the fpga powered up and asserted INIT
before the PROM finished it's startup sequence.
( a pullup on DONE was also missing)

jakab

C.W. THomas <cwthomas@bittware.com> wrote in message
news:ue7ciq320ddd13@corp.supernews.com...
>
>
> I'd try messing with the pullup/pulldown settings for TDI and TCLK and
maybe
> TMS.
>
> Good Luck;
>
>
>
> "Joze Dedic" <joze.dedic@email.si> wrote in message
> news:ac0163$dva$1@planja.arnes.si...
> > I am trying to configure XC2S200 (FG456) 5C in master serial mode
(M(2:0)
> > all 0) from PROM XC18V02 - but the problem is that configuration does
not
> > succeed every time.
> > FPGA DONE signal stays low and CCLK is running at 5 MHz whenever the
cofig
> > fails - but nPROGRAM and nINIT signals are high. I have even monitored
the
> > bitstream (DIN) of succeded and failed config - it started in the same
> way.
> > FPGA is located on PCI evaluation board (6 layers - one for 3.3 and one
> for
> > GND). On this EVB fits platform with SA1110. Thing is that config
succeeds
> > every time whenever I hold SA1110 in reset. This indicates on some noisy
> > enviroment problem. I think...
> > I have monitored core supply (2.5) and it is clean and stabile. There
are
> 8x
> > 10n, 8x 100n, 2x 1u, and 3x 10u F capacitators around FPGA.
> >
> > Are there any config setings that I should change - or it is just lack
of
> > blocking C and poor supply condition.
> >
> > I would like to mention that one board (luckily the first one) works
fine.
> I
> > have no ideas more. Thanks for any advice.
> >
> > jOc
> >
> >
>
>



Article: 43220
Subject: Need Help on FPGA and Spiking Neurons
From: Traveler <Traveler@nospam.com>
Date: Thu, 16 May 2002 20:30:30 GMT
Links: << >>  << T >>  << A >>
Hi,

I am researching the suitability of FPGA technology for the real-time
simulation of spiking or pulsed neurons in a feedforward network. The
system I envision will have up to 200,000 neurons organized in several
specialized layers. At least one of the layers will use massive
recurrent feedback.

The system must make it easy to attach an indefinite number of
synaptic (input and output) connections to a neuron, and to disconnect
them when necessary. Some of my neurons have as little as two inputs
while others may have hundreds of inputs. The efficacy of the
connections must be adjustable in real time. Good timing capability is
essential although not stringent. I need to resolve signal arrival
times to within 1 millisecond. I need to be able to add precise signal
delays to specific inputs. Thanks in advance for any relevant info.

Nemesis

Temporal Intelligence:
http://home1.gte.net/res02khr/AI/Temporal_Intelligence.htm

Article: 43221
(removed)


Article: 43222
Subject: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 16 May 2002 18:26:50 -0400
Links: << >>  << T >>  << A >>
Austin,
    My appolgies for what, as I re-read what I wrote last night, appears to be
somewhat rude at best.  I will try to find out what might be readily available
for IBIS simulation on campus.  You most likely are right, there probably is
something available.
    By the way, has Xilinx considered providing PSPICE models for the output
devices in the FPGA?  (Perhaps I am just behind the times, but PSPICE is simple
and readily available as a demo version.)

Thanks for the answer.

Austin Lesea wrote:

> Theron,
>
> I won't then.
>
> Austin
>
> PS:  regular customers who need a "what if" can open a case on the hotline,
> and request an IBIS simulation be run for just such a case.  University
> customers are supported through a different system and program.  I would
> hope that the university sponsering this would be at the cutting edge, and
> have IBIS simulation tools available.  I will check on that.  I have run
> the simulation, and the overshoot and undershoot is terrible, and the rise
> and fall times are 1.4 ns for the fast corner, and 3.7 ns for the slow
> corner.
>
> Email me directly if you wish to receive the .jpg of the simulation.
>
> "Theron Hicks (Terry)" wrote:
>
> > Hi,
> >     I am considering using a Spartan2E to generate a clock signal
> > (amongst other things).  The clock will probably be driven by a slow
> > LVTTL signal with a 12 mA drive current.  I am trying to decide whether
> > to terminate this output and if so how to do so (source vs load
> > termination, etc.)  To do so, I need to know what the rise and fall
> > times of the output signal are.  Please do not tell me to use IBIS.  I
> > am quite competent with SPICE and PSPICE but I have no experience with
> > IBIS models and no availability to the software.  For this simple
> > calculation I really don't need to use such tools anyway.  FYI the
> > transmission line will be less than 0.3 meters
> > (> 1 foot).  Load is one Spartan2E LVTTL input.  Frequency is 100MHz.
> >     Alternatively, I could use the differential LVPECL capacity of the
> > Spartan2E, but it appears to be overkill and would add an additional
> > connector pair to the system.
> >
> > Theron Hicks


Article: 43223
Subject: Timing constraints on internal signals
From: "Douglas Miller" <dougandsheilamiller@worldnet.att.net>
Date: Fri, 17 May 2002 00:09:16 GMT
Links: << >>  << T >>  << A >>
I'm a newby trying to use the Xilinx ISE constraints editor to put timing
constraints on  internal signals (i.e. signals that don't go to output
pads).  The internal signals consist of a bus being reclocked.  Any guidance
on how this is done?  (For discussion purposes, assume the clks are clk1 and
clk2 and the signal busses are bus1 and bus2)

Doug



Article: 43224
Subject: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 16 May 2002 17:13:08 -0700
Links: << >>  << T >>  << A >>
Theron,

Unfortunately, wew can not encrypt the technology files with psice, so we only
support hspice under NDA for IO simulations (and only then under some duress as the
there is no gaurantee of security in this method of encryption).

One can appreciate that all of the device models are proprietary to our foundries,
and to us, and their disclosure is absolutely prohibited.

Austin


"Theron Hicks (Terry)" wrote:

> Austin,
>     My appolgies for what, as I re-read what I wrote last night, appears to be
> somewhat rude at best.  I will try to find out what might be readily available
> for IBIS simulation on campus.  You most likely are right, there probably is
> something available.
>     By the way, has Xilinx considered providing PSPICE models for the output
> devices in the FPGA?  (Perhaps I am just behind the times, but PSPICE is simple
> and readily available as a demo version.)
>
> Thanks for the answer.
>
> Austin Lesea wrote:
>
> > Theron,
> >
> > I won't then.
> >
> > Austin
> >
> > PS:  regular customers who need a "what if" can open a case on the hotline,
> > and request an IBIS simulation be run for just such a case.  University
> > customers are supported through a different system and program.  I would
> > hope that the university sponsering this would be at the cutting edge, and
> > have IBIS simulation tools available.  I will check on that.  I have run
> > the simulation, and the overshoot and undershoot is terrible, and the rise
> > and fall times are 1.4 ns for the fast corner, and 3.7 ns for the slow
> > corner.
> >
> > Email me directly if you wish to receive the .jpg of the simulation.
> >
> > "Theron Hicks (Terry)" wrote:
> >
> > > Hi,
> > >     I am considering using a Spartan2E to generate a clock signal
> > > (amongst other things).  The clock will probably be driven by a slow
> > > LVTTL signal with a 12 mA drive current.  I am trying to decide whether
> > > to terminate this output and if so how to do so (source vs load
> > > termination, etc.)  To do so, I need to know what the rise and fall
> > > times of the output signal are.  Please do not tell me to use IBIS.  I
> > > am quite competent with SPICE and PSPICE but I have no experience with
> > > IBIS models and no availability to the software.  For this simple
> > > calculation I really don't need to use such tools anyway.  FYI the
> > > transmission line will be less than 0.3 meters
> > > (> 1 foot).  Load is one Spartan2E LVTTL input.  Frequency is 100MHz.
> > >     Alternatively, I could use the differential LVPECL capacity of the
> > > Spartan2E, but it appears to be overkill and would add an additional
> > > connector pair to the system.
> > >
> > > Theron Hicks




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