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Messages from 43225

Article: 43225
Subject: Re: 50 mA sink
From: kayrock66@yahoo.com (Jay)
Date: 16 May 2002 17:46:31 -0700
Links: << >>  << T >>  << A >>
The other option to paralleling outputs is to just use an external
transistor and save your FPGA the strain.  If you're a digital guy
don't be afraid, its really a simple configuration.

emanuel stiebler <emu@ecubics.com> wrote in message news:<3CE05E45.72E906B8@ecubics.com>...
> Hi all,
> anybody out here knows a CPLD/FPGA which can sink at least 50 mA
> on a 5V TTL compatible output ?
> 
> cheers & thanks

Article: 43226
Subject: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 16 May 2002 21:47:25 -0400
Links: << >>  << T >>  << A >>
I suspected that might be the reason.  Oh well...  Thanks.

Austin Lesea wrote:

> Theron,
>
> Unfortunately, wew can not encrypt the technology files with psice, so we only
> support hspice under NDA for IO simulations (and only then under some duress as the
> there is no gaurantee of security in this method of encryption).
>
> One can appreciate that all of the device models are proprietary to our foundries,
> and to us, and their disclosure is absolutely prohibited.
>
> Austin
>
> "Theron Hicks (Terry)" wrote:
>
> > Austin,
> >     My appolgies for what, as I re-read what I wrote last night, appears to be
> > somewhat rude at best.  I will try to find out what might be readily available
> > for IBIS simulation on campus.  You most likely are right, there probably is
> > something available.
> >     By the way, has Xilinx considered providing PSPICE models for the output
> > devices in the FPGA?  (Perhaps I am just behind the times, but PSPICE is simple
> > and readily available as a demo version.)
> >
> > Thanks for the answer.
> >
> > Austin Lesea wrote:
> >
> > > Theron,
> > >
> > > I won't then.
> > >
> > > Austin
> > >
> > > PS:  regular customers who need a "what if" can open a case on the hotline,
> > > and request an IBIS simulation be run for just such a case.  University
> > > customers are supported through a different system and program.  I would
> > > hope that the university sponsering this would be at the cutting edge, and
> > > have IBIS simulation tools available.  I will check on that.  I have run
> > > the simulation, and the overshoot and undershoot is terrible, and the rise
> > > and fall times are 1.4 ns for the fast corner, and 3.7 ns for the slow
> > > corner.
> > >
> > > Email me directly if you wish to receive the .jpg of the simulation.
> > >
> > > "Theron Hicks (Terry)" wrote:
> > >
> > > > Hi,
> > > >     I am considering using a Spartan2E to generate a clock signal
> > > > (amongst other things).  The clock will probably be driven by a slow
> > > > LVTTL signal with a 12 mA drive current.  I am trying to decide whether
> > > > to terminate this output and if so how to do so (source vs load
> > > > termination, etc.)  To do so, I need to know what the rise and fall
> > > > times of the output signal are.  Please do not tell me to use IBIS.  I
> > > > am quite competent with SPICE and PSPICE but I have no experience with
> > > > IBIS models and no availability to the software.  For this simple
> > > > calculation I really don't need to use such tools anyway.  FYI the
> > > > transmission line will be less than 0.3 meters
> > > > (> 1 foot).  Load is one Spartan2E LVTTL input.  Frequency is 100MHz.
> > > >     Alternatively, I could use the differential LVPECL capacity of the
> > > > Spartan2E, but it appears to be overkill and would add an additional
> > > > connector pair to the system.
> > > >
> > > > Theron Hicks


Article: 43227
Subject: Re: Need Help on FPGA and Spiking Neurons
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 16 May 2002 22:45:53 -0400
Links: << >>  << T >>  << A >>
Traveler wrote:
> 
> Hi,
> 
> I am researching the suitability of FPGA technology for the real-time
> simulation of spiking or pulsed neurons in a feedforward network. The
> system I envision will have up to 200,000 neurons organized in several
> specialized layers. At least one of the layers will use massive
> recurrent feedback.
> 
> The system must make it easy to attach an indefinite number of
> synaptic (input and output) connections to a neuron, and to disconnect
> them when necessary. Some of my neurons have as little as two inputs
> while others may have hundreds of inputs. The efficacy of the
> connections must be adjustable in real time. Good timing capability is
> essential although not stringent. I need to resolve signal arrival
> times to within 1 millisecond. I need to be able to add precise signal
> delays to specific inputs. Thanks in advance for any relevant info.
> 
> Nemesis
> 
> Temporal Intelligence:
> http://home1.gte.net/res02khr/AI/Temporal_Intelligence.htm

FPGAs may be quite useful in your research efforts, but you have not
defined the requirements in terms that a logic designer can use.  To
evaluate the suitability of FPGAs for your research, your problem
statement needs to use logical constructs like gates, counters, storage
elements, etc.  To say that you need to implement neurons and synapses
makes it hard to compare to the flip flops, gates and memory contained
in an FPGA.  

But I think the key to your problem statement is your signal arrival
timing of 1 milliSecond.  This is far slower than what can be done in
logic (by about 10,000 to 100,000 times) and so you will most likely
find that software will operate fast enough for your needs.  Simulating
200,000 neurons may exceed the capability of a single CPU, but a multi
CPU system (say up to 10 CPUs or DSPs) will be much easier to design and
program than an FPGA if you are not a logic designer.  

Although there is something to be said for implementing the problem in
an FPGA.  An FPGA running at 10 to 100 MHz can simulate from 10,000 to
100,000 neurons in 1 mS in each instance of the neuron.  So obviously
developing a large array of neurons in a single FPGA will not be a
problem.  If the inter neuron connections need to be selectable, then
you need to design in a level of programmable interconnect that may make
the problem a bit more complex.  

The more I think about it, the more this sounds like a design of a
cellular automata.  

But the trick to it all is to define what you need in terms of
arithmetic or logic functions.  Can you do that, or will you need help? 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 43228
Subject: Circuit design for Altera ACEX development board
From: "Frank" <fjm_2@lycos.com>
Date: Thu, 16 May 2002 19:48:24 -0700
Links: << >>  << T >>  << A >>
Hello,

I am designing a very bare-bones development board using Altera ACEX fpga's
(EP1K10, EP1K30, and EP1K50) and EPC2 configuration memory.  There will
be a couple of push-buttons and LED's.  I will use a 4-wire JTAG interface
to
program the memory and/or fpga.  I am hoping to find a schematic design to
compare with my work.  Before sending the PCB design out, I'd like to be
sure
that I've not overlooked any needed connections.  Looking at another design
may
also alert me to features that could enhance the functionality of the board
without
materially increasing its complexity.

I would appreciate links to such designs.  I am NOT interested in designs
whose
developers would consider dissemination of such information as theft of
intellectual
property.

Thank You and Best Regards,

Frank Madison



Article: 43229
Subject: Re: Architecture for high-level reconfigurable computing
From: Keith R. Williams <krw@attglobal.net>
Date: Thu, 16 May 2002 23:02:46 -0400
Links: << >>  << T >>  << A >>
In article <3CE32E1F.62854C2B@earthlink.net>, 
palfke@earthlink.net says...
> 
> 
> "Keith R. Williams" wrote:
> 
> > Obviously you have your (official Xilinx) bias.  It's been stated
> > with no uncertain terms.
> >
> > <snip>
> 
> > I really like Xilinx products, the company, the whole idea, but I
> > don't understand the refusal to understand the other side's
> > problems.  I've been a lurker here for three years, occasionally
> > adding something when I can.  When it comes to some serious
> > issues with the "Xilinx way" I see nothing but defense.  Yes,
> > some of us have been well roasted by things you consider
> > "trivial".
> >
> > ----
> >   Keith
> 
> Keith, both Austin and I make no secret about the fact that we are loyal
> Xilinx employees. As such we will not attack our company in a public forum.

I have no problem with that.  I appreciate what you folks are 
doing on this forum.

> But we are also engineers, so we will represent Xilinx in a rational way.
> Non-volatile memory in a CMOS process is not a trivial issue, and Xilinx
> developers have struggled with this issue for years. Austin and I have given
> inputs about the desirability, and about the many attractive possibilities
> that would come with such a solution.

Fine.  My point is that this issue has been covered for ten 
years.  I know nothing (ok, small lie) about your foundry 
efforts, but I can assure you that reliable fuses have been 
around for years.  My example of the mainframe crypto stuff 
(almost ten years ago) was an attempt to show that what the 
customers are asking for is bit only possible, but reliable.  
Sheesh! All D/SRAM manufacturers have some sort of fuse 
technology for redundancy.  This isn't rocket-surgery anymore.

> Our processing folks ( yes, we have dozens of them, even though we are a
> fabless company) listen to these inputs, and take them into consideration,
> together with many other requirements. Like the need for process migration to
> ever smaller geometries, compatibility with different fabs, speed, cost,
> reliability, etc.

"Cost" is the only part of this I understand.  That "cost" is not 
in the process, but rather "we've caught the car, now what do we 
do with it?".
  
> Weighted against all these sometimes conflicting choices and trade-offs,
> non-volatile storage has not made it. Other things were more important. And I
> can live with those priorities.

I can live within your priorities as well, but don't tell us the 
technology isn't available.  It is!  The only question is 
business.  If no one wants to *pay* for security, then it's not 
to be.  Certainly there are issues that are specific to FPGAs, 
but they are not a problem with your desired technology.

> My personal opinion is that it might have made it, if the fate our company
> were depending on it, but that is clearly not the case. Other things are far
> more important.

That, is the bottom line.  If you (collective) believe the fate 
of Xilinx depends on not offering some real security, I have no 
problem with the decision.  Please don't tell us it's a 
technology problem.  I've seen what has been proposed, in 
*spades* (every chip with a unique public/private 2048bit key).  
...in a process far older than what you're currently using.  
Reliability?  Please! 

> So, for the time being, we are without such a capability. It still is very
> much on our wish list, but we concede that there are other priorities. That's
> why Austin and I defend the present situation, and explain the realistic user
> options. Publicly, we are applications engineers who understand how to build
> systems using our existing devices and technology. Inside Xilinx, we may rant
> and rave and fight and disagree about dfferent options, but outside we try to
> help you use our parts in the best way. Pretty obvious, isn't it.

I have no real problem with your business decision.  Your 
argument about the technology not being there is, in my opinion, 
bogus.  It's been there for *years* and it's cheap.  

Again, even DRAM manufacturers use it.  *THAT'S* cheap.  I 
dispute your (Austin included) claim that fuses are 
strange/unreliable/dangerous.  Yes, there are issues with them. 
...as there are with everything else about this business. 

> End of soapbox.

I'd like to know if people *really* want security (as in paying 
for it). Since I worked in secure/crypto hardware for some years 
it's kinda a side interest for me. The technology is not only 
available, but cheap.  The management of any real security is the 
real problem.

----
  Keith

Article: 43230
Subject: Re: extend jtag downloadcable
From: "Leo Havm°ller" <leh@-nospam-rtx.dk>
Date: Fri, 17 May 2002 06:21:27 +0200
Links: << >>  << T >>  << A >>
"Wim Peeters" <peeters_wim@hotmail.com> wrote in message
news:8f00e675.0205160608.771e20f9@posting.google.com...
> Hello,
>
> HAs anyone ever extended a jtag download cable up to 1-2 metres. What
> I want to archieve is to doewload at a reasonable speed but without
> using any buffers in the cable. I was thinking of using a "better"
> cable than the standard flatcable.
> My interface is a JTAG Technologies BV USB adapter JT3710. My device
> is an Altera 3128.
>
> What i have now is a clabel of approx. 1 metre but I have to adjes the
> download speed from 25kHz to 5KHz. My target is to go back to 25kHz by
> using a better quality cable.
>
> Thanks in advance for your advise!

This is not for an FPGA, but it discusses some omf the problems with long
JTAG cables:
http://www.arm.com/support.nsf/html/multi_ice_faq!OpenDocument&ExpandSection
=12#_Section12

Leo Havm°ller.



Article: 43231
Subject: Spartan2 on a Compact Flash card
From: jeff@mock.com (Jeff Mock)
Date: 16 May 2002 21:44:53 -0700
Links: << >>  << T >>  << A >>
I'm looking at doing a contract project to design a compact flash
card.  I would like to use a Spartan2 on the board, but I'm 
concerned about the I(ccpo) parameter in Spartan2.  The Spartan2
needs 500mA for a couple mS during power-on until it sorts out the
random power-on bus contention in the chip.

The Compact Flash spec says that a card shouldn't consume more 
than 75mA.

Xilinx has nice app notes on spartan power supply requirements at
power-up:   http://www.xilinx.com/xapp/xapp450.pdf  and
http://www.xilinx.com/xapp/xapp451.pdf

I generally believe the Xilinx story, but I'm hesitatant to use
the part in an environment where I don't have control over the 
power supply.  It would be horrible to plug the CF card into a 
PDA and have the power supply fold-back on insertion and screw-up
everything.

Does anyone have any experience with SpartanII in a Compact Flash
sort of power environment?

jeff

Article: 43232
Subject: PCI target with FPGA question
From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange)
Date: 16 May 2002 21:53:12 -0700
Links: << >>  << T >>  << A >>
Hello again. 
This is my second post to this group, I am really grateful for the
answers to my first posting.
Well, as some know already, I need to design a PCI add-in board, with
the minimum target capabilities. Things are getting in place, but
there is something that is puzzling me.
The FPGAs loose their configuration when powered off, right? 
Ok, then, I should keep my add-in board powered on, that is to say,
with some backup supply, to have the FPGA configured BEFORE the PC
starts its card registering routines (via BIOS).
Maybe this is not necessary, and I can get the FPGA configured using a
PROM, fast enough to allow the PCI BIOS to register my card.

Would someone give me a hint about this?

Thank you very much.

Mauricio Lange
mlange@ieee.org

Article: 43233
Subject: Accessing TAP registers from within the FPGA (VirtexII)
From: Patrik Eriksson <patrik.eriksson@netinsight.net>
Date: Fri, 17 May 2002 05:02:17 GMT
Links: << >>  << T >>  << A >>
[VirtexII]

In the JTAG TAP there are some user defined rgisters such as the 
USERCODE rgister. The value of this register will be assigned by bitgen. 
The register can be read back through the JTAG port but is it possible 
to access this register from logic within the FPGA?


Regards,
Patrik

-- 
Patrik Eriksson              |  patrik.eriksson@netinsight.net
Net Insight AB               |  phone:  +46 8 685 04 89
Vństberga AllÚ 9             |  fax:    +46 8 685 04 20
SE-126 30 STOCKHOLM, Sweden  |  http://www.netinsight.net


Article: 43234
Subject: HardPath
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Fri, 17 May 2002 05:03:11 GMT
Links: << >>  << T >>  << A >>

Xilinx has a interesting idea with "EasyPath", in that they only test
the parts of a Virtex-2 that are really used in your design, and save
you some money in the process.

http://www.xilinx.com/prs_rls/silicon_vir/0248easypath.html

Of course, this isn't for everyone.  Some of the designs may reprogram
devices to new designs frequently.  See:

http://groups.google.com/groups?hl=en&lr=&selm 010731.103308.1239036029.24248%40polybus.com


I would like to suggest "HardPath", in that Xilinx produces a more
completely tested version of their parts, much as the above thread
discussed.  As you may or may not know, Xilinx's parts are given a
reasonable test, not a complete test.  This test is good enough for most
users, however it may not be good enough for users that frequently
reprogram devices to different designs, or where the cost of failing to
correctly reprogram a device to a new design would be substantial.  So
will Xilinx sell a version of their part with a more complete test?

I know that tester time is expensive, and these parts would need to be
priced higher, and that's ok.  I know that this doesn't guarantee that
there still may be a defect that has been missed that will cause a
device to fail work correctly with a new design.  After all, a complete
test would take longer than practical.  I'm not looking for perfection. 
I'd just like better odds than what I see now.

Anyone else interested?


-- 
Phil Hays

Article: 43235
Subject: LOCKED signal of a DLL in a Virtex device questions
From: "jfh" <jfhasson@club-internet.fr>
Date: Fri, 17 May 2002 08:07:04 +0200
Links: << >>  << T >>  << A >>
Hi,

I am wondering if the LOCKED signal of a DLL is synchronous to something ?
Moreover are the clock outputs of a DLL correct as soon as the LOCKED signal
is high or is there a little more time to wait before actually using the
clock outputs ?
Thanks.

J.F.



Article: 43236
Subject: interfacing dspand fpga
From: anjanr@yahoo.com (Anjan)
Date: 16 May 2002 23:55:27 -0700
Links: << >>  << T >>  << A >>
Hi
The design architecture consists of a DSP, fpga and other devices
which are memory mapped to the DSP. Now the DSP and fpga communicate
over bidirectional(inout) bus and use control signals
"write(w)","read(r)" and "chip select(cs)" from DSP. I am using
Webpack 4.2 from Xilinix and a Virtex device. I am facing problems
when the DSP writes to the fpga. The simulation tool(modelsim 5.5e)
shows 'X' when the DSP is writing. Please help. Also tell me if it
only a simulation problem. The communication is async

read:process(read,cs)
begin
if(cs='1' then)
data_bus<="Z";
elsif(read='0' and read'event) then
data_bus="some data";
end if;
end process;
write:process(write,cs)
begin

if(write'event and write='0') then
if(cs='0') then
something=data;
end if;
end if;
end process;
Anjan

Article: 43237
Subject: Re: PCI target with FPGA question
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Fri, 17 May 2002 08:35:05 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------28C374112F6A28AE5E40ED56
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi Maurico,

The PCI spec now includes a minimum time after which the PCI agents should
be active on the bus, and this time is 100ms (apparently Xilinx requested
this info to be added to the spec). This is definitely achievable if you
configure the FPGA in a parallel mode, i.e. 8 bits at a time.

Regards,
Stephan

Mauricio Lange wrote:

> Hello again.
> This is my second post to this group, I am really grateful for the
> answers to my first posting.
> Well, as some know already, I need to design a PCI add-in board, with
> the minimum target capabilities. Things are getting in place, but
> there is something that is puzzling me.
> The FPGAs loose their configuration when powered off, right?
> Ok, then, I should keep my add-in board powered on, that is to say,
> with some backup supply, to have the FPGA configured BEFORE the PC
> starts its card registering routines (via BIOS).
> Maybe this is not necessary, and I can get the FPGA configured using a
> PROM, fast enough to allow the PCI BIOS to register my card.
>
> Would someone give me a hint about this?
>
> Thank you very much.
>
> Mauricio Lange
> mlange@ieee.org



Article: 43238
Subject: Re: PCI Board Project
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 17 May 2002 08:04:23 -0000
Links: << >>  << T >>  << A >>
>Other question:
>To get the FGPA configured, I will need to wire in the board a PROM
>with the bitstream, right?

You should also think about how you are going to update that PROM.
Turning power off and taking out the card so you can remove the chip
and put it into a PROM blaster gets annoying after the first few
times.

So you want something like a JTAG connection to program the PROM.


> The FPGAs loose their configuration when powered off, right? 
> Ok, then, I should keep my add-in board powered on, that is to say,
> with some backup supply, to have the FPGA configured BEFORE the PC
> starts its card registering routines (via BIOS).
> Maybe this is not necessary, and I can get the FPGA configured using a
> PROM, fast enough to allow the PCI BIOS to register my card.

I think if you read the right place in the PCI spec you will find
that they left plenty of time to cover this case.  [Most PCs spend
a lot of time checking memory before they look for PCI devices.]

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 43239
Subject: Re: PCI Board Project
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Fri, 17 May 2002 09:13:03 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------9DC574E8FC3A6BF2C066F124
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Yes, according to the new spec. there should be a time of 100ms provided before
your device actually needs to be active on the bus.

Hal Murray wrote:

> >Other question:
> >To get the FGPA configured, I will need to wire in the board a PROM
> >with the bitstream, right?
>
> You should also think about how you are going to update that PROM.
> Turning power off and taking out the card so you can remove the chip
> and put it into a PROM blaster gets annoying after the first few
> times.
>
> So you want something like a JTAG connection to program the PROM.
>
> > The FPGAs loose their configuration when powered off, right?
> > Ok, then, I should keep my add-in board powered on, that is to say,
> > with some backup supply, to have the FPGA configured BEFORE the PC
> > starts its card registering routines (via BIOS).
> > Maybe this is not necessary, and I can get the FPGA configured using a
> > PROM, fast enough to allow the PCI BIOS to register my card.
>
> I think if you read the right place in the PCI spec you will find
> that they left plenty of time to cover this case.  [Most PCs spend
> a lot of time checking memory before they look for PCI devices.]
>
> --
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.



Article: 43240
Subject: Re: Reading GSR signal of Spartan-II
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Fri, 17 May 2002 09:11:24 GMT
Links: << >>  << T >>  << A >>
On Fri, 17 May 2002 09:17:32 +0200, Stephanie McBader
<mcbader@neuricam.com> wrote:

>OK, that I understand.. But what I need is to *read* the GSR net - how can I do
>that?

What do you want to read it for?

You said earlier:
>> >> The
>> >> problem is that we have a system in which a controller must be
>> >> implemented inside the FPGA but which does not provide any form of reset
>> >> signal as an input to the FPGA logic.

Do you mean that your external logic does not provide a signal to
reset the controller?
Or do you mean that your current controller design does not have an
asynchronous reset input?

Neither requires "reading" the GSR net.

What are you *really* trying to do?

Regards,
Allan.


>Still looking out for help :)
>
>- Cross posted to comp.arch.fpga
>
>Best Regards,
>
>Stephanie McBader
>Researcher/Design Engineer
>NeuriCam S.p.A
>Via S M Maddalena 12
>38100 Trento TN, Italy
>Tel: +39-0461-260552
>Fax: +39-0461-260617
>
>
>Allan Herriman wrote:
>
>> [snip]
>
>> You can drive GSR (to reset or set every flip flop in the chip) by
>> asserting the GSR input on the startup block at any time.
>>
>
>I earlier wrote:
>
>> >> Hi there,
>> >>
>> >> Apologies if this has come up before - I have searched both newsgroups
>> >> and the Xilinx support website but I have not found *exactly* what I'm
>> >> looking for.
>> >>
>> >> Is it possible to *read* the GSR signal of a Spartan-II FPGA? The
>> >> problem is that we have a system in which a controller must be
>> >> implemented inside the FPGA but which does not provide any form of reset
>> >> signal as an input to the FPGA logic. I have had a look at the
>> >> Spartan-II datasheet and on page 19 there is a waveform describing the
>> >> start-up sequence of the FPGA after programming. The GSR is evidently
>> >> active high and is negated shortly after DONE goes high. I would like to
>> >> be able to use the GSR value as an asynchronous reset input to the logic
>> >> implemented in the FPGA.. How do I do this?
>> >>
>> >> I have seen numerous answers pointing to the STARTUP block, but this
>> >> only has the GSR signal as an *input*! I need to read it somehow and I
>> >> do not know which source to use..
>> >>
>> >> Oh, we're using VHDL by the way (just thought I'd mention it even though
>> >> this *is* comp.lang.vhdl)
>> >>
>> >> Your help would be much appreciated.
>> >>
>> >> Regards,
>> >>
>> >> Stephanie McBader
>
>
>


Article: 43241
Subject: Re: Spartan2 on a Compact Flash card
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Fri, 17 May 2002 11:27:00 +0200
Links: << >>  << T >>  << A >>

Maybe think about using a big CoolRunner or 2 big Coolrunners in BGA 
package (pcb density will stay < a spartanII + a prom)!
You will save Ah.

Laurent Gauch
http://www.amontec.com


Jeff Mock wrote:

> I'm looking at doing a contract project to design a compact flash
> card.  I would like to use a Spartan2 on the board, but I'm 
> concerned about the I(ccpo) parameter in Spartan2.  The Spartan2
> needs 500mA for a couple mS during power-on until it sorts out the
> random power-on bus contention in the chip.
> 
> The Compact Flash spec says that a card shouldn't consume more 
> than 75mA.
> 
> Xilinx has nice app notes on spartan power supply requirements at
> power-up:   http://www.xilinx.com/xapp/xapp450.pdf  and
> http://www.xilinx.com/xapp/xapp451.pdf
> 
> I generally believe the Xilinx story, but I'm hesitatant to use
> the part in an environment where I don't have control over the 
> power supply.  It would be horrible to plug the CF card into a 
> PDA and have the power supply fold-back on insertion and screw-up
> everything.
> 
> Does anyone have any experience with SpartanII in a Compact Flash
> sort of power environment?
> 
> jeff
> 


Article: 43242
Subject: Problem with Xilinx ISE 4.2i map
From: Roman MORAWEK<Roman.MORAWEK@frequentis.com>
Date: Fri, 17 May 2002 09:31:12 GMT
Links: << >>  << T >>  << A >>
In my design I previously used the Xilinx ISE 2.1i tools and everything worked without a problem.

Changing to ISE 4.2i I get the following error using map:

Release 4.2.01i - Map E.36
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Reading NGD file "if_asic.ngd"...
Using target part "4020xlabg256-07".
MAP xc4000xla directives:
   Covermode = "area".
   Pack Unrelated Logic into CLBs targeting 100% of CLB resources.
Processing logical timing constraints...
ERROR:OldMap:661 - FDP symbol
   "pm_slave_unit/pm_bscan_slave/tap_dr_shift_cnt_reg<0>" (output
   signal=pm_slave_unit/pm_bscan_slave/tap_dr_shift_cnt<2>) - The attribute RLOC
   has been placed on the wrong type of symbol.  Please consult the "Attributes,
   Constraints, and Carry Logic" section of the Libraries Guide for more
   information on legal parameters.
... 5 more times for the other elements of the tap_dr_shift_cnt array...
ERROR:OldMap:630 - Problems were found processing RPMs in the design.
Errors found in users design.  Output files not written.

Design Summary
--------------
Number of errors   :   6
Number of warnings :   1


pm_slave_unit/pm_bscan_slave/tap_dr_shift_cnt is a signal array of type integer with imo no special vhdl code associated.

I used Synopsys FPGA Express Version: 2001.08-FE3.6, Build: 3.6.0.6613 and NgdBuild - Release 4.2.01i - edif2ngd E.36.

The "Attributes, Constraints, and Carry Logic" section of the Libraries Guide brought no useful information for me.

What causes this error?
Where should I start to fix this problem?

thanks,
Roman Morawek


Article: 43243
Subject: Re: Frequency synthesiser
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 17 May 2002 09:34:41 -0000
Links: << >>  << T >>  << A >>
> Search for Fractional-N Synthesizers, and maybe Rate Multipliers, which
> make good filter-able DACs, so are suited to your 'dithering' scheme.

Thanks.  I found a few that will keep me busy for a while.


> Are you wanting to modulate the DDS and you're unhappy with the current
> implementation?  A DDS is designed to provide sinusoidal values to the DAC.  The
> DAC is lowpassed to obtain a clean sine with exquisite time resolution.  What are
> you trying to do with your dithering?

DDS is the wrong word/concept.  Dithering is closer.

I was thinking of clocks for digital logic rather than sine waves.

Is there a good glossary describing clock generation schemes?


> The book I bought in '96 proved very interesting at the time when
> I was doing some DDS design.

> Digital Techniques in Frequency Synthesis
> Bar-Giora Goldberg
> McGraw-Hill 1996

Thanks.  How does that compare to a modern general DSP type book?

> Most of the Fractional-N work I did was from a rare data sheet or
> two, some papers on Delta-Sigma D/A converters, and a bunch of Mathcad
> analysis of spurs.

Ah..  Delta-Sigma.  Another one of those wonderful ideas that
I can follow when somebody explains it to me but it never sinks
in deep enough for me to explain it to somebody else.  One of these
days...



I think the main problem with my question is that I don't know
enough about what I'm looking for to ask a good question.  Partly
I was hoping for some general/overview answers like I got.  Thanks.

[I've been lucky enough to work with several smart people who
could read between the lines on my crazy questions and explain
to me what the right question was and then answer it.]

One application I had in mind was something like a clock that
could be used for keeping time on computers.  Software can
compute the actual frequency of the local "reference" clock
if there is a better reference clock out there on the net (and
NIST, USNO  and many GPS clocks are on the net).  It just takes
a while.  Given that info it should be reasonable to make a
10,000,000.000 Hz clock from a reference that's (say) 9,999,993.638 Hz.

Of course, the timekeeping can be done in software too, probably
cheaper.  But I'll probably learn something by trying to do it
in hardware, and FPGAs seem good at that type of thing.

For more than you ever wanted to know about computer timekeeping,
see www.ntp.org and/or comp.protocols.time.ntp

For timekeeping, the phase noise isn't a problem as long as the
long term answer is accurate.  But part of me wants to clean that
up too, so then the question is how to do it and how clean can
you get.  That's where the VXCO came from.

Going in the other direction, you can get a 1 pulse-per-second
signal out of many GPS receivers.  That and a stable (but not
accurate) local crystal could be used to make an accurate reference
clock, and for lab use, you might want that to be clean.


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 43244
Subject: Re: What properties has FPGA?
From: ziakjan@host.sk (Jan Ziak)
Date: 17 May 2002 02:35:06 -0700
Links: << >>  << T >>  << A >>
The thing that I am interested in is precisely this one: can we
reconfigure PLA so that is can contain 10 bits of memory in one case
and 123 bits of memory in some other case? Can we create memory? Am I
free to create any algorithm? If yes then I would like to know what
model of PLA is capable of this. If not then I would like to know what
is the problem, why it cant be done.

I will reformulate the question one more: can we freely make tradeoffs
between the size of memory and spatial complexity of an algorithm? So
can we create memory and also any interconnection pattern between the
"logic gates"? The question is whether the number of memories and
logic gates is fixed in current implemetations or whether we can
create memory and also the logic.

Thanks to any answers in advance.


Peter Alfke <Peter.Alfke@xilinx.com> wrote in message news:<3CE41C9C.3AE88096@xilinx.com>...
> The short answer is: yes, it does.
> The long answer is that Programmable Logic just contains large arrays of
> digital logic, arithmetic circuits and memory that can be interconnected
> freely to achieve any digital function, at a reasonable speed. Your
> question was very abstract, but the answer is: yes.
> Peter Alfke, Xilinx Applications
> =====================================
> Jan Ziak wrote:
> 
> > Hi. I would like to know what exact properties a programmable array
> > has. More precissely, I want to know whether it allows to represent
> > any algorithm, that is whether a programmable array includes:
> >
> > 1. causality (i.e. conditional execution in general)
> > 2. stability (i.e. some sort of memory)
> >
> > I was searching for this information in the internet but have found
> > nothing.
> >
> > I would like to know whether such PA exists.
> >
> > Thanks in advance.

Article: 43245
Subject: Re: Timing constraints on internal signals
From: "Jerzy Gbur" <furia@wp.pl>
Date: Fri, 17 May 2002 11:48:40 +0200
Links: << >>  << T >>  << A >>
Hi
> I'm a newby trying to use the Xilinx ISE constraints editor to put timing
> constraints on  internal signals (i.e. signals that don't go to output
> pads).  The internal signals consist of a bus being reclocked.  Any
guidance
> on how this is done?  (For discussion purposes, assume the clks are clk1
and
> clk2 and the signal busses are bus1 and bus2)

Maybe more details? There is simple instruction in every ucf file, generated
by ISE.

furia




Article: 43246
Subject: Re: What properties has FPGA?
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 17 May 2002 10:08:39 -0000
Links: << >>  << T >>  << A >>
>I will reformulate the question one more: can we freely make tradeoffs
>between the size of memory and spatial complexity of an algorithm? So
>can we create memory and also any interconnection pattern between the
>"logic gates"? The question is whether the number of memories and
>logic gates is fixed in current implemetations or whether we can
>create memory and also the logic.

It sounds like you are thinking of "real" gate arrays where
you get a big sea of gates and you have to use them to make
flip-flops.  FPGAs aren't like that.  You typically get an
array with a reasonable (for most projects) ratio of logic
to storage.  Typically one FF per LUT.  LUT is look-up-table.
You can get any logic equation you want as long as it has N
or fewer inputs.  That's the logic gates part of many FPGAs.
n is typically 4.

If you see a number like "100K equivalent gates", that's just
marketing noise.



The size is fixed.  You don't have to use it all.  Most people
get a larger chip if their problem doesn't fit.  That only works
so far.  Sometimes you run out of storage first.  Sometimes you
run out of logic.

There is some flexibility, but you generally can't trade logic
gates for storage.  Xilinx allows you to use a 4 input LUT
as a 16 bit shift register.  You can use big RAMs (storage) as
table lookup (logic).

I'm not sure what you mean by "spatial complexity".  Routing
resources are also limited.  If your problem requires too
complicated an interconnect pattern you will get into trouble.
This is one of the hard parts of using FPGAs.  If your problem
is regular and easy to draw the diagram/schematic on paper
without a blizard of crossing lines then it will probably fit
in an FPGA.

You can probably get a better feel for this by looking at
a data sheet.  They are easy to find on the web.


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 43247
Subject: Re: Architecture for high-level reconfigurable computing
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Fri, 17 May 2002 11:13:31 +0100
Links: << >>  << T >>  << A >>
Keith R. Williams wrote

> I'd like to know if people *really* want security (as in paying
> for it). Since I worked in secure/crypto hardware for some years
> it's kinda a side interest for me. The technology is not only
> available, but cheap.  The management of any real security is the
> real problem.

Yes, worth paying for.  Though not worth the cost and problems of
the battery solution.

Mostly my customers just want to raise the bar on copying.  Program
a (secret) key into the chip at manufacturing time, then the copiers
would not be able to use your bitstream without cracking the key.
Of course they would still be able to work the problem from other
angles, but the other angles are all significantly more difficult
than just copying a bit stream.





Article: 43248
Subject: Re: Architecture for high-level reconfigurable computing
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 17 May 2002 10:17:35 -0000
Links: << >>  << T >>  << A >>
>I'd like to know if people *really* want security (as in paying 
>for it). Since I worked in secure/crypto hardware for some years 
>it's kinda a side interest for me. The technology is not only 
>available, but cheap.  The management of any real security is the 
>real problem.

I have one data point.  I worked on one card that got to production.
It was an early ATM card, expensive, but worked well, and it was
available "now".

We didn't worry about getting cloned - never thought about it.
I'll bet if somebody wanted to clone it we would have given them
the whole package as long as they would sell boards back to us.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 43249
Subject: Re: Reading GSR signal of Spartan-II
From: "sweir" <weirsp@yahoo.com>
Date: Fri, 17 May 2002 12:31:35 GMT
Links: << >>  << T >>  << A >>
Stephanie,

I think what you are trying to ask is:

"How do I use the internal global reset in a design that does not have an
external reset pin?"

If so, then all you need to do is instantiate the ROC ( reset on
configuration ) component in your design.  You can connect that output to
RTL that has async reset logic.

Regards,
"Stephanie McBader" <mcbader@neuricam.com> wrote in message
news:3CE4AE8C.7016211F@neuricam.com...
> OK, that I understand.. But what I need is to *read* the GSR net - how can
I do
> that?
>
> Still looking out for help :)
>
> - Cross posted to comp.arch.fpga
>
> Best Regards,
>
> Stephanie McBader
> Researcher/Design Engineer
> NeuriCam S.p.A
> Via S M Maddalena 12
> 38100 Trento TN, Italy
> Tel: +39-0461-260552
> Fax: +39-0461-260617
>
>
> Allan Herriman wrote:
>
> > [snip]
>
> > You can drive GSR (to reset or set every flip flop in the chip) by
> > asserting the GSR input on the startup block at any time.
> >
>
> I earlier wrote:
>
> > >> Hi there,
> > >>
> > >> Apologies if this has come up before - I have searched both
newsgroups
> > >> and the Xilinx support website but I have not found *exactly* what
I'm
> > >> looking for.
> > >>
> > >> Is it possible to *read* the GSR signal of a Spartan-II FPGA? The
> > >> problem is that we have a system in which a controller must be
> > >> implemented inside the FPGA but which does not provide any form of
reset
> > >> signal as an input to the FPGA logic. I have had a look at the
> > >> Spartan-II datasheet and on page 19 there is a waveform describing
the
> > >> start-up sequence of the FPGA after programming. The GSR is evidently
> > >> active high and is negated shortly after DONE goes high. I would like
to
> > >> be able to use the GSR value as an asynchronous reset input to the
logic
> > >> implemented in the FPGA.. How do I do this?
> > >>
> > >> I have seen numerous answers pointing to the STARTUP block, but this
> > >> only has the GSR signal as an *input*! I need to read it somehow and
I
> > >> do not know which source to use..
> > >>
> > >> Oh, we're using VHDL by the way (just thought I'd mention it even
though
> > >> this *is* comp.lang.vhdl)
> > >>
> > >> Your help would be much appreciated.
> > >>
> > >> Regards,
> > >>
> > >> Stephanie McBader
>
>
>





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