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Messages from 43175

Article: 43175
Subject: Re: Architecture for high-level reconfigurable computing
From: Neil Franklin <neil@franklin.ch.remove>
Date: 15 May 2002 21:31:48 +0200
Links: << >>  << T >>  << A >>
Micah Dowty <micahjd@users.sourceforge.net> writes:

> On Tue, 14 May 2002 14:34:37 -0600, Neil Franklin wrote:
>
> >> If JBits can in fact to routing, it
> >> sounds like a good interim solution to use until you reverse engineer
> >> the bitstream so we can have faster and open tools.
> >
> > It can and it is.
>
> Sounds like it would be useful to have an intermediate format that could
> be fed into a JBits-based tool or into your open tools. Are there already
> any good formats for this?

Never heard of one.
But also never looked for one, so above does not mean much.


FYI: I am presently aiming that my tools will be 2-level:

- an .so library (libvirtex) with an API of functions, callable from
  C (or possibly also perl).
- an assembler-like program (vas) that uses above library, and reads
  an abstracted assembly-like source file.

Aim of that is that then VHDL/Verilog/... compilers can target 'vas'
to make the bitstream, the same as the gcc C/Fortran/... compilers
target 'as' to make the binaries.

I _perhaps_ may develop the 'vas' source language still using JBits,
i.e. there would in the end exist 2 assemblers for it, one written in
Java/JBits and one in C/libvirtex.


This source form may be usefull as an intermediate form for you:

design---your-Tool---C/gcc---as-------------binary for CPU
                 `---X/???---vas/libvirtex--bitstream for FPGA
                           `-vas/JBits-----'

Of course this language is not yet defined, so it may be no more use
to you than waiting till I am finished. So perhaps better to use
direct JBits and then convert.

For an preview of the ideas going into developing this language, look
at the style adopted in my PDP-10 code. Particularly how I wrap the
JBits API with the stuff in the first larger section of the code.


P.S: I am now going offline for 5 days, visiting the anual
German/Swiss/Austrian Linux User Group meeting. They should have
Internet there, but last year it sucked so bad that even ssh failled.
So I do not expect to be able to Usenet while there.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Make your code truely free: put it into the public domain

Article: 43176
Subject: Re: PCI Board Project
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 15 May 2002 21:39:22 +0200
Links: << >>  << T >>  << A >>
"Micah Dowty" <micahjd@users.sourceforge.net> schrieb im Newsbeitrag
news:pan.2002.05.15.18.06.34.810837.4538@users.sourceforge.net...
> At those prices you're probably better off using a Spartan II device. You

Yes, its is STRONGLY recommended to use a Spartan-II, not those old 4k
stuff.

> can use the WebPack tools to design for them. I've seen the Spartan II
> for $20 or so at digi-key but only in quantities of at least 25 IIRC. I
> might need to get me some FPGAs for my own board in the sort-of-near
> future. Is there any place to get them in < 10 quantity nowadays?

Sure.

www.nuhorizons.com


--
MfG
Falk





Article: 43177
Subject: Re: Eliminating Hierarchy in Xilinx XST
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Wed, 15 May 2002 15:23:10 -0500
Links: << >>  << T >>  << A >>


Edzel wrote:
> 
> 
> Yup, that sure did it. I've checked with the output EDN file and only the
> modules with the keep_hierarchy attribute set to "yes" remained. But
> something weird happened. The device usage still remained the same. There
> were no improvements. I was hoping that by eliminating the hierarchy
> between the submodules, XST could do a better job of optimizing the logic
> and area. Any comment on this?


        I doubt that the synthesis tool will be able to remove that many
redundant LUTs/FFs.
You will be lucky if the synthesis tool finds some FFs doing the same
thing.
I suppose you can optimize the design for area, but I know that that
really kills the speed of the design. (i.e., maximum frequency and setup
time.)
At this point, you will have to find some ways to make your design
smaller which might be possible if you try, or use a larger device.



Regards,



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 43178
Subject: xilinx foundation 2.1 RPC problem on win2000
From: hunter@dementedhampsters.com (Brad)
Date: 15 May 2002 13:24:18 -0700
Links: << >>  << T >>  << A >>
I have installed the xilinx foundation 2.1i software on a win2000
machine (multiple times.  As user.  As admin).  It seems to 
install fine and I can run part of the program.  I can enter a
VHDL design but when I try to sysnthesize I get errors:

Pcm  :Automation cause an exception, exit code 80010104
Pcm  :RPC could not call the server or could not return the results of 
calling the server
Pcm  :Automation caused and exception, exit code 800706BA
Pcm  :The RPC server is unavailable.

thanks

Article: 43179
Subject: Re: Architecture for high-level reconfigurable computing
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 15 May 2002 20:25:47 GMT
Links: << >>  << T >>  << A >>
"Steve Casselman" <sc.nospam@vcc.com> writes:

>Yes the other way in C is to have functions that run in parallel like
>threads. The compiler must be smart enough to infer real parallel hardware.
>Also if you take the list operator and define the behavior as fully parallel
>then C does not seem sequential.

Say I take an FFT algorithm from Numerical Recipes in C.

What is the chance that I will find a compiler that can generate
a reasonable FPGA implementation of that algorithm, say in the
next 5 years to give someone a chance?

-- glen


Article: 43180
Subject: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Wed, 15 May 2002 15:30:41 -0500
Links: << >>  << T >>  << A >>


Jerzy Gbur wrote:
> 
> 
> I'm not sure I understood You have problems with FF in IOB?
> Maybe You should look at (Xilinx) OnLine documentation in section:
> Constraints (Keep Hierachy, IOB)
> and VHDL - using "generate" or "loop"
> Try
> 
> furia


        I believe I have a good understanding of the IOB packing rules.
I have read all the related documentations Xilinx publishes.
I will suggest that you try to get IOB FFs duplicated with "Add I/O
Buffers" option unchecked, and then you will see what I am talking about
because XST will just not duplicate them with the I/O pads. 



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 43181
Subject: Re: PCI Board Project
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Wed, 15 May 2002 15:34:05 -0500
Links: << >>  << T >>  << A >>
Why use older parts?
You should use a Spartan-II at least.
If doing so, you should use a PQ208 version which is cheap.
Also, do you got a PCI IP core to test it out?



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 43182
Subject: Re: Altera/Quartus II: unconditional loop?
From: "Kevin Neilson" <kevin-neilson@removethistextattbi.com>
Date: Wed, 15 May 2002 21:13:10 GMT
Links: << >>  << T >>  << A >>
sorry, I meant i.e., not e.g.  I always get my Latin mixed up.
"Kevin Neilson" <kevin-neilson@removethistextattbi.com> wrote in message
news:DAvE8.24578$L76.1255@rwcrnsc53...
> This is inline sequential code, e.g. software.  This may run as a
simulation
> but will not create hardware.  Since you are still learning
(synthesizable)
> HDL, I suggest you draw a schematic of the circuit you want to create and
> then convert it to HDL.  If you can't visualize the circuit, then the
> synthesizer probably can't either.
> -Kevin
>
> "Ted Bronson" <tedbronson@hotmail.com> wrote in message
> news:3CE1A04B.8000506@hotmail.com...
> >
> >
> > Dines Justesen wrote:
> >
> > >>I'm a bit new to all this... why doesn't the Quartus II
> > >>support the "loop <body> end loop;" loop??
> > >>
> > >
> > > When synthesizing VHDL loops inside a process will result in the logic
> > > inside the loop being repeated as many time as the code is looped. So
if
> > > you loop a statement which generates and adder 16 times, it will
> generally
> > > create 16 adders. So an unconditional loop will keep generating new
> > > hardware, which wont fit in a any device.
> > >
> > > Suggesting an alternative way of implementing your function would be
> easier
> > > if you posted the code you have now, but I think that a process with
the
> > > right sensitivity lis (and no loops) might be the soltion. (A process
> with
> > > a sensitivity list will loop everytime one of the signals in the
> > > sensitivity list changes)
> > >
> > > Dines
> > >
> > >
> >
> > I was going to do that at first, but didn't because as I
> > found in my reading, this should be a legal thing to do.
> >
> > But... here's what I'm trying to do:
> >
> > process is
> > begin
> >    loop
> >      wait until clk_2MHz = '0';
> >      start <= '0';
> >      wait until busy = '0';
> >      wait until bust = '1';
> >      data <= data_bus;
> >      start <= '1';
> >    end loop;
> > end process;
> >
> > The idea is that, since the loop will take much
> > less than 500 nsec to run, I would wait until the
> > clock went low, trigger start, wait for busy to
> > go low, then high, then I could latch the data bus,
> > and clear start, then do it all over again.
> >
> > Now, I'm just learning VHDL (I did well in the classes
> > and since I know Ada, the language per se isn't too hard),
> > so if there are ignorant mistakes in here, please
> > overlook them (and make suggestions if you wish).
> >
> > BTW Quartus ALSO does not like having multiple wait
> > statements, which I also don't understand, because I've
> > seen examples in VHDL texts which indicate this should be
> > legal.
> >
> > If anyone wishes, could you explain the divergence between
> > Quartus II and VHDL '93???  I've only been exposed to
> > one tool, so I really don't know what to expect (NOT like
> > a compiler...).
> >
> > Regards,
> >
> > TB
> >
>
>



Article: 43183
Subject: Re: Altera/Quartus II: unconditional loop?
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Wed, 15 May 2002 22:49:45 +0100
Links: << >>  << T >>  << A >>
Kevin Neilson wrote
> sorry, I meant i.e., not e.g.  I always get my Latin mixed up.


Mutatis mutandis.




Article: 43184
Subject: Re: Exemplar in ISE
From: theoldgeezer@hotmail.com (the Geez)
Date: 15 May 2002 15:27:23 -0700
Links: << >>  << T >>  << A >>
I tried the VHDL group with no reply..anyone here heard?

> Hi,
> I have heard that Leonardo is going to be included in Xilinx ISE to
> replace FPGA Express and as an alternate to XST.  Does anyone know for
> sure?
> G

Article: 43185
Subject: Re: Altera/Quartus II: unconditional loop?
From: Dines Justesen <dines@aub.dk>
Date: 15 May 2002 23:05:07 GMT
Links: << >>  << T >>  << A >>
> I was going to do that at first, but didn't because as I
> found in my reading, this should be a legal thing to do.

Your code seems like it would work fine in a simulator, but not all legal 
VHDL code can be synthesized. There are common ways to write lots of 
standard functions i VHDL, and most synthesized has a manual describing how 
to write the VHDL in way the synthesizer understands (I know Xilinx has 
manuals like that, Altera probably has some too). Try downloading one of 
those manual and have a look at the VHDL code shown there.

> BTW Quartus ALSO does not like having multiple wait
> statements, which I also don't understand, because I've
> seen examples in VHDL texts which indicate this should be
> legal.

If you try to simulate it it will work fine, but synthesizers will have a 
hard time converting it to real hardware. If you now how you want the 
hardware to look before you write your code youwill ususally end up with 
better code.

-- 
---------------------------------------------------
 Dines Justesen | dines@aub.dk | www.aub.dk/~dines
---------------------------------------------------

Article: 43186
Subject: WEBPack 4.1 - vhdl modules in schematics?
From: leotran@_*worldnet.att.net (Loi Tran)
Date: Wed, 15 May 2002 23:16:45 GMT
Links: << >>  << T >>  << A >>
How do I add a VHDL module to schematic?  As it is, it's not very intuitive.

Thanks.

LT

Article: 43187
Subject: Re: Architecture for high-level reconfigurable computing
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 16 May 2002 11:56:24 +1200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Jim,
> 
> I didn't say that, but you guessed it.
> 
> In all fairness, as the we descend into the UDSM world, all foundries
> have NVRAM/ROM (read: fuse) type cells that they are offering (eg in
> 0.1u). 

 Yes, but virage claim not ROM, but EE cells, supposedly on a Std CMOS
process.

# NOVeA is a non-volatile memory that can be reprogrammed multiple 
# times. Additionally, this memory can be embedded into a SoC and can be 
# fabricated in a state-of-the-art, leading edge standard logic process 
# with no additional process steps.

I do note they mention TSMC, but not UMC :-)

Does sound like a free lunch - anyone used these cells ?

-jg

Article: 43188
Subject: Re: Altera/Quartus II: unconditional loop?
From: Davis Moore <dmoore@ieeeNOSPAM.org>
Date: Wed, 15 May 2002 18:19:24 -0600
Links: << >>  << T >>  << A >>
Ted Bronson wrote:

> But... here's what I'm trying to do:
>
> process is
> begin
>    loop
>      wait until clk_2MHz = '0';
>      start <= '0';
>      wait until busy = '0';
>      wait until bust = '1';
>      data <= data_bus;
>      start <= '1';
>    end loop;
> end process;
>

I'm not familiar with VHDL, but the loop..end loop construct
looks like something you would use in your simulation or test
bench code. In other words, you would use the construct to
infinitely provide stimulus to the inputs of your circuit or design
during simulation.

The hardware by nature already operates in an infinite loop. You just need to
define what the hardware does and it will *always* do it. It may stop in
states, but it is always ready to transition to a new state when the inputs
change.





Article: 43189
Subject: Re: PCI Board Project
From: "Austin Franklin" <austin@dark98room.com>
Date: Wed, 15 May 2002 20:36:20 -0400
Links: << >>  << T >>  << A >>
> I need to design a PCI32 add-in board as a school project. Having a
> XESS XS40v1.2 eval board, I have some experience with the XC4010XL.
> The question goes as this:

> Is it feasible to implement a minimum
> target configuration with this IC?

Yes, and a full master too.  The logic can easily fit in an XC4010.

> If that were not the case, to which
> FPGA (in the XC4000 line) should I jump? And, finally (yes, I am a
> newbie in the area): where can I get prices of XC4000 ICs?

If your quantity as some monerary consideration, as others have suggested,
go to the Spartan series.  Your code from the 4k part should pretty much
work in the Spartan series.  I did one PCI board that first used a 4kE in a
240 PQFP, and used the same bitstream later on the same board, but with a
Spartan, same package, XCS30 I believe it was.  If that compatibility is
important to you, I suggest checking it out your self.

Regards,

Austin




Article: 43190
Subject: Re: Exemplar in ISE
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Wed, 15 May 2002 19:45:00 -0600
Links: << >>  << T >>  << A >>
Leonardo will not be included as part of the ISE package,
although integration will be offered if you already own
the software.  XST will be the only included synthesis tool.

Regards,
Kamal

the Geez wrote:

> I tried the VHDL group with no reply..anyone here heard?
> 
> 
>>Hi,
>>I have heard that Leonardo is going to be included in Xilinx ISE to
>>replace FPGA Express and as an alternate to XST.  Does anyone know for
>>sure?
>>G
>>


Article: 43191
(removed)


Article: 43192
Subject: Re: WEBPack 4.1 - vhdl modules in schematics?
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Wed, 15 May 2002 19:49:07 -0600
Links: << >>  << T >>  << A >>
Loi,

If you click on the VHDL source and look under the
Processes window, you should see a Process under
Design Entry Utilities that allows you to create a
schematic symbol from the file. Double-click it.

After successfully completing that process, a symbol
should be available in ECS for the VHDL file.  This
is all covered in the ISE Tutorial located here:
http://support.xilinx.com/support/techsup/tutorials/tutorials4.htm

Regards,
Kamal

Loi Tran wrote:

> How do I add a VHDL module to schematic?  As it is, it's not very intuitive.
> 
> Thanks.
> 
> LT
> 


Article: 43193
Subject: Re: Architecture for high-level reconfigurable computing
From: Keith R. Williams <krw@attglobal.net>
Date: Wed, 15 May 2002 22:07:22 -0400
Links: << >>  << T >>  << A >>
In article <3CE278BC.AC460E55@xilinx.com>, 
austin.lesea@xilinx.com says...

> Obviously, we are not into fuse (or anti-fuses), and have a long
> tradition of SRAM based FPGAs and EEPROM, EPROM based CPLDs.  Fuses just
> make us nervous ..... did they blow?  did we blow something else? Will
> they heal?  etc.  Right now, if a foundry is asked what the reliability
> of their 0.1u NV technology is, you can't expect an answer .... no one
> has built enough of anything yet to run a reliability study on.

Obviously you have your (official Xilinx) bias.  It's been stated 
with no uncertain terms. 

The fact is that these things have been used for at least ten 
years.  They've been used for similar applications for nearly as 
long (I personally know of such).  I'm on the other side of this 
fence, I *hate* batteries and as long as I work for my current 
employer I hope I won't be forced onto that pyre again.  Read the 
specs all you want, but batteries are not nice.  

As an example, think about storage of replacement parts in 
uncontrolled wharehouses in the middle of a desert!  Batteries 
are *bad* news.  

Your specs of .1nA don't impress me either (if that is even the 
right number).  It's *easy* to have contaminates on the board 
that have more leakage.  Anyone who's had a PC die because the 
frappin' battery went west knows this.
 
Reasonable people can differ in opinions, but your faith in 
batteries is very much displaced.  Some of us have *no* faith in 
batteries and have much experience with fuses. Don't tell me 
fuses cannot be done, because I know better.  Xilinx *chooses* 
not to go there.  That's a business decision and that's 
acceptable.  ...unless one needs real security and reliability.  

Yes, I consider "forever-caps" toys in this application. Consider 
a compu-nerd:  takes the card out and lays it on his anti-stat-
mat and then leaves for the weekend.  For most cards, not a 
biggie!  For the Xilinx customer's card? 

I really like Xilinx products, the company, the whole idea, but I 
don't understand the refusal to understand the other side's 
problems.  I've been a lurker here for three years, occasionally 
adding something when I can.  When it comes to some serious 
issues with the "Xilinx way" I see nothing but defense.  Yes, 
some of us have been well roasted by things you consider 
"trivial".

----
  Keith

Article: 43194
Subject: PCMCIA interface Logic Between PCMCIA LAN Card and ARM CPU....
From: "vandam" <lacoste@pionnex.com>
Date: Thu, 16 May 2002 11:28:32 +0900
Links: << >>  << T >>  << A >>
Hi, everybody!
I'm studing Altera FPGA nowadays. 
I am beginning the task of connecting an ARM CPU to  PCMCIA-base  LAN Card.
I'm tring to implement interface logic between PCMCIA LAN Card and ARM CPU.
Please help me. 
Is there any suggested reference logic, schematic or verilog hdl code ?

Regards,
vandam

P.S> Where can I get PCMCIA specipication? I can't find 'em.



Article: 43195
Subject: output rise and fall time for Spartan2E??
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Wed, 15 May 2002 22:44:15 -0400
Links: << >>  << T >>  << A >>
Hi,
    I am considering using a Spartan2E to generate a clock signal
(amongst other things).  The clock will probably be driven by a slow
LVTTL signal with a 12 mA drive current.  I am trying to decide whether
to terminate this output and if so how to do so (source vs load
termination, etc.)  To do so, I need to know what the rise and fall
times of the output signal are.  Please do not tell me to use IBIS.  I
am quite competent with SPICE and PSPICE but I have no experience with
IBIS models and no availability to the software.  For this simple
calculation I really don't need to use such tools anyway.  FYI the
transmission line will be less than 0.3 meters
(> 1 foot).  Load is one Spartan2E LVTTL input.  Frequency is 100MHz.
    Alternatively, I could use the differential LVPECL capacity of the
Spartan2E, but it appears to be overkill and would add an additional
connector pair to the system.

Theron Hicks


Article: 43196
Subject: Re: xilinx foundation 2.1 RPC problem on win2000
From: "sweir" <weirsp@yahoo.com>
Date: Thu, 16 May 2002 03:12:41 GMT
Links: << >>  << T >>  << A >>
Foundation 2.1 is a late 1998 / early 1999 pre Win 2000 product.  You should
at least get your hands on 3.x.  Preferably, get 4.2.  Or run 2.1i on NT4.0.

Regards,
"Brad" <hunter@dementedhampsters.com> wrote in message
news:Xns920F884805AAFdementedhampsters@216.146.128.7...
> I have installed the xilinx foundation 2.1i software on a win2000
> machine (multiple times.  As user.  As admin).  It seems to
> install fine and I can run part of the program.  I can enter a
> VHDL design but when I try to sysnthesize I get errors:
>
> Pcm  :Automation cause an exception, exit code 80010104
> Pcm  :RPC could not call the server or could not return the results of
> calling the server
> Pcm  :Automation caused and exception, exit code 800706BA
> Pcm  :The RPC server is unavailable.
>
> thanks



Article: 43197
Subject: Re: PCMCIA interface Logic Between PCMCIA LAN Card and ARM CPU....
From: "Joze Dedic" <joze.dedic@email.si>
Date: Thu, 16 May 2002 10:09:49 +0200
Links: << >>  << T >>  << A >>
I have been working on the same projet for some time now - SA1110 and
PCMCIA...
If you look at SA1110 developers manual (Figure 10-23. PCMCIA External Logic
for a One-Socket Configuration) you should see that's quite simple.
- 10 signals on SA1110 is dedicated only to PCMCIA control (one is just for
socket select) - I used FPGA with these group just for buffering
- 8 PCMCIA control signals have to be implemented in FPGA
    * nCD1,nCD2,nVS1,nVS1 -  card type detect mechanism (you must support
detecting various combination of connection betwen each other in order to
recognize the card type and voltage requirements - as it is set by PCMCIA
specs.)
    * nINPACK, RDY - to SA1110 gpio
    * RESET, BVD1, BVD2 - simple regs in FPGA
Because of many other bus devices I used FPGA to buffer complete add & data
bus (and because of different voltages).

PCMCIA specs - I was searcing for some pdfs or sth elese... but no luck... I
got the specs in paper.

have a nice day, jOc

"vandam" <lacoste@pionnex.com> wrote in message
news:abv4fj$mr9$1@news1.kornet.net...
> Hi, everybody!
> I'm studing Altera FPGA nowadays.
> I am beginning the task of connecting an ARM CPU to  PCMCIA-base  LAN
Card.
> I'm tring to implement interface logic between PCMCIA LAN Card and ARM
CPU.
> Please help me.
> Is there any suggested reference logic, schematic or verilog hdl code ?
>
> Regards,
> vandam
>
> P.S> Where can I get PCMCIA specipication? I can't find 'em.
>
>



Article: 43198
Subject: XAPP173 BUG
From: "Dany" <daniel_hernanz_chiloeches@NOSPAMhotmail.com>
Date: Thu, 16 May 2002 09:15:26 GMT
Links: << >>  << T >>  << A >>
Hi,

The last two weeks I have been working in the implementation of a Ethernet
controller. I needed an asynchronous clocks FIFO and I find the XAPP173 :
"Using Block SelectRAM+ Memory in Spartan-II FPGAs". I downloaded the .vhd
file and tried to use it in my design. After some headaches I found a bug.
The .vhd sample file have a serious bugs.

The solution was try to look for other .vhd sample file. I found XAPP131 :
"170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature". This XAPP is the
same XAPP173, but with some corrections. This XAPP works very well with
asynchronous clocks ;-)

If its possible it would be interesting that the Xilinx engineers debug the
.vhd sample files of their XAPPs.

Sorry. My english is very bad.

Bye.

Dani








Article: 43199
Subject: SPARTAN II - Master serial mode configuration problem
From: "Joze Dedic" <joze.dedic@email.si>
Date: Thu, 16 May 2002 12:22:48 +0200
Links: << >>  << T >>  << A >>
I am trying to configure XC2S200 (FG456) 5C in master serial mode (M(2:0)
all 0) from PROM XC18V02 - but the problem is that configuration does not
succeed every time.
FPGA DONE signal stays low and CCLK is running at 5 MHz whenever the cofig
fails - but nPROGRAM and nINIT signals are high. I have even monitored the
bitstream (DIN) of succeded and failed config - it started in the same way.
FPGA is located on PCI evaluation board (6 layers - one for 3.3 and one for
GND). On this EVB fits platform with SA1110. Thing is that config succeeds
every time whenever I hold SA1110 in reset. This indicates on some noisy
enviroment problem. I think...
I have monitored core supply (2.5) and it is clean and stabile. There are 8x
10n, 8x 100n, 2x 1u, and 3x 10u F capacitators around FPGA.

Are there any config setings that I should change - or it is just lack of
blocking C and poor supply condition.

I would like to mention that one board (luckily the first one) works fine. I
have no ideas more. Thanks for any advice.

jOc





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