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Messages from 43250

Article: 43250
Subject: RPMs
From: Russell <rjshaw@iprimus.com.au>
Date: Fri, 17 May 2002 14:08:36 GMT
Links: << >>  << T >>  << A >>
Hi all,

I placed various primitives in floor-planner
(webpack 4.2, spartan2), then grouped and
bound it to make an RPM. I then put it back
into the hierarchy window, so that PAR can
place the RPM. I also saved the constraints
to the .ucf and .mfp files.

However, when i open floor-planner after PAR,
the group (GRP0) has been placed, but all the
primitives have been re-arranged (structure is
lost). Has anyone got RPMs to work right?

Article: 43251
Subject: Spartan II Proto. Board
From: gsletch@yahoo.com (Greg)
Date: 17 May 2002 07:12:03 -0700
Links: << >>  << T >>  << A >>
Hi,

I am looking at buying a Spartan II proto. board from Insight
Electronics and was wondering if I need to buy the package that comes
with the JTAG cable. There is ~ a $40 difference between the package
with and without the JTAG cable. Is it possible to use something other
than a JTAG cable to configure the FPGA?

Thanks,
Greg

Article: 43252
Subject: Re: HardPath
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 17 May 2002 07:48:25 -0700
Links: << >>  << T >>  << A >>

--------------31983CCE6626C0E462F69858
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Phil,

Your information is out of date.

Our test coverage has increased radically over the last four years, and is still increasing.

For details, you would need to contact your FAE, as most of this is proprietary (competitive
advantage gained by test techniques).  After signing an NDA we are happy to talk about our
improved test programs.

After all, we "sell" re-configuration, so we have to test for it as well.

Even if you discover a bug, and have to re-program with EasyPath, you do not have to scrap
everything - it requires a new test program, and inventories of bulk parts can be rescreened to
the new program.  Sure, it all costs money, but then, a bug in an ASIC is called scrap, and lost
market til it gets fixed.

Austin


Phil Hays wrote:

> Xilinx has a interesting idea with "EasyPath", in that they only test
> the parts of a Virtex-2 that are really used in your design, and save
> you some money in the process.
>
> http://www.xilinx.com/prs_rls/silicon_vir/0248easypath.html
>
> Of course, this isn't for everyone.  Some of the designs may reprogram
> devices to new designs frequently.  See:
>
> http://groups.google.com/groups?hl=en&lr=&selm 010731.103308.1239036029.24248%40polybus.com
>
> I would like to suggest "HardPath", in that Xilinx produces a more
> completely tested version of their parts, much as the above thread
> discussed.  As you may or may not know, Xilinx's parts are given a
> reasonable test, not a complete test.  This test is good enough for most
> users, however it may not be good enough for users that frequently
> reprogram devices to different designs, or where the cost of failing to
> correctly reprogram a device to a new design would be substantial.  So
> will Xilinx sell a version of their part with a more complete test?
>
> I know that tester time is expensive, and these parts would need to be
> priced higher, and that's ok.  I know that this doesn't guarantee that
> there still may be a defect that has been missed that will cause a
> device to fail work correctly with a new design.  After all, a complete
> test would take longer than practical.  I'm not looking for perfection.
> I'd just like better odds than what I see now.
>
> Anyone else interested?
>
> --
> Phil Hays



Article: 43253
Subject: Re: LOCKED signal of a DLL in a Virtex device questions
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 17 May 2002 07:49:18 -0700
Links: << >>  << T >>  << A >>
It is synchronous to the CLKIN pin.

The outputs are correct just before LOCKED goes high.

Austin

jfh wrote:

> Hi,
>
> I am wondering if the LOCKED signal of a DLL is synchronous to something ?
> Moreover are the clock outputs of a DLL correct as soon as the LOCKED signal
> is high or is there a little more time to wait before actually using the
> clock outputs ?
> Thanks.
>
> J.F.


Article: 43254
Subject: Re: What properties has FPGA?
From: John_H <johnhandwork@mail.com>
Date: Fri, 17 May 2002 15:11:58 GMT
Links: << >>  << T >>  << A >>
It almost sounds like you want to develop some C code to tell the FPGA to reconnect in an
alternative configuration dynamically.  Since you appear to be new to the concept of FPGAs,
there may be one or two things to understand.

Most FPGAs have a mix of memory (similar to RAM), registers, and combinatorial logic that can be
configured in just about any fashion.  To get an algorithm implemented in an FPGA, a hardware
designer needs to develop the algorithm targeted to logic that is parallel in nature;  where C
code typically works one instruction at a time instruction after instruction, the FPGA reaches a
new state across the entire device each clock cycle.  The algorithm is coded into hardware
compatible formats with - typically - a hardware description language such as Verilog or VHDL.
The code is synthesized with a program that knows the architecture of the device being
targeted.  A different program (or different module in an integrated development tool) will take
the synthesized code and perform the place and route function to take all the elements and
connectivity defined by the synthesizer and make it compatible for the target FPGA and to meet
timing and other constraints defined by the designer.

Many things that can be done with software algorithms can also be done with FPGAs, often much
faster.  The limit of FPGAs is their dedication:  software algorithms can seemlessly transition
- from decryption to ethernet protocol to mathematical transforms to memory management - with
little consideration for what other tasks may be present in the same code.  FPGAs cannot easily
make massive changes in the algorithm being implemented.  An FPGA can be reconfigured to a
predesigned algorithm in a fraction of a second.  Some FPGA devices allow a very short time to
transition from one configuration to another by shifting in the new configuration while the old
one is still operating (not mainstream devices, though).  An FPGA can be configured with
multiple algorithms - effectively multiple separately functional devices "under one roof" - and
some of the algorithms can be enabled and disabled but must still be present if they are ever to
be used.

These devices are very generic but the ability to hook the piece-parts together in the fashion
to accomplish the algorithm is a specialized task that isn't easily done well.

There is some effort being made into reconfiguable FPGAs that are a little more flexible from
the user's perspective, the hope being that the devices can be reconfigured on the fly with less
specialized knowledge of routing and architecture nuances but the development isn't mature and
the costs in performance in the immediate future are sever compared to dedicated solutions.

Good luck in your pursuits.


Jan Ziak wrote:

> The thing that I am interested in is precisely this one: can we
> reconfigure PLA so that is can contain 10 bits of memory in one case
> and 123 bits of memory in some other case? Can we create memory? Am I
> free to create any algorithm? If yes then I would like to know what
> model of PLA is capable of this. If not then I would like to know what
> is the problem, why it cant be done.
>
> I will reformulate the question one more: can we freely make tradeoffs
> between the size of memory and spatial complexity of an algorithm? So
> can we create memory and also any interconnection pattern between the
> "logic gates"? The question is whether the number of memories and
> logic gates is fixed in current implemetations or whether we can
> create memory and also the logic.
>
> Thanks to any answers in advance.
>
> Peter Alfke <Peter.Alfke@xilinx.com> wrote in message news:<3CE41C9C.3AE88096@xilinx.com>...
> > The short answer is: yes, it does.
> > The long answer is that Programmable Logic just contains large arrays of
> > digital logic, arithmetic circuits and memory that can be interconnected
> > freely to achieve any digital function, at a reasonable speed. Your
> > question was very abstract, but the answer is: yes.
> > Peter Alfke, Xilinx Applications
> > =====================================
> > Jan Ziak wrote:
> >
> > > Hi. I would like to know what exact properties a programmable array
> > > has. More precissely, I want to know whether it allows to represent
> > > any algorithm, that is whether a programmable array includes:
> > >
> > > 1. causality (i.e. conditional execution in general)
> > > 2. stability (i.e. some sort of memory)
> > >
> > > I was searching for this information in the internet but have found
> > > nothing.
> > >
> > > I would like to know whether such PA exists.
> > >
> > > Thanks in advance.


Article: 43255
Subject: Re: Frequency synthesiser
From: John_H <johnhandwork@mail.com>
Date: Fri, 17 May 2002 15:35:10 GMT
Links: << >>  << T >>  << A >>


Hal Murray wrote:

> > The book I bought in '96 proved very interesting at the time when
> > I was doing some DDS design.
>
> > Digital Techniques in Frequency Synthesis
> > Bar-Giora Goldberg
> > McGraw-Hill 1996
>
> Thanks.  How does that compare to a modern general DSP type book?

I'm not so familiar with DSP texts.  The book I mentioned covers what you need to know
for solid frequency synthesis to include how to get desireable preformance for
parameters that are typical to frequency synthesis.

> One application I had in mind was something like a clock that
> could be used for keeping time on computers.  Software can
> compute the actual frequency of the local "reference" clock
> if there is a better reference clock out there on the net (and
> NIST, USNO  and many GPS clocks are on the net).  It just takes
> a while.  Given that info it should be reasonable to make a
> 10,000,000.000 Hz clock from a reference that's (say) 9,999,993.638 Hz.

This level of adjustment can be made without great concern for Fractional-N or
filtering issues for a VCXO.  To get a VCO near those levels, a real PLL scheme would
have to be in place and adjustments made to "nudge" the phase/frequency the right
direction.  If all you need is timekeeping, the accuracy probably isn't high enough
that adjustments beyond software controlled voltage changes to the VCXO tuning is
needed.  If your tuning range is +/100ppm on a 10MHz clock, the +/- 1kHz range can be
cut down to less than 8 Hz for a single step in an 8-bit DAC.  You can get tiny 16 bit
DACs to make the software servicing interval much longer.  To do the phase comparison
in software, you have an error of at least one cycle in a reading anyway making the
8-bit DAC software overhead on the order of 8 events per second.  Your absolute time
can be kept to about 100ns pretty readily.  Adding software techniques to produce
dither might improve on that further, but there are other VCXO factors like "Allen
varience" that might get into your system and make the frequency a little harder to pin
down.  Those factors are where solid frequency synthesis system knowledge can tie up
the loose ends.

> For timekeeping, the phase noise isn't a problem as long as the
> long term answer is accurate.  But part of me wants to clean that
> up too, so then the question is how to do it and how clean can
> you get.  That's where the VXCO came from.

You can only lowpass a signal so far but the phase noise that you would get from a +/-
100ppm VCXO changing with an 8-bit DAC would be nearly imperceptible since the phase
noise introduced wouldn't be in the 10kHz range or even the 100Hz range.  It would be
on the order of 8 Hz - the software control time.  Move it to a 16 bit DAC and you have
to move to the time domain - phase offset measurements - to see the difference.  Using
your dual counters with an appropriate software algorithm, the only time domain
difference you'll see with that 16 bit DAC controlled VCXO is due to the oscillator's
limits.


Article: 43256
Subject: Re: Problem with Xilinx ISE 4.2i map
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Fri, 17 May 2002 09:39:52 -0600
Links: << >>  << T >>  << A >>
Hello Roman,

Please check Xilinx Answer Record 10719 as it seems to
be related to your problem.  You can find it here:

http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=10719

Regards,
Kamal

Roman MORAWEK wrote:

> In my design I previously used the Xilinx ISE 2.1i tools and everything worked without a problem.
> 
> Changing to ISE 4.2i I get the following error using map:
> 
> Release 4.2.01i - Map E.36
> Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
> Reading NGD file "if_asic.ngd"...
> Using target part "4020xlabg256-07".
> MAP xc4000xla directives:
>    Covermode = "area".
>    Pack Unrelated Logic into CLBs targeting 100% of CLB resources.
> Processing logical timing constraints...
> ERROR:OldMap:661 - FDP symbol
>    "pm_slave_unit/pm_bscan_slave/tap_dr_shift_cnt_reg<0>" (output
>    signal=pm_slave_unit/pm_bscan_slave/tap_dr_shift_cnt<2>) - The attribute RLOC
>    has been placed on the wrong type of symbol.  Please consult the "Attributes,
>    Constraints, and Carry Logic" section of the Libraries Guide for more
>    information on legal parameters.
> ... 5 more times for the other elements of the tap_dr_shift_cnt array...
> ERROR:OldMap:630 - Problems were found processing RPMs in the design.
> Errors found in users design.  Output files not written.
> 
> Design Summary
> --------------
> Number of errors   :   6
> Number of warnings :   1
> 
> 
> pm_slave_unit/pm_bscan_slave/tap_dr_shift_cnt is a signal array of type integer with imo no special vhdl code associated.
> 
> I used Synopsys FPGA Express Version: 2001.08-FE3.6, Build: 3.6.0.6613 and NgdBuild - Release 4.2.01i - edif2ngd E.36.
> 
> The "Attributes, Constraints, and Carry Logic" section of the Libraries Guide brought no useful information for me.
> 
> What causes this error?
> Where should I start to fix this problem?
> 
> thanks,
> Roman Morawek
> 
> 


Article: 43257
Subject: Re: What properties has FPGA?
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Fri, 17 May 2002 08:46:44 -0700
Links: << >>  << T >>  << A >>
The answer is still: yes.
There is obviously an upper limit for the complexity and speed of the implementation in any
particular programmable logic part, but there is no inherent limit to the way you can
interconnect and structure logic gates, memory etc.

Peter Alfke

Jan Ziak wrote:

> The thing that I am interested in is precisely this one: can we
> reconfigure PLA so that is can contain 10 bits of memory in one case
> and 123 bits of memory in some other case? Can we create memory? Am I
> free to create any algorithm? If yes then I would like to know what
> model of PLA is capable of this. If not then I would like to know what
> is the problem, why it cant be done.
>
> I will reformulate the question one more: can we freely make tradeoffs
> between the size of memory and spatial complexity of an algorithm? So
> can we create memory and also any interconnection pattern between the
> "logic gates"? The question is whether the number of memories and
> logic gates is fixed in current implemetations or whether we can
> create memory and also the logic.
>
> Thanks to any answers in advance.
>
> Peter Alfke <Peter.Alfke@xilinx.com> wrote in message news:<3CE41C9C.3AE88096@xilinx.com>...
> > The short answer is: yes, it does.
> > The long answer is that Programmable Logic just contains large arrays of
> > digital logic, arithmetic circuits and memory that can be interconnected
> > freely to achieve any digital function, at a reasonable speed. Your
> > question was very abstract, but the answer is: yes.
> > Peter Alfke, Xilinx Applications
> > =====================================
> > Jan Ziak wrote:
> >
> > > Hi. I would like to know what exact properties a programmable array
> > > has. More precissely, I want to know whether it allows to represent
> > > any algorithm, that is whether a programmable array includes:
> > >
> > > 1. causality (i.e. conditional execution in general)
> > > 2. stability (i.e. some sort of memory)
> > >
> > > I was searching for this information in the internet but have found
> > > nothing.
> > >
> > > I would like to know whether such PA exists.
> > >
> > > Thanks in advance.


Article: 43258
Subject: Re: Architecture for high-level reconfigurable computing
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Fri, 17 May 2002 08:51:45 -0700
Links: << >>  << T >>  << A >>


Tim wrote:

> Keith R. Williams wrote
>
> Yes, worth paying for.  Though not worth the cost and problems of the
> battery solution.

Cost cannot be the issue. Battery plus holder are less than $2.
Reliabilty is the subject of some discussions, not cost.

Peter Alfke


Article: 43259
Subject: Re: PCI Board Project
From: "Austin Franklin" <austin@dark98room.com>
Date: Fri, 17 May 2002 11:57:19 -0400
Links: << >>  << T >>  << A >>

"Stephan Neuhold" <stephan.neuhold@xilinx.com> wrote in message
news:3CE4BB8F.A4A8D821@xilinx.com...
> Yes, according to the new spec. there should be a time of 100ms provided
before
> your device actually needs to be active on the bus.

Stephan,

I believe the PCI 2.2 spec says in Table 4-6 that it is  2^25 clocks from
RST# high to First configuration Access.  And...since the PCI bus powers up
at 33MHz, no matter what's in the slots (so it can check 66MHz capability),
that would be 0.000_000_030 seconds times 2**25th which I believe is 1
second.

An issue to be aware of, is that this was not spec'd in the 2.1 and earlier
PCI spec, but...having designed quite a few Xilinx FPGA interfaces, and them
being in thousands of production boards for some near 10 years now, I have
never run into a problem, at least that I've heard of ;-)

Austin




Article: 43260
Subject: Re: PCI target with FPGA question
From: "Austin Franklin" <austin@dark98room.com>
Date: Fri, 17 May 2002 11:59:09 -0400
Links: << >>  << T >>  << A >>

"Stephan Neuhold" <stephan.neuhold@xilinx.com> wrote in message
news:3CE4B2A9.4FB71991@xilinx.com...
> Hi Maurico,
>
> The PCI spec now includes a minimum time after which the PCI agents should
> be active on the bus, and this time is 100ms

Stephan,

(this is a re-post of another reply to the same issue)

I believe the PCI 2.2 spec says in Table 4-6 that it is  2^25 clocks from
RST# high to First configuration Access.  And...since the PCI bus powers up
at 33MHz, no matter what's in the slots (so it can check 66MHz capability),
that would be 0.000_000_030 seconds times 2**25th which I believe is 1
second.

An issue to be aware of, is that this was not spec'd in the 2.1 and earlier
PCI spec, but...having designed quite a few Xilinx FPGA interfaces, and them
being in thousands of production boards for some near 10 years now, I have
never run into a problem, at least that I've heard of ;-)

> (apparently Xilinx requested
> this info to be added to the spec).

Well, I don't know if Xilinx did, but I certainly did ;-)

Austin




Article: 43261
Subject: Re: PCI Board Project
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Fri, 17 May 2002 17:14:58 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------A8CFC19CA371B961DA6994C6
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Yes of course. My mistake. I was looking at the reset signal. Add to this 2^25
clocks at 33MHz and get 1.0666secs. So, 100ms + 1.0666secs = more than enough
time for configuration. Thanks for pointing out the mistake.

Austin Franklin wrote:

> "Stephan Neuhold" <stephan.neuhold@xilinx.com> wrote in message
> news:3CE4BB8F.A4A8D821@xilinx.com...
> > Yes, according to the new spec. there should be a time of 100ms provided
> before
> > your device actually needs to be active on the bus.
>
> Stephan,
>
> I believe the PCI 2.2 spec says in Table 4-6 that it is  2^25 clocks from
> RST# high to First configuration Access.  And...since the PCI bus powers up
> at 33MHz, no matter what's in the slots (so it can check 66MHz capability),
> that would be 0.000_000_030 seconds times 2**25th which I believe is 1
> second.
>
> An issue to be aware of, is that this was not spec'd in the 2.1 and earlier
> PCI spec, but...having designed quite a few Xilinx FPGA interfaces, and them
> being in thousands of production boards for some near 10 years now, I have
> never run into a problem, at least that I've heard of ;-)
>
> Austin



Article: 43262
Subject: SDRAM pricing
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 17 May 2002 14:30:47 -0400
Links: << >>  << T >>  << A >>
I am seeing the price of 256 Mbit SDRAM at about $20 to $25.  This is
about 8 times what it costs for the same amount of memory on DIMMs.  I
know that quantity makes a difference, but I can buy a single 256 MByte
DIMM for $22 or I can buy 1k 32 MByte SDRAM chips at $20 each.  This
seems very excessive.  

Anyone getting better pricing on 16x16 SDRAM?  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 43263
Subject: virtex 2 block rams
From: shparekh@yahoo.com
Date: 17 May 2002 11:38:26 -0700
Links: << >>  << T >>  << A >>
Hi,

I am trying to convert bus widths.  One bus spans multiple block rams.
 In other words while writing to brams, the data word is 96 bits - 3
block rams.  While reading, the word is 32 bits i.e. 1 block ram at a
time.  Therefore, while reading I need to access the three block rams
for which I use lower order address bits to enable the block rams.  My
question is if I take away the enable will the output port of the
block ram be placed in tristate.  If so then on the read port I can
simply bus the output data to all the block rams.

I was trying to search for this information in the databook/handbook
but no luck so far.

I would appreciate some words of wisdom.

-sanjay

Article: 43264
Subject: Re: Architecture for high-level reconfigurable computing
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Fri, 17 May 2002 19:49:27 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote

> Tim wrote:
>
>> Yes, worth paying for.  Though not worth the cost and problems of the
>> battery solution.
>
> Cost cannot be the issue. Battery plus holder are less than $2.
> Reliabilty is the subject of some discussions, not cost.

Absolutely.  What I should have said is the "real estate cost".
It is quite a while since I did a design where physical size was
not a prime constraint.  But maybe that is just my destiny working
itself out.





Article: 43265
Subject: Re: virtex 2 block rams
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 17 May 2002 20:49:31 +0200
Links: << >>  << T >>  << A >>
<shparekh@yahoo.com> schrieb im Newsbeitrag
news:f54889e9.0205171038.293e1918@posting.google.com...
> Hi,
>
> I am trying to convert bus widths.  One bus spans multiple block rams.
>  In other words while writing to brams, the data word is 96 bits - 3
> block rams.  While reading, the word is 32 bits i.e. 1 block ram at a
> time.  Therefore, while reading I need to access the three block rams
> for which I use lower order address bits to enable the block rams.  My
> question is if I take away the enable will the output port of the
> block ram be placed in tristate.  If so then on the read port I can
> simply bus the output data to all the block rams.

No, BRAM outputs have tristae capability. In virtex-II there are "just"
three different data-out mode during read (old or new data).
Just use a MUX for the BRAM outputs. If speed is critical, pipeline.

--
MfG
Falk





Article: 43266
Subject: Re: virtex 2 block rams
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Fri, 17 May 2002 12:05:09 -0700
Links: << >>  << T >>  << A >>
"word of wisdom"
I think ( note the cautious wording) that you can eliminate this problem
by reorganizing your input data, effectively scrambling it, so bit 0 is
written in one BlockRAM, 1 in the next BlockRAM, etc. I am pretty sure
this works for 128 bits in 4 BlockRAMs.
I got a headache figuring it out for 3 BRAMs.
Maybe I am all wrong, but if it works, it would be really neat...
Peter Alfke, Xilinx Applications
===================================
shparekh@yahoo.com wrote:

> Hi,
>
> I am trying to convert bus widths.  One bus spans multiple block rams.
>  In other words while writing to brams, the data word is 96 bits - 3
> block rams.  While reading, the word is 32 bits i.e. 1 block ram at a
> time.  Therefore, while reading I need to access the three block rams
> for which I use lower order address bits to enable the block rams.  My
> question is if I take away the enable will the output port of the
> block ram be placed in tristate.  If so then on the read port I can
> simply bus the output data to all the block rams.
>
> I was trying to search for this information in the databook/handbook
> but no luck so far.
>
> I would appreciate some words of wisdom.
>
> -sanjay


Article: 43267
Subject: Re: RPMs
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 May 2002 19:20:09 GMT
Links: << >>  << T >>  << A >>
Yes, but not ones created in the floorplanner and then left
unplaced.  The floorplanner doesn't create RLOCs needed to
make an RPM persist outside of the floorplanner.  It will
persist if you place the created RPM on the grid, but that
works by essentially putting LOCs on the parts.   To do what
you are trying to do, you unfortunately have to do the RLOCs
in your source rather than trying to bind the RPMs in the
floorplanner.  This is an unfortunate artifact of the fact
that the floorplanner works with a flattened view of the
design.

Russell wrote:

> Hi all,
>
> I placed various primitives in floor-planner
> (webpack 4.2, spartan2), then grouped and
> bound it to make an RPM. I then put it back
> into the hierarchy window, so that PAR can
> place the RPM. I also saved the constraints
> to the .ucf and .mfp files.
>
> However, when i open floor-planner after PAR,
> the group (GRP0) has been placed, but all the
> primitives have been re-arranged (structure is
> lost). Has anyone got RPMs to work right?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 43268
Subject: Re: Need Help on FPGA and Spiking Neurons
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 May 2002 19:22:17 GMT
Links: << >>  << T >>  << A >>
At that relatively low rate, your best bet might be to make a smaller number
of Neuron processors in the FPGA.  YOu would probably associate each with a
block RAM to store the states of each of the neurons it processes.

rickman wrote:

> Traveler wrote:
> >
> > Hi,
> >
> > I am researching the suitability of FPGA technology for the real-time
> > simulation of spiking or pulsed neurons in a feedforward network. The
> > system I envision will have up to 200,000 neurons organized in several
> > specialized layers. At least one of the layers will use massive
> > recurrent feedback.
> >
> > The system must make it easy to attach an indefinite number of
> > synaptic (input and output) connections to a neuron, and to disconnect
> > them when necessary. Some of my neurons have as little as two inputs
> > while others may have hundreds of inputs. The efficacy of the
> > connections must be adjustable in real time. Good timing capability is
> > essential although not stringent. I need to resolve signal arrival
> > times to within 1 millisecond. I need to be able to add precise signal
> > delays to specific inputs. Thanks in advance for any relevant info.
> >
> > Nemesis
> >
> > Temporal Intelligence:
> > http://home1.gte.net/res02khr/AI/Temporal_Intelligence.htm
>
> FPGAs may be quite useful in your research efforts, but you have not
> defined the requirements in terms that a logic designer can use.  To
> evaluate the suitability of FPGAs for your research, your problem
> statement needs to use logical constructs like gates, counters, storage
> elements, etc.  To say that you need to implement neurons and synapses
> makes it hard to compare to the flip flops, gates and memory contained
> in an FPGA.
>
> But I think the key to your problem statement is your signal arrival
> timing of 1 milliSecond.  This is far slower than what can be done in
> logic (by about 10,000 to 100,000 times) and so you will most likely
> find that software will operate fast enough for your needs.  Simulating
> 200,000 neurons may exceed the capability of a single CPU, but a multi
> CPU system (say up to 10 CPUs or DSPs) will be much easier to design and
> program than an FPGA if you are not a logic designer.
>
> Although there is something to be said for implementing the problem in
> an FPGA.  An FPGA running at 10 to 100 MHz can simulate from 10,000 to
> 100,000 neurons in 1 mS in each instance of the neuron.  So obviously
> developing a large array of neurons in a single FPGA will not be a
> problem.  If the inter neuron connections need to be selectable, then
> you need to design in a level of programmable interconnect that may make
> the problem a bit more complex.
>
> The more I think about it, the more this sounds like a design of a
> cellular automata.
>
> But the trick to it all is to define what you need in terms of
> arithmetic or logic functions.  Can you do that, or will you need help?
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43269
Subject: Re: SDRAM pricing
From: "Matt H" <nospamyhensonator@yahoo.com>
Date: Fri, 17 May 2002 14:24:11 -0500
Links: << >>  << T >>  << A >>

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3CE54C57.E05567F8@yahoo.com...
> I am seeing the price of 256 Mbit SDRAM at about $20 to $25.  This is
> about 8 times what it costs for the same amount of memory on DIMMs.  I
> know that quantity makes a difference, but I can buy a single 256 MByte
> DIMM for $22 or I can buy 1k 32 MByte SDRAM chips at $20 each.  This
> seems very excessive.
>
> Anyone getting better pricing on 16x16 SDRAM?
>
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com

Hi Rick,
Check out this community:
http://www.dramexchange.com/default.asp
It looks like the current price for 16x16 is about $8.  Perhaps you can find
a better price.
Good Luck,
Matt




-----------== Posted via Newsgroups.Com - Uncensored Usenet News ==----------
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Article: 43270
Subject: Re: What properties has FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 May 2002 19:31:58 GMT
Links: << >>  << T >>  << A >>
I think you may have missed the idea of an FPGA altogether.  THe FPGA
is not inherently a processor, rather it is a regular array of
unconnected logic gates and flip-flops.  The 'program' (an
unfortunate term, since it leaves the connotation of being like a
microprocessor) sets the logic function of each logic cell (these are
typically a 16x1 look-up table memory and a flip-flop, the memory
allows you to program any boolean logic function of 4 inputs) and the
connections between the cells.  Designing an FPGA is digital hardware
design, which comes with all the concerns about
timing, clocks, concurrency and other considerations commonly
considered in hardware design but rarely considered in software.
Executing an FPGA design is not unlike any other chip design
except the chip function is determined at the time the bitstream is
loaded into the part rather than at the time of manufacture.  That
said, modern FPGA do have reasonable sized memories on chip,
free to be used in whatever way the hardware designer sees fit, and
provided the digital designer does a proper design, the design will be
causal.  You might read over some of the introductory
pages on the vendor websites (I realize these can be hard to find, the
vendors seem to assume everyone visiting the websites already knows
what an FPGA is).


Jan Ziak wrote:

> Hi. I would like to know what exact properties a programmable array
> has. More precissely, I want to know whether it allows to represent
> any algorithm, that is whether a programmable array includes:
>
> 1. causality (i.e. conditional execution in general)
> 2. stability (i.e. some sort of memory)
>
> I was searching for this information in the internet but have found
> nothing.
>
> I would like to know whether such PA exists.
>
> Thanks in advance.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43271
Subject: Re: virtex 2 block rams
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 May 2002 19:33:47 GMT
Links: << >>  << T >>  << A >>
No, there are no tristates on the BRAM outputs.  The enable is akin to a
clock enable, not a tristate enable.

shparekh@yahoo.com wrote:

> Hi,
>
> I am trying to convert bus widths.  One bus spans multiple block rams.
>  In other words while writing to brams, the data word is 96 bits - 3
> block rams.  While reading, the word is 32 bits i.e. 1 block ram at a
> time.  Therefore, while reading I need to access the three block rams
> for which I use lower order address bits to enable the block rams.  My
> question is if I take away the enable will the output port of the
> block ram be placed in tristate.  If so then on the read port I can
> simply bus the output data to all the block rams.
>
> I was trying to search for this information in the databook/handbook
> but no luck so far.
>
> I would appreciate some words of wisdom.
>
> -sanjay

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43272
Subject: Re: PCI Board Project
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Fri, 17 May 2002 14:42:41 -0500
Links: << >>  << T >>  << A >>
Another thing to consider is that Spartan-II is a lot faster than
XC4000XL.
It is a lot easier to meet 33MHz PCI's Tsu < 7ns with a Spartan-II.
Plus, Spartan-II has more LUTs than XC4000XL for the same amount of
money.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 43273
Subject: Re: PCI target with FPGA question
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Fri, 17 May 2002 14:50:49 -0500
Links: << >>  << T >>  << A >>
You can download a schematics of Insight Electronics Spartan-II
development board if you want to know how to hook up an external
Configuration PROM.

http://208.129.228.206/solutions/kits/xilinx/downloads/SpartanPCISchematics.PDF



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 43274
Subject: Re: SDRAM pricing
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 17 May 2002 17:22:12 -0400
Links: << >>  << T >>  << A >>
Matt H wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3CE54C57.E05567F8@yahoo.com...
> > I am seeing the price of 256 Mbit SDRAM at about $20 to $25.  This is
> > about 8 times what it costs for the same amount of memory on DIMMs.  I
> > know that quantity makes a difference, but I can buy a single 256 MByte
> > DIMM for $22 or I can buy 1k 32 MByte SDRAM chips at $20 each.  This
> > seems very excessive.
> >
> > Anyone getting better pricing on 16x16 SDRAM?
> >
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> 
> Hi Rick,
> Check out this community:
> http://www.dramexchange.com/default.asp
> It looks like the current price for 16x16 is about $8.  Perhaps you can find
> a better price.
> Good Luck,
> Matt

Interesting web site, but these prices are largely irrelevant.  None of
this is open to me to purchase.  Even after I register, I don't see a
way to buy.  I expect these prices are for very large orders.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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