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Hello all I have a reference design which uses a Lattice CPLD to implement some glue logic and I plan to use a Xilinx FPGA (which will have other functions) in my design. I have translated the .ldf netlist in VHDL but I don't know how to verify that it works as I expect (in fact I don't know what to expect). Does anyone know of an ldf simulator? -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 02 http://www.IPricot.com/Article: 43726
Thanks for all replies. Anyway, can I just set this timing constraints in Leonardo Spectrum? Actually I have tried to use it there, but I didn't notice a significant improvement. The stranger thing is I have synthesized and done place-and-route for my receiver with nice result (Quartus reported that the max freq was 137 MHz, I need 125 MHz). Then I switched to my transmitter, and it also went well. The problem arose when I swtiched back to my receiver (coz I forgot to put a shift register just for delaying purpose), but now it only achieved 100 MHz, though I used the same procedure as far as I can remember. With headache, Robert "Phil Connor" <philip_john_connor@hotmail.com> wrote in message news:5204909a9ebad1ce3e59a429d49d05f1.89140@mygate.mailgate.org... > "Robert O. Taniman" <bobchen74@yahoo.com> wrote in message > news:abjqkg$ck0$1@dinkel.civ.utwente.nl > > Hi Robert, > > A second thought.... > > Have you got some sort of timing constraint on the synthesis > in the UCF file. If you're new to FPGAs its possible to overlook > this requirement. > > Use something like... > > ####TIMING CONSTRAINTS ##### > NET "Clk" TNM_NET = "Clk"; > TIMESPEC "TS_Clk" = PERIOD "Clk" 50 MHz HIGH 50 %; > ############################ > > Naturally there are a mass of more complicated ways to put timing > constraints on the synthesis. These can be found in the literature. > > If you are nearly there with your current timing then simply do > multiple Place&Route with the constraints until the chip passes. > > If not follow the more radical Xilinx tips, previously referenced, to > speed it up, the biggest improvement being "reduce the number of > layers of logic". > > Any serious design needs to have all timing problems resolved. That is, > if it's only for your own use as an amusement then you could live with > the odd glitch, otherwise I'd fix it. > > Best regards > > Phil > > > > > > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 43727
Austin, Thanks for the reply. But I don't see how Hspice using IBIS files helps. Hspice is a licensed product and is not cheap. I was referring to Spice simulators being available as freeware. So it is not likely that the Spartan II chips will get spice models anytime soon? Austin Lesea wrote: > > Rick, > > The spice models are encrypted because they contain the foundry's > technology files (highly proprietary). > > A smart technologist can figure out exactly how a foundry is building > their transistors from examining the details of the technology models. > > We have encrypted spice models only for customers who sign NDAs, and > who have the latest Avant! Hspice. > > The IBIS models are developed from these spice models. > > The latest version of Hspice accepts IBIS models, so the need for > spice models has actually diminished. > > Virtex II ushered in a new age of high speed designs, and as such, an > effort was made to support such designs with better modeling > resources. > > Austin > > > rickman wrote: > > > Checking the Xilinx web site it looks like you can download IBIS > > models > > for various devices including the Spartan IIe devices. However, > > these > > files do you no good if you don't have IBIS simulator which seem to > > cost > > even more than a logic or HDL simulator. > > > > I also found that there are spice models available for the VirtexII > > parts. But not for any other devices. Since Spice is much more > > available, any idea why the Spice models are not available for parts > > > > other than the VII? > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the > > XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43728
Hi.
I'm working on an address generator for a DMA controller in FPGA.
To save logic resources, I want to use non-sequential addresses.
Instead, I want to use an LFSR.
The range is 512 byte, or 2^9. The great program "LFSR Testbench"
calculates a variety of possible solutons for this problem. However,
the silicon-efficient solutions have a cycle of (2^n)-1. I need
the whole 2^n to move all 512 bytes.
Since I am new to LFSRs, I checked the theory with pencil and
paper with a 2-bit LFSR. "LFSR Testbench" suggests:
feedback := LFSR(1) xor not(LFSR(0));
LFSR(0) <= feedback;
LFSR(1) <= LFSR(0) xor feedback;
My pencil & paper work suggests:
bit1 <= bit0;
bit0 <= not(bit1);
to count through 00,01,11,10. The latter solution uses less
logic gates, and more important: less WIDE logic inputs.
With 9 bits, LFSR Testbench suggests a solution with 8 inputs
in one logic equation. This kills FPGA logic area.
Is it possible to come up with a similar solution for 2^9 like
I did for 2^2? I ask because I don't want to spend 2 days
trying, when it's known to be impossible.
Marc
Article: 43729I use .ttf file and give additional ten clocks cycles after all bits were sent. Now I want to use .rbf file to try. if the .ttf file has some troubles?Article: 43730
Yes, I have given the additiional ten clock cycles, but the Configure_Done signal was never to High. "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<ad5ior$ue5ed$1@ID-84877.news.dfncis.de>... > "wuqiang" <wq00001@163.com> schrieb im Newsbeitrag > news:32ebf098.0205291650.25752ccf@posting.google.com... > > I use mcu 89c51 to PS configure Flex10k10. I have followed the timing > > in the altera pdf file, used the content of .ttf(Byte) file as > > unsigned char array. Now NStatus signal is ok, but Conf_Done is never > > to become hign to inform me to configure success. I check the board > > and program again, but no error is found. > > Who have finished similar work? > > Did you generate additional configuration clock cycles after all bits have > been loaded into the FPGA(4..6)? There are required to initiate the > startup-sequence.Article: 43731
Look for de Bruijn sequences. If all else (a.k.a. a search on the
Internet) fails, the book "Shift Register Sequences" by S. Golomb,
Holden-Day 1967; Aegean Press 198? discusses these in Chapter 6 .
--
.-. .-. .-. .-. .-. .-. .-.
/ D \ I / L \ I / P \ / S \ A / R \ W / A \ T / E \
`-' `-' `-' `-' `-' `-'
Article: 43732--------------2DDC8936630EA09CDC8B2AD0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Rick, I know exactly what you are referring to. Rather than just say, "nope" I took the opportunity to explain why the answer is what it is. And freeware versions do not support encrypted files. Sorry, we support Hspice for spice for a very good, and sound business reason. The hotline has Hspice licenses, and we can solve problems, and support customers this way (in addition to protecting our IP). We also have licenses for Cadence SpectraQuest (for the multi-gigbit transceivers), and HyperLynx. These are our recommended SI simulation tools, and are Xilinx partners. If you have a simple "what if" question, the hotline can do a simulation for you (commercial customers please! students are supported thru the Xilinx University program http://www.xilinx.com/univ/index.htm) and email you the results (similar to what I have done here on this board). Austin rickman wrote: > Austin, > > Thanks for the reply. But I don't see how Hspice using IBIS files > helps. Hspice is a licensed product and is not cheap. I was referring > to Spice simulators being available as freeware. > > So it is not likely that the Spartan II chips will get spice models > anytime soon? > > Austin Lesea wrote: > > > > Rick, > > > > The spice models are encrypted because they contain the foundry's > > technology files (highly proprietary). > > > > A smart technologist can figure out exactly how a foundry is building > > their transistors from examining the details of the technology models. > > > > We have encrypted spice models only for customers who sign NDAs, and > > who have the latest Avant! Hspice. > > > > The IBIS models are developed from these spice models. > > > > The latest version of Hspice accepts IBIS models, so the need for > > spice models has actually diminished. > > > > Virtex II ushered in a new age of high speed designs, and as such, an > > effort was made to support such designs with better modeling > > resources. > > > > Austin > > > > > > rickman wrote: > > > > > Checking the Xilinx web site it looks like you can download IBIS > > > models > > > for various devices including the Spartan IIe devices. However, > > > these > > > files do you no good if you don't have IBIS simulator which seem to > > > cost > > > even more than a logic or HDL simulator. > > > > > > I also found that there are spice models available for the VirtexII > > > parts. But not for any other devices. Since Spice is much more > > > available, any idea why the Spice models are not available for parts > > > > > > other than the VII? > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the > > > XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43733
Without losing data or inserting junk in your 100 MHz multiplexed stream, the 25 MHz has to be related to the 100 MHz in *some* fashion. If the relationship between these clocks allows good clk-to-out at 25 MHz relative to the setup and hold at 100 MHz, accounting for the skew and jitter between the two domains, everything works. If you don't know the relationship, only that they're phase locked, a short FIFO would be the cleanest implementation with a "half full" as the startup state so the FIFO doesn't over or under fill. Ken Mac wrote: > Hello folks, > > Recently I did a design (Xilinx Spartan-II) that required data to be passed > from a 33MHz domain to a 425kHz domain. > > I did this using an Asynchronous FIFO and all was well. > > Now for another design: > > If I have 4 registers being clocked at 25MHz (with data coming in on each > clock) and these 4 registers are to be multiplexed in turn into one register > at 100MHz (i.e. the MUX and storage register are being clocked at 100MHz), > do I need to worry about metastability? > > I would guess that I do, unless I used one of the CLKDLLs to divide the > 100MHz clock down by 4 to 25MHz (thus making the 25MHz synchronised to the > 100MHz in some way?) - would this ensure no metastabilty problems and allow > me to just wire up the MUX to the 4 registers without any intervening > Asynchronous FIFO or whatever? > > Thanks for your time, > > KenArticle: 43734
Hi Loi, The trick here is not to double-click on the net, and then try to name it. This will end up in the error you have seen. What you should do is to be in net naming mode, then type in a net name in the options box, and finally click on the net you want named. I hope this helps. Regards, Kamal Loi Tran wrote: > Hi, > > I'm working with WEBpack 4.1 and I was wondering if there is a way to work > with multiple schematics on same level sheets instead of hierarchy sub-level > format. Example, I want 2 separate sheets on the same level to have a common > signal line, and therefore a common net. I tried it and a query tells me > they're two different nets altogether. Please tell me if this can be done? > > Thanks > > LT > > For the Xilinx guys who've been helping me out, thank you very much. >Article: 43735
"jetmarc" <jetmarc@hotmail.com> schrieb im Newsbeitrag news:af3f5bb5.0205310606.49667136@posting.google.com... > Hi. > > I'm working on an address generator for a DMA controller in FPGA. > To save logic resources, I want to use non-sequential addresses. > Instead, I want to use an LFSR. > > The range is 512 byte, or 2^9. The great program "LFSR Testbench" > calculates a variety of possible solutons for this problem. However, > the silicon-efficient solutions have a cycle of (2^n)-1. I need > the whole 2^n to move all 512 bytes. I think there are two problems. 1.) You would like to save ressources. 2) You would like to find a special LFSR sequence. The second one is a nice brain teaser. So far my comment on this. For the first one, I dont think the problem (saving ressources) is worth the trouble. A 9 bit counter just takes 9 FlipFlops and a carry chain. Not much to save. Even in a CPLD (which dont have carry chain by now) you still need 9 macrocells. -- MfG FalkArticle: 43737
"Allan Herriman" <allan_herriman.hates.spam@agilent.com> schrieb im Newsbeitrag news:3cf6e314.346890862@netnews.agilent.com... > I still find synthesiser bugs even in purely synchronous designs. I > don't think gate level sims are going to go away any time soon. Yes, there are still synthesizer bug. But would you hunt down such a bug with a timing simulation of a full FPGA? I woudnt. Ray Andraka proposed to do post-mapping simulation to veryfy the sythesis result, since a post-maping is (much?) faster than post P&R. -- MfG FalkArticle: 43738
On Fri, 31 May 2002 14:36:23 GMT, Dilip V. Sarwate <sarwate@uiuc.edu> wrote, in part: >Look for de Bruijn sequences. If all else (a.k.a. a search on the >Internet) fails, the book "Shift Register Sequences" by S. Golomb, >Holden-Day 1967; Aegean Press 198? discusses these in Chapter 6 . Unfortunately, what a de Bruijn sequence does is it inserts an extra zero into a standard LFSR sequence by adding a 0 after the 000...0001 state is reached, and that requires a logic gate as wide as the shift register, which is exactly what the poster would like to avoid. But perhaps there is a simpler way to generate them. His example, with a NOT gate, strictly speaking is _not_ an LFSR; it is provably impossible to construct an LFSR of n stages with a period longer than 2^n-1 (specifically because the allowed operations in LFSRs are such that once it's loaded with all zeroes, it stays there forever). Of course, he could always use an LFSR with one extra cell, and only use the values in the other cell when that cell contained a 1. But that would be extremely inefficient, allowing only half the bandwidth to be used. John Savard http://home.ecn.ab.ca/~jsavard/index.htmlArticle: 43739
To implement a 9-bit LFSR for the DMA address generator, you need 9 register bits. To implement a 9-bit counter you need 9 register bits. No difference in logic resources from the flop standpoint. Since you need all 9 bits in parallel you can't use a Xilinx SRL16 primitive to help save resources. So... What device architecture are you working with such that the counter takes up more resources? Saving 8 LUTs in an FPGA (using the direct-in to the registers and leaving the LUTs for other combinatorial functions) doesn't seem like something to worry about. Efficiency is great but at what cost? jetmarc wrote: > Hi. > > I'm working on an address generator for a DMA controller in FPGA. > To save logic resources, I want to use non-sequential addresses. > Instead, I want to use an LFSR. > > The range is 512 byte, or 2^9. The great program "LFSR Testbench" > calculates a variety of possible solutons for this problem. However, > the silicon-efficient solutions have a cycle of (2^n)-1. I need > the whole 2^n to move all 512 bytes. > > Since I am new to LFSRs, I checked the theory with pencil and > paper with a 2-bit LFSR. "LFSR Testbench" suggests: > > feedback := LFSR(1) xor not(LFSR(0)); > LFSR(0) <= feedback; > LFSR(1) <= LFSR(0) xor feedback; > > My pencil & paper work suggests: > > bit1 <= bit0; > bit0 <= not(bit1); > > to count through 00,01,11,10. The latter solution uses less > logic gates, and more important: less WIDE logic inputs. > > With 9 bits, LFSR Testbench suggests a solution with 8 inputs > in one logic equation. This kills FPGA logic area. > > Is it possible to come up with a similar solution for 2^9 like > I did for 2^2? I ask because I don't want to spend 2 days > trying, when it's known to be impossible. > > MarcArticle: 43740
"Rajat Karol" <rajatkarol@softhome.net> wrote in message news:a78f7c6d.0205292217.78041f01@posting.google.com... > Hi, > > I wanted to know whether Xilinx or Altera provides engineering samples > for free? I got a sample CPLD (one of the little ones) from Altera. I don't think I requested it. I haven't got round to trying it yet, though. I might make a PCB for it at home. I don't think Xilinx or Altera give away samples of their larger chips on a routine basis, although I have got Altera samples from my Altera distributor in the past. > > Also whether there is any difference in function/ quality ( in terms > of perfomance or features or testability ) between engineering samples > and production samples. They should be identical, unless they are pre-production units. I've been caught out by this, before now. > > Also are engineering samples available at a lesser rate ?? Not generally. They often cost more, because of the small quantities. Generally, if you want free samples you are best off approaching your distributor and seeing if they can help, or a manufacturer's FAE, if you know one. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 43741
Can't Xilinx write a behavioral spice model that gives 99% accuracy? It does not have to be the 100% netlist version of the I/O cell just something someone can use to model the I/O pin and do some simulation. Xilinx should get used to putting out information and just saying "we don't support this but..." If someone wants to reverse engineer the part they can do it. That is no reason to withhold (or make expensive) information someone needs to do a proper design with Xilinx parts. I think there is some information that can be released and supported by the users at large. I just wish Xilinx would start to understand the difference between what they need to keep secret, what they can release that needs full support and information they can give out and not support. For example you have the bitstream specs for lookup tables, BRAMs and flops. But not routing. I can however get this information from the XDL tools but only at great expense in time. I guess I've just heard the "if we tell you we'll have to support you" or "if you know this your going to hurt yourself" lines a little too often. Steve "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3CF78DA1.8E0ECD98@xilinx.com... Rick, I know exactly what you are referring to. Rather than just say, "nope" I took the opportunity to explain why the answer is what it is. And freeware versions do not support encrypted files. Sorry, we support Hspice for spice for a very good, and sound business reason. The hotline has Hspice licenses, and we can solve problems, and support customers this way (in addition to protecting our IP). We also have licenses for Cadence SpectraQuest (for the multi-gigbit transceivers), and HyperLynx. These are our recommended SI simulation tools, and are Xilinx partners. If you have a simple "what if" question, the hotline can do a simulation for you (commercial customers please! students are supported thru the Xilinx University program http://www.xilinx.com/univ/index.htm) and email you the results (similar to what I have done here on this board). Austin rickman wrote: Austin, Thanks for the reply. But I don't see how Hspice using IBIS files helps. Hspice is a licensed product and is not cheap. I was referring to Spice simulators being available as freeware. So it is not likely that the Spartan II chips will get spice models anytime soon? Austin Lesea wrote: > > Rick, > > The spice models are encrypted because they contain the foundry's > technology files (highly proprietary). > > A smart technologist can figure out exactly how a foundry is building > their transistors from examining the details of the technology models. > > We have encrypted spice models only for customers who sign NDAs, and > who have the latest Avant! Hspice. > > The IBIS models are developed from these spice models. > > The latest version of Hspice accepts IBIS models, so the need for > spice models has actually diminished. > > Virtex II ushered in a new age of high speed designs, and as such, an > effort was made to support such designs with better modeling > resources. > > Austin > > > rickman wrote: > > > Checking the Xilinx web site it looks like you can download IBIS > > models > > for various devices including the Spartan IIe devices. However, > > these > > files do you no good if you don't have IBIS simulator which seem to > > cost > > even more than a logic or HDL simulator. > > > > I also found that there are spice models available for the VirtexII > > parts. But not for any other devices. Since Spice is much more > > available, any idea why the Spice models are not available for parts > > > > other than the VII? > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the > > XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43742
William Wallace wrote: > However, my experience based on a few simple experiments is that using > a single process based on transitions and clocks works as well > real-estate-wise, and is much more readable. This is with XST and > FPGAExpress synthesizers. > > Anybody have a different experience? No. Single process machines work fine. It's style issue. -- Mike TreselerArticle: 43743
"samlin" <gammalin@seed.net.tw> schrieb im Newsbeitrag news:ad8bp5$t07$1@news.seed.net.tw... > hi... > I have a problem... > if I use a delay in fpga... > How can I do? What kind of delay do you need? How much delay do you need? -- MfG FalkArticle: 43744
Steve, Sorry you feel this way. But as you well point out, keeping our hard earned IP confidential is only part of the issue. The other part is the support. Right now our support is 'world class'. It doesn't happen by accident. What you suggest would fragment resources, cause more customer issues. We are daily trying to make FPGAs a "pushbutton" experience for the average user. My holy grail is to reduce the ever more difficult signal integrity issues to something that is closer to the experience of the HDL to bitstream flow, and less something accomplished by "experts" with magic wands. There is no such thing as 'unsupported' documentation. Even these emails have led to support issues. If this philosophy (in part) helps create a market for Xilinx experts, who make a living from consulting in the (more) optimal use of the FPGAs, I would hardly lobby to have Xilinx put them out of business..... Austin Steve Casselman wrote: > Can't Xilinx write a behavioral spice model that gives 99% accuracy? It does > not have to be the 100% netlist version of the I/O cell just something > someone can use to model the I/O pin and do some simulation. Xilinx should > get used to putting out information and just saying "we don't support this > but..." If someone wants to reverse engineer the part they can do it. That > is no reason to withhold (or make expensive) information someone needs to do > a proper design with Xilinx parts. I think there is some information that > can be released and supported by the users at large. I just wish Xilinx > would start to understand the difference between what they need to keep > secret, what they can release that needs full support and information they > can give out and not support. For example you have the bitstream specs for > lookup tables, BRAMs and flops. But not routing. I can however get this > information from the XDL tools but only at great expense in time. I guess > I've just heard the "if we tell you we'll have to support you" or "if you > know this your going to hurt yourself" lines a little too often. > > Steve > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:3CF78DA1.8E0ECD98@xilinx.com... > Rick, > I know exactly what you are referring to. Rather than just say, "nope" I > took the opportunity to explain why the answer is what it is. > And freeware versions do not support encrypted files. > Sorry, we support Hspice for spice for a very good, and sound business > reason. The hotline has Hspice licenses, and we can solve problems, and > support customers this way (in addition to protecting our IP). We also have > licenses for Cadence SpectraQuest (for the multi-gigbit transceivers), and > HyperLynx. These are our recommended SI simulation tools, and are Xilinx > partners. > If you have a simple "what if" question, the hotline can do a simulation for > you (commercial customers please! students are supported thru the Xilinx > University program http://www.xilinx.com/univ/index.htm) and email you the > results (similar to what I have done here on this board). > Austin > > rickman wrote: > Austin, > Thanks for the reply. But I don't see how Hspice using IBIS files > helps. Hspice is a licensed product and is not cheap. I was referring > to Spice simulators being available as freeware. > So it is not likely that the Spartan II chips will get spice models > anytime soon? > Austin Lesea wrote: > > > > Rick, > > > > The spice models are encrypted because they contain the foundry's > > technology files (highly proprietary). > > > > A smart technologist can figure out exactly how a foundry is building > > their transistors from examining the details of the technology models. > > > > We have encrypted spice models only for customers who sign NDAs, and > > who have the latest Avant! Hspice. > > > > The IBIS models are developed from these spice models. > > > > The latest version of Hspice accepts IBIS models, so the need for > > spice models has actually diminished. > > > > Virtex II ushered in a new age of high speed designs, and as such, an > > effort was made to support such designs with better modeling > > resources. > > > > Austin > > > > > > rickman wrote: > > > > > Checking the Xilinx web site it looks like you can download IBIS > > > models > > > for various devices including the Spartan IIe devices. However, > > > these > > > files do you no good if you don't have IBIS simulator which seem to > > > cost > > > even more than a logic or HDL simulator. > > > > > > I also found that there are spice models available for the VirtexII > > > parts. But not for any other devices. Since Spice is much more > > > available, any idea why the Spice models are not available for parts > > > > > > other than the VII? > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the > > > XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > -- > Rick "rickman" Collins > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43745
Even the PCMCIA stuff doesn't do too well under NT.
rickman wrote:
> Instead of disabling it in the BIOS, why not make it removable with a
> slide in cartdrige or use a PCMCIA adapter? I guess with the slide in
> cartdrige you still have to take it out of the BIOS unless they provide
> software to automatically do that as with the the PCMCIA interfaces.
>
> Ray Andraka wrote:
> >
> > I currently do my backups onto a drive on another machine. The hard part is
> > remembering to do the copy. I don't trust one machine to hold the data
> > uncorrupted. I had a case a year or so ago where my raid card bellied up and took
> > out the data on the raid array. I am still concerned about a virus getting into the
> > network and wiping both, so I keep not-frequent-enough-backups of the accounting and
> > project files onto CDs. I've dabbled with tapes a couple of times, but frankly have
> > never had much success with them. I had attempted to use an IDE drive on my machine
> > which I did disk images too on a frequent basis, and intended to disable in the BIOS
> > except when doing the back-up. Good intention, but too inconvenient to keep it off
> > line.
> >
> > Nicholas Weaver wrote:
> >
> > > In article <3CEE74F0.1CC15C51@yahoo.com>,
> > > rickman <spamgoeshere4@yahoo.com> wrote:
> > > >Hal Murray wrote:
> > > >>
> > > >> >Agreed, The raid is in the current system for reliability. I've suffered 3
> > > >> >or 4 disk failures over the years and the time spent recovering from backups
> > > >> >is well worth the extra cost of having a raid system.
> > > >>
> > > >> Don't forget to back things up (somehow) anyway. RAID won't protect
> > > >> you from software/mushware/operator errors.
> > > >
> > > >Just to add my two cents worth. I use a manual disk mirror approach for
> > > >protection against HW, SW and "mushware" issues. The second HD is an
> > > >exact duplicate of the first and is updated on a regular basis. We do
> > > >this once a week, but the weak point in the system is the operator
> > > >reliability. If I forget, I have lost some of my protection.
> > > >
> > > >By not having automatic duplication, we have some protection against
> > > >accidentally deleted file and other issues from software installation
> > > >and such. If we decide the backup is eaiser to work with than the
> > > >messed up current drive, we swap the drives and copy the backup to the
> > > >old original.
> > > >
> > > >This has saved us in some situations where a software crash wiped out a
> > > >significant part of the OS, once when we were infected with a virus and
> > > >many times when we did something to a file that we regretted.
> > > >
> > > >So RAID may not be the best option if you have the discipline to do your
> > > >backups.
> > >
> > > My 2 cents worth:
> > >
> > > Retrospect. It is a wonderful mac backup tool, doing both full and
> > > incremental backups, both on the machine and to other client machines
> > > over the network. My dad has had it save his bacon on his production
> > > mac system many times: he uses both a nightly incremental backup of
> > > everything and a nightly copying of critical files onto other drives.
> > >
> > > They finally have a Windows version as well, which if it works half as
> > > good as the Mac version, makes it worth its weight in gold.
> > > --
> > > Nicholas C. Weaver nweaver@cs.berkeley.edu
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43746> Is it possible to come up with a similar solution for 2^9 like > I did for 2^2? I ask because I don't want to spend 2 days > trying, when it's known to be impossible. > > Marc A discussion of 2^N sequences is on page 181 of the HDL Chip Design book by Douglas J Smith. If you are on a tight budget, I once saw someone reading this book at Barnes and Nobles if you get my drift. NewmanArticle: 43747
On Fri, 31 May 2002 20:13:57 +0200, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: >> I have a problem... >> if I use a delay in fpga... >> How can I do? > >What kind of delay do you need? How much delay do you need? not much... just a couple of days...Article: 43748
First I want to say I really like most of the people I meet at Xilinx but as the systems you try and field become more complicated your going to need to give up more information or grind to a halt. I look at it as a lack of over all confidence in the ablities of your users. It reminds of Clive whats his name form Altera who stood up and said "we make our tools for morons because morons use our tools." I've had this talk with lots of people and it is like your trying to make a pushbutton automobile. Imagine a car with only one button and all the software is written by microsoft but they won't tell anyone how it works or how to fix it when it breaks... I had to laugh when a high ranking Xilinx exec said "we are proud to have the best place and route for our parts in the industry." Last time a company "broke the code" they came up with a place and route tool 10x better than the Xilinx in house tool. The Xilinx president at the time bought the company and was eventually fired for it. But it was this tool devloped outside of Xilinx that gave Xilinx a big jump over Altera. It is like this I/O issue you don't give up anything by making a behavioral spice model for the I/Os. You know it's not that I dislike anyone or am mad I just feel like Richard Stallman sometimes, just give me the code and I'll fix my own problem. Ever think about open sourcing the code for your EDA tools. What do you have 500 software engineers? Open source your tools and you'll have 5000 engineers working for you and you don't have to pay them. Just do it like Sun did with Java. Anyone who wants to steal your IP can do it anyway. I think just the little stuff you've done so far has been good. Look at XDL that is great stuff. The docs on that have not been changed since the 4000 series. And of course the advanced user guide for Virtex. The guy who first wrote that up almost got fired for it. So here is what I think. The company that starts to make it easy for other companies to create tools for it's parts will be the winner. If Altera or Xilinx would publish everything people would use that information to make better tools. Yes the FPGA company might loose 2% in EDA sales but I think they would make this up in part sales by expanding their market into areas where they don't have the man power to address issues. Have a great weekend!! Steve "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3CF7C469.98890A30@xilinx.com... > Steve, > > Sorry you feel this way. > > But as you well point out, keeping our hard earned IP confidential is only part > of the issue. The other part is the support. > > Right now our support is 'world class'. It doesn't happen by accident. What > you suggest would fragment resources, cause more customer issues. > > We are daily trying to make FPGAs a "pushbutton" experience for the average > user. My holy grail is to reduce the ever more difficult signal integrity > issues to something that is closer to the experience of the HDL to bitstream > flow, and less something accomplished by "experts" with magic wands. > > There is no such thing as 'unsupported' documentation. Even these emails have > led to support issues. > > If this philosophy (in part) helps create a market for Xilinx experts, who make > a living from consulting in the (more) optimal use of the FPGAs, I would hardly > lobby to have Xilinx put them out of business..... > > Austin > > > Steve Casselman wrote: > > > Can't Xilinx write a behavioral spice model that gives 99% accuracy? It does > > not have to be the 100% netlist version of the I/O cell just something > > someone can use to model the I/O pin and do some simulation. Xilinx should > > get used to putting out information and just saying "we don't support this > > but..." If someone wants to reverse engineer the part they can do it. That > > is no reason to withhold (or make expensive) information someone needs to do > > a proper design with Xilinx parts. I think there is some information that > > can be released and supported by the users at large. I just wish Xilinx > > would start to understand the difference between what they need to keep > > secret, what they can release that needs full support and information they > > can give out and not support. For example you have the bitstream specs for > > lookup tables, BRAMs and flops. But not routing. I can however get this > > information from the XDL tools but only at great expense in time. I guess > > I've just heard the "if we tell you we'll have to support you" or "if you > > know this your going to hurt yourself" lines a little too often. > > > > Steve > > > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > > news:3CF78DA1.8E0ECD98@xilinx.com... > > Rick, > > I know exactly what you are referring to. Rather than just say, "nope" I > > took the opportunity to explain why the answer is what it is. > > And freeware versions do not support encrypted files. > > Sorry, we support Hspice for spice for a very good, and sound business > > reason. The hotline has Hspice licenses, and we can solve problems, and > > support customers this way (in addition to protecting our IP). We also have > > licenses for Cadence SpectraQuest (for the multi-gigbit transceivers), and > > HyperLynx. These are our recommended SI simulation tools, and are Xilinx > > partners. > > If you have a simple "what if" question, the hotline can do a simulation for > > you (commercial customers please! students are supported thru the Xilinx > > University program http://www.xilinx.com/univ/index.htm) and email you the > > results (similar to what I have done here on this board). > > Austin > > > > rickman wrote: > > Austin, > > Thanks for the reply. But I don't see how Hspice using IBIS files > > helps. Hspice is a licensed product and is not cheap. I was referring > > to Spice simulators being available as freeware. > > So it is not likely that the Spartan II chips will get spice models > > anytime soon? > > Austin Lesea wrote: > > > > > > Rick, > > > > > > The spice models are encrypted because they contain the foundry's > > > technology files (highly proprietary). > > > > > > A smart technologist can figure out exactly how a foundry is building > > > their transistors from examining the details of the technology models. > > > > > > We have encrypted spice models only for customers who sign NDAs, and > > > who have the latest Avant! Hspice. > > > > > > The IBIS models are developed from these spice models. > > > > > > The latest version of Hspice accepts IBIS models, so the need for > > > spice models has actually diminished. > > > > > > Virtex II ushered in a new age of high speed designs, and as such, an > > > effort was made to support such designs with better modeling > > > resources. > > > > > > Austin > > > > > > > > > rickman wrote: > > > > > > > Checking the Xilinx web site it looks like you can download IBIS > > > > models > > > > for various devices including the Spartan IIe devices. However, > > > > these > > > > files do you no good if you don't have IBIS simulator which seem to > > > > cost > > > > even more than a logic or HDL simulator. > > > > > > > > I also found that there are spice models available for the VirtexII > > > > parts. But not for any other devices. Since Spice is much more > > > > available, any idea why the Spice models are not available for parts > > > > > > > > other than the VII? > > > > > > > > -- > > > > > > > > Rick "rickman" Collins > > > > > > > > rick.collins@XYarius.com > > > > Ignore the reply address. To email me use the above address with the > > > > XY > > > > removed. > > > > > > > > Arius - A Signal Processing Solutions Company > > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > > 4 King Ave 301-682-7772 Voice > > > > Frederick, MD 21701-3110 301-682-7666 FAX > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX >Article: 43749
Have not been following this thread, but I think vII numbering in general makes more sense, complete pain in rear before. my 2 euros Mike <Martin> wrote in message news:ee76d2b.0@WebX.sUN8CHnE... > Hi Marcus, > > tzhe first idea here that comes to my mind is the difference for the numbering in Virtex-II compared to Virtex. > In the 'old' Virtex architechture you started in the top left corner and counted down and to the right in rows and columns. Now in the V-II architecture you start in the bottom-left corner and count in a kind of x-y-diagram to the right and upwards. > > Check if you still have the old syntax. Previously the syntax would have been something like ...RxCy.S0. > This must be now something like ...XaYb. > > My 2 Euro-Cent. > > Martin
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