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Messages from 43675

Article: 43675
Subject: place and route simulation time
From: nagaraj@accord-soft.com (Nagaraj)
Date: 29 May 2002 04:52:33 -0700
Links: << >>  << T >>  << A >>
Hi all,
   I have a design in vhdl (targeted at xilinx 300k virtex device).
The post place and route simulation is taking lot of time (several
days for 1ms worth simulation). I am using ModelSim simulator.
  Any suggestions to reduce the time taken for simulation?

regards,
CS

Article: 43676
Subject: Re: Frequency synthesiser
From: John_H <johnhandwork@mail.com>
Date: Wed, 29 May 2002 06:37:43 -0700
Links: << >>  << T >>  << A >>
Apologies, my jitter amplitude values are WRONG unless my memory
produced the right equations (doubtful) but my example of 55/128 is
completely wrong.  I do stand by the jitter frequencies from the "beat
frequency generator."

The phase error function needed for time domain analysis and for input
to the FFT is not the raw phase accumulator value.  Not at all.  I
should have noticed the phase difference value of 18 I got graphically
for the third beat wasn't the "master clock over two" or 27.5 that I
suggested should be the numerical value.

In a PLL system, the phase error is the difference between the "ideal"
clock and the Fractional-N sequence we're producing with this DDFS. 
What I used in the example - the raw phase accumulator value - isn't the
equivalent of this phase error, it's the difference between the ideal
value and the MSB edge that are important.  In the example, there should
be 55 clock intervals examined (56 end points) with the error as the
difference between the integer MSB edge and a 128/55 clock cycle
"ideal."

I'll revisit my mistake this evening and try to reproduce my original
work, checking my numbers this time.

I shouldn't jump the gun.

Article: 43677
Subject: Re: place and route simulation time
From: Utku Ozcan <utku.ozcan@netas.com.tr>
Date: Wed, 29 May 2002 17:04:23 +0300
Links: << >>  << T >>  << A >>
Nagaraj wrote:

> Hi all,
>    I have a design in vhdl (targeted at xilinx 300k virtex device).
> The post place and route simulation is taking lot of time (several
> days for 1ms worth simulation). I am using ModelSim simulator.
>   Any suggestions to reduce the time taken for simulation?

Some tips:

1. vector simulation. Generate testvectors from simulation models
and save them. Now run the simulation the vectors.

2. If you working on a UNIX platform, generate libraries, simulation
databases on the local harddisk, rather than on the network drive.
This will reduce interactions of HDL simulator with network filesystem.

3. Use a machine-code compiled simulator like Cadence NC-Sim.

> regards,
> CS

Utku



Article: 43678
Subject: Re: Frequency synthesiser
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 29 May 2002 07:46:53 -0700
Links: << >>  << T >>  << A >>
Luis,

Upconversion is a good way to see the close in products.

Excellent work, thank you for sharing this with the group.

I also would like to get a hold of that excel spreadsheet from John once he has
the maths right.......

The diminishing power of close in sidebands is interesting, and the telecom
system I had was a Stratum 1 GPS/Rubidium clock source (redundant).  This system
also had built in phase measurement, so we could monitor and collect statistics
(including raw phase).

The longest we ever ran the system to compare and collect information was 63
days undistrubed.  It was monitoring a free running rubidium source, a cesium
source, and a third GPS receiver source.  There was absolutely no evidence of
any phase jumps at any time during the 63 days.  On other occasions, the test
was run for month long periods as many as six times in a row.

Unfortunately, the company I worked for had the worst luck:  the roof developed
a leak, and water poured into the setup (twice!), the UPS system failed (twice),
the battery fuse blew out (once), and the collecting data logging computer
crashed (five times).

Splicing all of the data together did allow for almost a year's worth of data,
which was sufficient to "prove" the system was more accurate and stable than any
of the references we were comparing it against.

We would routinely send the system out to be tested by customers, and have the
customer send us the phase plots vs. their cesium standards.  I don't know how
many times I had to show that we had just calibrated their cesium clock for
free.  Cesiums are interesting, like a drunk, they can always find the bar (they
are accurate to 1E-12), but they wander all over the place trying to get there.
Rubidiums are absolutely wonderful for short term stability, but they are blind,
and don't know where they are going (ie they age).  Hydrogen Masers are
extremely accurate and have excellent short term stability, but their
frequencies are all slightly different.

Sigh.

Austin

Luis Cupido wrote:

> Hello,
>
> ...  >> I have no answers, just what the spectrum analyzer and wander
> analysis shows.
> > <paste>
>
> Yes certainly quite hard to measure, if not impossible in some cases.
>
> However I've seen this effect quite clearly while using a DDS as reference
> for a
> pll locking a millimeter wave oscillator in the 92GHz range.
> The dds (24bits,100MHz  ck) at about 20MHz output was mutiplied
> by 4608 (that is 256 times in a pll to 5.12GHz and 2 times in a doubler and
> 9 times in the
> mmW PLL harmonic mixer) (the aprox 6Hz step translates to about 28Khz at the
> output)
> We could observe a wobling spanning about 30KHz mooving slowly, and
> dependent on the N input
> of the DDS. Need to mention that the phase noise of the 92GHz oscillator
> itself was in the
> range of 50KHz+ and obviously this effect had no impact on the application,
> even if the wobling
> were 10 times worst wouldn't be a problem. It was found by accident by
> noticing a strange up
> and down on the frequency counter periodically.
>
> But it was funny to confirm theory.
>
> Luis Cupido.
>
> P.S. all things were using a unique 10MHz reference, including the freq.
> counter.


Article: 43679
Subject: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
From: "Michael Rhotert" <mrhotert@yahoo.com>
Date: Wed, 29 May 2002 17:33:27 +0200
Links: << >>  << T >>  << A >>
Kevin Brace wrote:

<snip>
> However, Xilinx is really mean (unreasonable), and if you will try to
> synthesize a design from ISE's GUI, it will change the -ofmt option back
> to NGC.
> To avoid that, you will have to run XST from a batch file (.BAT file in
> DOS) from your project's directory.
> In case someone is not too familiar to run XST from a command line, the
> batch file will look like this,
>
> xst -ifn (Your Project).xst -ofn (Your Project).syr
>
>
> This way, ISE cannot manipulate the .xst file, so XST will generate an
> EDIF netlist.

<snip>

There's also a way to do this from ISE's GUI:
Select   Edit - Preferences - Processes  and set "Process Settings" to
"Advanced".
Now there is a new property in the Synthesis Options called "Other XST
Command Line Options".
Enter "-ofmt EDIF" (without quotes) as the value.
If you synthesize your design, XST now generates both, EDIF and NGC
netlists.

/Michael




Article: 43680
Subject: Re: Rounding Accumulator
From: "Steve Casselman" <sc@vcc.com>
Date: Wed, 29 May 2002 16:14:24 GMT
Links: << >>  << T >>  << A >>
Stick the lsb to a '1' if you underflow. This is call von Neumann rounding.
The idea is you'll be right 1/2 the time. This is not true if you stick to a
zero (then its like  you don't have the bit at all).

Steve

"Pete Dudley" <pete.dudley@comcast.net> wrote in message
news:fZSF8.184433$M7.19063100@bin7.nnrp.aus1.giganews.com...
> Hello
>
> I have an distributed arithmetic design that uses a scaling accumulator.
The
> Xilinx core generator produces an accumulator that shifts right by one bit
> before feeding back into the adder to affect a divide by two. In the
process
> the lsb is simply thrown away.
>
> My application is sensitive to truncation errors. Is there a simple way to
> use the carry_in pin of the accumulator to implement a round instead of a
> truncation in the shifted feedback data? The input and output data of the
> accumlator is signed two's complement.
>
> --
> Pete Dudley
>
> Arroyo Grande Systems
>
>
>



Article: 43681
Subject: Re: Addressable shift register
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 29 May 2002 09:18:35 -0700
Links: << >>  << T >>  << A >>
John Williams wrote:

> I guess I'm still in some ways trying to map
> conventional languages (C,C++, Matlab etc) onto VHDL... 


You can do this for the main process of a simulation testbench.

Synthesis does seem a little backwards at first.

  -- Mike Treseler




Article: 43682
Subject: Re: JTAG ICE or programmer
From: "Steve Casselman" <sc_no_spam@vcc.com>
Date: Wed, 29 May 2002 16:26:34 GMT
Links: << >>  << T >>  << A >>
You can use our HOTMan product ($65) but you'll have to do a little
programming. You can use any of the Jtag download cables. There is a Jtag
example that uses the Xilinx download cable. You can download a free
evaluation copy to see if it is right for you from www.vcc.com

Steve


"Laurent Gauch" <laurent.gauch@amontec.com> wrote in message
news:3CEE6134.4000507@amontec.com...
> That will be not very easy to write the same software to programm Xilinx
> and Altera FPGAs and Atmel AVRs. That's the job of www.jtag.com . Price
> about $30K for the jtag software, but I know why!
> Same hardware is possible using the universal POD called Chameleon POD
> http:\\www.amontec.com\chameleon.shtml
>
> Laurent
>
> Frank Scherler wrote:
>
> > Hello
> >
> > I am looking for a JTAG ICE. I don't wanne spend much money on it.
> > I want to be able to have a look on the schematics and to be able to
> > compile the software on my own. I am looking for hardware to programm
> > Xilinx and Altera FPGAs and Atmel AVRs with one Software and one
> > hardware. If it would be possible to debug software over JTAG with
> > this hardware it would be great. Dose anyone know any Project with
> > this topic?
> >
> > regards
> > Frank
> >
>
>



Article: 43683
Subject: Re: Xilinx proprietary format?
From: "Steve Casselman" <sc_no_spam@vcc.com>
Date: Wed, 29 May 2002 16:47:07 GMT
Links: << >>  << T >>  << A >>
XDL is a one-to-one translation of the ncd. By that I mean if you do
ncd->xdl->ncd you get your design back. In fact using the XDL report you can
get everything you need to reverse engineer the bitsteam. So software wise
Xilinx has released enough information to say program up a set of tools if
someone wants to do this.  Basically XDL report gives out all the tile and
pip information. You use this to build a repersentation of the device. Then
read in the design information and over lay this on the device information.


Steve


"Kevin Neilson" <kevin-neilson@removethistextattbi.com> wrote in message
news:JnbH8.94598$Po6.189187@rwcrnsc52.ops.asp.att.net...
> If Xilinx releases too much infomation, it would be easier for another
> company to make a gate array or clone FPGA that could use the same bit
file.
>
> "Jeff" <jeff@Despammed_Domain.com> wrote in message
> news:b862d891.0205231110.2da2e57f@posting.google.com...
> > Hi,
> >
> > I'm somewhat new to the newsgroup and this may be an old topic, but
> > why is it that Xilinx keeps the format of its .ncd files a secret?
> > This seems a bit strange to me since Xilinx offers a tool (XDL) which
> > translates the NCD file to an ASCII file in XDL format, which is not
> > proprietary (though documentation for XDL isn't easily found).
>
>
>



Article: 43684
Subject: DCM partial reconfiguration
From: <s>
Date: Wed, 29 May 2002 18:57:27 +0200
Links: << >>  << T >>  << A >>
Hello,

I have tried to make a two-configuration solution with two different
settings for my DCM (Virtex-II). The first configuration sets CLKFX_MULTIPLY
= 13 and CLKFX_DIVIDE = 12. The other configuration sets CLKFX_MULTIPLY = 9
and CLKFX_DIVIDE = 5. First I generate a bitfile, then I change the values
using the FPGA editor and run the bitgen command: bitgen -g
ActiveReconfig:Yes -r first_config.bit second_config.ncd
The difference is 62 frames. I was thinking about storing the configuration
in BlockRAM, but 62 frames is too much. Is there a chance of decreasing the
amount of frames stored in BlockRAM. I am using sets ISE 4.2 SP2.

Thanks in advance
Stein



Article: 43685
Subject: Re: Xilinx proprietary format?
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Wed, 29 May 2002 17:00:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <fC7J8.9299$v81.347158736@newssvr21.news.prodigy.com>,
Steve Casselman <sc_no_spam@vcc.com> wrote:
>XDL is a one-to-one translation of the ncd. By that I mean if you do
>ncd->xdl->ncd you get your design back. In fact using the XDL report you can
>get everything you need to reverse engineer the bitsteam. So software wise
>Xilinx has released enough information to say program up a set of tools if
>someone wants to do this.  Basically XDL report gives out all the tile and
>pip information. You use this to build a repersentation of the device. Then
>read in the design information and over lay this on the device information.

Note however that ncd->xdl->ncd works fine for the normal flow, it
does break the backannotation path in Version 4.1, at least when done
between mapping and P&R.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 43686
Subject: Re: Xilinx Foundation schematic multi-sheet problem.
From: hess@cs.indiana.edu (Caleb Hess)
Date: Wed, 29 May 2002 17:11:23 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3CF4AB92.7080702@wp.pl>, Daniel Han'czewski  <danhan@wp.pl> wrote:
>Dear all,
>
>I have to make some changes in an old project created in Foundation 2.1i 
>schematic editor and it consists of four schematic sheets (no hierachy - 
>just flat model). A "connect-by-name" feature allows me to connect nets 
>with the same name although they exist on different sheets. That works 
>fine. But I can't see it working for buses. Two buses with the same name 
>placed on two sheets are not connected! How can I solve this problem?
>
>Thanks in advance
>Daniel
>

In the Foundation schematic editor, buses are just a graphic aid to
human readability. The signals within the bus are dealt with individually
with names that are structured as <bus_name><bit_number>. To get buses
connected across non-hierarchical sheet boundaries you will have to break
out and name the individual signals in each bus, on each sheet. Bus signals 
are only connected automatically across hierarchical levels, where there
is a mapping from bussAsignalname to instance/bussBsignalname. Even within a
sheet, connect-by-name to an individual bus signal doesn't work until
you put in a bus tap that names that bit.

Seems like an oversight, but I just verified that it still works that way
in Foundation 3.1i.
-- 
Caleb Hess						hess@cs.indiana.edu


Article: 43687
Subject: virtex 2 : DCM divided clock
From: eyals@hywire.com (Eyal Shachrai)
Date: 29 May 2002 10:17:18 -0700
Links: << >>  << T >>  << A >>
1. is there apossibility to use the same DCM to synthisize two divided clocks?
2. will it be wise to divide a 125 MHz clock in 16 ?

Article: 43688
Subject: Re: ALtera SOPC Builder
From: 9+3@supereva.it (Fabio G.)
Date: Wed, 29 May 2002 17:43:52 GMT
Links: << >>  << T >>  << A >>
Prager Roman <rprager@frequentis.com> ha scritto:

>I use the NIOS core,

I have the Nios developement board, do you?

>One of my biggest problems is that the NIOS core consumes too much space in the
>FPGA

The Apex in the board has 8320 LCs.
How many LCs does the Nios consume?

>However, I think the idea of the SOPC- builder is really great. It is quite
>easy to implement a working system within very short time. 

I'm doing the synthetizable version of  a RISC processor: 
http://xirisc.deis.unibo.it
It is a reconfigurable processor for high performance embedded system:
something similar (but better) to Nios: it has a built in FGPA... so
it's FPGA^2 !! (actual, on Altera I've implemented a smaller version of
the FPGA  than the one on the sylicon version).

I have to implement my processor in the FPGA but I want that when I shut
down the board, the configuration is not lost.
Do you know how to download the configuration info into the FlashRAM of
the Nios development board? 

Bye!

--
Per rispondermi via email sostituisci il risultato
dell'operazione (in lettere) dall'indirizzo.

Article: 43689
Subject: Re: Frequency synthesiser
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 29 May 2002 19:49:28 +0200
Links: << >>  << T >>  << A >>
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag
news:3CF3F43D.949429AF@mail.com...
> "Not true at all."
>
> Could you elaborate on what's not true rather than dismissing my comments
in
> whole?
> 1)  I thought the classic DDS was more than just a Phase Accumulator
>      and included the (co)sine lookup tables for driving a DAC to get a
>      true sinusoid.

Yes, no argument.

> 2)  Using just the MSB of the phase accumulator or the MSB of the
>      phase-to-sine lookup, the jitter is [a maximum of] the master clock
>      period.  [I realize it will be zero in subharmonic cases, thanks]

Dito.

> 3)  If you actually use a DAC to generate the sinusoid - not the phase
>      ramp - then you just need to do a good job of filtering so the
aliased
>      sinusoids don't get into your baseband signal, creating jitter.

Thats the point I was critizizing.

> If you have a sinusoidal DDS with a filtered DAC output there is no jitter
even
> for "a setting very close to on of the "perfect" increments (when the
increment
> is a power of 2)."  You absolutely have jitter you cannot filter out if
you

This is not true I think. Iam not sure.Maybe Iam on the wrong track, since
the paper I mentioned, is trying to develop a DDS without a DAC, and so
things may be a little bit different.

> only use the MSB.  In the case of the DDS with a filtered DAC your system
noise
> is limited by the phase word resolution in the phase to sine lookup, the
noise
> in the DAC, and the aliased frequencies that weren't filtered out in the
analog
> sinusoid.

Yes, with this I can agree.

> My DDS background came from the development of a jitter generation test
> equipment design for telecom testing with very stringent inherent jitter
> requirements.

I did develop jitter measurement device etc. and Iam also far away from
beeing a DDS guru.
Just my two (EURO) cents.
;-)

--
Regards
Falk




Article: 43690
Subject: Re: State machine synthesis
From: sandeep@wrs.com (sandeep)
Date: 29 May 2002 10:51:46 -0700
Links: << >>  << T >>  << A >>
> The problem seems like it is an XST's bug, but eventually I found a
> workaround by changing a synthesis option, and the problem disappeared
> in both versions of XST.

Hi Kevin,

What option did you have to change ? I use WebPack ISE and have similar
problem. I cannot do a Post-Synthesis simulation of state machines, 
although the state machines work perfectly in actual hardware. 

Sandeep

Article: 43691
Subject: Re: DCM partial reconfiguration
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 29 May 2002 11:40:53 -0700
Links: << >>  << T >>  << A >>
S,

You should have only one frame different.  You are doing something wrong to get
this result.

Compare the two designs.

If you did a bitgen on the two designs separately in the .rbt file format,
(ascii 1's and 0's), and do a 'diff' on the two files, there should only be the
M and D values that are different (as well as the checksum).

If they are different, then something else is changing between the two designs.

To be sure nothing changes, you may use FPGE_Editor to change the M and D values
to get the different .ncd files.

Austin

s wrote:

> Hello,
>
> I have tried to make a two-configuration solution with two different
> settings for my DCM (Virtex-II). The first configuration sets CLKFX_MULTIPLY
> = 13 and CLKFX_DIVIDE = 12. The other configuration sets CLKFX_MULTIPLY = 9
> and CLKFX_DIVIDE = 5. First I generate a bitfile, then I change the values
> using the FPGA editor and run the bitgen command: bitgen -g
> ActiveReconfig:Yes -r first_config.bit second_config.ncd
> The difference is 62 frames. I was thinking about storing the configuration
> in BlockRAM, but 62 frames is too much. Is there a chance of decreasing the
> amount of frames stored in BlockRAM. I am using sets ISE 4.2 SP2.
>
> Thanks in advance
> Stein


Article: 43692
Subject: Re: place and route simulation time
From: newman5382@aol.com (newman)
Date: 29 May 2002 11:54:21 -0700
Links: << >>  << T >>  << A >>
nagaraj@accord-soft.com (Nagaraj) wrote in message news:<9c782518.0205290352.417edae5@posting.google.com>...
> Hi all,
>    I have a design in vhdl (targeted at xilinx 300k virtex device).
> The post place and route simulation is taking lot of time (several
> days for 1ms worth simulation). I am using ModelSim simulator.
>   Any suggestions to reduce the time taken for simulation?
> 
> regards,
> CS

CS,

What Modelsim are you using?  PE, SE, XE?  I've heard that if you use
the XE version, you should use the precompiled Xilinx libraries for
the simulation.  Have not heard if the precompiled libraries help with
the PE or SE version.

How is your memory situation? If you run short, virtual memory will
slow you down alot.  I've heard SE os maybe twice as fast as PE, and
PE maybe 2X faster than XE.

I've run PE gate level simulations with a dual 800 MHz Pentium III
with 1 Gig of memory with a Virtex 1000E target at 60% fill, and it
ran about 26 mS of simulations is a couple of hours.  The machine only
used one processor to run the simulation.  Your simulation time
appears to be on the high side, but mileage may vary.

Newman

Article: 43693
Subject: Re: Frequency synthesiser
From: John_H <johnhandwork@mail.com>
Date: Wed, 29 May 2002 19:02:01 GMT
Links: << >>  << T >>  << A >>
Thanks for the clarification, Falk.  A DDS without a DAC will absolutely give
the jitter you mentioned for all but the N exact submultiples of a 2^N phase
accumulator.  If a scheme used an arbitrary modulus phase accumulator, there are
more submultiples (or at least different ones) that could produce zero jitter in
the raw MSbit DDFS output.

The Analog Devices data sheets for their integrated DDS products do an excellent
job of characterizing the spectral output of their devices.  It's the fine
addressability of the spectrally pure sinusoid that allows the zero crossing of
the filtered output to be so precisely placed in time.  The DAC based DDS will
provide superb results as long as the filtering is done well.  Looking at the
raw unfiltered output of a DDS DAC, a scope trace will give you a beautiful
stairstep when the higher frequency components are in place.  When filtered, the
sinewave is pure.


Falk Brunner wrote:

> "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag
> news:3CF3F43D.949429AF@mail.com...
> > 3)  If you actually use a DAC to generate the sinusoid - not the phase
> >      ramp - then you just need to do a good job of filtering so the aliased
> >      sinusoids don't get into your baseband signal, creating jitter.
>
> Thats the point I was critizizing.
>
> > If you have a sinusoidal DDS with a filtered DAC output there is no jitter
> even
> > for "a setting very close to on of the "perfect" increments (when the
> increment
> > is a power of 2)."  You absolutely have jitter you cannot filter out if you
>
> This is not true I think. Iam not sure.Maybe Iam on the wrong track, since
> the paper I mentioned, is trying to develop a DDS without a DAC, and so
> things may be a little bit different.


Article: 43694
Subject: Re: place and route simulation time
From: jeff@mock.com (Jeff Mock)
Date: 29 May 2002 13:47:44 -0700
Links: << >>  << T >>  << A >>
Modelsim is a toy, especially when it comes to doing gate
level simulation of any reasonable size.

The big guys are all fine, but I like finsim from
Fintronic.  It's cheap, it runs on Linux, I've never
been able to break it, and it's really fast.  I'm sure
it would do fine on your virtex gate level sim.

jeff


Utku Ozcan <utku.ozcan@netas.com.tr> wrote in message news:<3CF4DFE7.617A5616@netas.com.tr>...
> 
> 3. Use a machine-code compiled simulator like Cadence NC-Sim.
> 
> > regards,
> > CS
> 
> Utku

Article: 43695
Subject: Re: How can I create an encrypted netlist for Altera?
From: Joe <xxx@yyy.com>
Date: Wed, 29 May 2002 23:13:00 +0100
Links: << >>  << T >>  << A >>


Kevin Brace wrote:

> Petter Gustad wrote:
> >
> >
> >
> > Is the NGD file actually encrypted? I thought it was only an
> > undocumented binary format?
> >
>
>         Actually, NGO is the file format (Native Design Object) in
> question.
> Okay, NGO is not actually encrypted (Yes, I was able to see LUT and FF
> names of my design when I opened it yesterday . . . ), but the format is
> proprietary.
> To me, that's adequate.
>
> > I've just used Synopsys FPGA Compiler II to create an EDIF netlist
> > which was read into Quartus II (I like the TCL support). An immediate
> > EQN file is created which is neither binary or encrypted, but I would
> > describe it as "obfuscated".
> >
>
>         Yes, I already knew that a .EQN does display the LUT equations,
> but I don't believe it is a proprietary netlist format I am looking for.
>
> > Would it be possible for you to distribute your core with the Altera
> > IP core program? There must already be a mechanism to protect your
>  > IP.
>
>         I am not interested in joining such a distribution program.
>
> > I know that you can download and simulate some of the IP's. Other's
> > like the Altera PCI core you can even upload to a device, but it will
> > only operate for two days or so. That's what I call try before you
> > buy.
> >
> > Petter
> > --
> >
>
>         Yes, I am aware that Altera encrypts their IP cores.
> It looks like they distribute their IP cores in .tdf files which are
> normally AHDL text files, but the .tdf files of an IP core are totally
> encrypted.
> Does anyone know if there is such a thing as an EDIF to an encrypted TDF
> converter?
> Such a program will do the same thing Xilinx's EDIF2NGD does.
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)

The Altera IPs are encrypted using an encryption program that is
available only to AMPP members (Altera Mega-function Partnership Program
or something like that).  The program also come with a license generator
that generates the licenses required to unlock the design.
An IP provider can then encrypt their IP and then sent it to customer,
as well as a license file, and the customer have to add the content of
this license file to their MAXPLUS II license file.
The IP can be any text file format.

Joe




Article: 43696
Subject: Director of FPGA Design - New York City
From: Chris@n2tech.com (Chris Lewis)
Date: Wed, 29 May 2002 22:28:36 GMT
Links: << >>  << T >>  << A >>
Director of FPGA Design

Must have an advanced degree from a top EE University!!!

Looking for a great paycheck and incredible equity at your next job?
Look no further...

We are a stealthy Biotech start-up, looking for a strong, hands-on
FPGA/ASIC Manager/Director who can build a world class team of Chip
Developers from scratch.   

Ideally, we need you to be a digital systems designer, experienced
with computer architecture, numerical applications, and simulations.
Your designs will help run the worlds most advanced computational
chemistry simulations in the world.  Responsible for technology
mapping and FPGA design flows, you will lead cross-functional
development efforts involving software development, design
engineering, applications and technology development.  

You must have stellar academic credentials (i.e. MS/PhD from Stanford,
MIT, Berkley...) and 3+ years full-time work experience POST academia.

As well as substantial architecture and software development
experience and knowledge of device architecture of most leading FPGA
series, you will ideally have:
 Experience in leading architecture and software teams
 Understanding of the software complexity and ability to co-design
software and hardware.  
 Experience in using all leading FPGA tools, synthesis and simulation
tools
 Experience in developing mapping, place and route algorithms, with
the ability to understand the implementation issues of leading
algorithms
 Experience with the Xilinx Virtex line of FPGA's

We are willing to relocate our perfect candidate!!!!!!


If you are interested in this position, please submit your resume 
as an attachment in Word format and we will give you a call 
once we have a chance to review it.
 
For more information about N2 Technologies, please visit our web site:  http://www.n2tech.com
 
Restrictions: 
Due to time constraints, full-time candidates with IMMEDIATE 
(1-2 weeks) ability to start only.  
No contractors or job-hoppers (1.5 years or more at each position) please.  
Local candidates given preference.
 
Chris Lewis
Technical Recruiter
N2 Technologies
Tel 650-493-1500
Fax 650-493-1520
chris@n2tech.com
http://www.n2tech.com

Check out my Current Jobs on NTERVIEW
http://www.nterview.com

If you know someone who would be interested in this 
position, and refer that person to us, we will pay 
you $2000 if we place your referral candidate and 
they stay at the position through the guarantee period 
(usually 30-90 days).
 
How's it work?   Just reply to the position with your 
referral's contact info and your contact info including 
name, mailing address, phone number and email and we 
link your info to the referral in the database.  We 
will contact you when we place the candidate and a check 
for $2000 will soon follow.  
That's all it takes!!!

Article: 43697
Subject: about Configure FLEX10K10 with 89c51
From: wq00001@163.com (wuqiang)
Date: 29 May 2002 17:50:00 -0700
Links: << >>  << T >>  << A >>
I use mcu 89c51 to PS configure Flex10k10. I have followed the timing
in the altera pdf file, used the content of .ttf(Byte) file as
unsigned char array. Now NStatus signal is ok, but Conf_Done is never
to become hign to inform me to configure success. I check the board
and program again, but no error is found.
Who have finished similar work?

Article: 43698
Subject: Re: virtex 2 : DCM divided clock
From: mrand@my-deja.com (Marc Randolph)
Date: 29 May 2002 19:42:10 -0700
Links: << >>  << T >>  << A >>
eyals@hywire.com (Eyal Shachrai) wrote in message news:<70029bf5.0205290917.1320d152@posting.google.com>...
> 1. is there apossibility to use the same DCM to synthisize two divided clocks?


It depends on what divided values you need.  You can use the CLKFX to
produce M/D ratio of the input clock.

In addition, can also use the CLKDV output to produce one divided
version of the clock.


> 2. will it be wise to divide a 125 MHz clock in 16 ?

Only if you need 7.8126 MHz. ;-)

Seriously, it should be no problem for the DCM to handle this, and in
fact, you can divide by up to 32 by enabling the predivider on the
DCM.

Which raises a question... is there any benefit to using the CLKDV
output to do a divide by 16 over using the CLKFX output with M=1 and
D=16?  Lower jitter perhaps?

What if you needed a divide by 64.  Is it better to use two DCM's, one
each with /8, or one with D=64?  Ignore the increased current/power
consumption due to the 2nd DCM.

Have fun,

   Marc

Article: 43699
Subject: Engineering Samples for free?
From: rajatkarol@softhome.net (Rajat Karol)
Date: 29 May 2002 23:17:23 -0700
Links: << >>  << T >>  << A >>
Hi,

I wanted to know whether Xilinx or Altera provides engineering samples
for free?

Also whether there is any difference in function/ quality ( in terms
of perfomance or features or testability ) between engineering samples
and production samples.

Also are engineering samples available at a lesser rate ??

regards

Rajat



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