Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Wed, 10 Nov 1999 15:23:12 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: >Anybody had any experience with the VHDL simulation ? loads. from what you're saying, it seems that VHDL unisim/simprim simulation is a lot more mature than the verilog route. i occasionally have problems, but i haven't seen a model error in at least the last year. there have certainly been none of the verilog LUT problems, but i can't speak for the blockRAM problem. perhaps part of the reason for this is that the VHDL unisim and simprim models are virtually identical, and both use VITAL routines for all the hard work (which may, at first sight, seem rather odd for a functional simulation library...) evanArticle: 18751
Euripides Sotiriades <esot@mhl.tuc.gr> wrote: >I would like to know if i can ReadBack an Altera FPGA so I can get the >file that it is programmed. I have an Altera Programmer (the card, mpu >unit and the serial cable) If you just want to be able to make a copy, yes as long as the security bit was not programmed in the device. If you want to look at the design, no. Just go to the programmer and tell it to examine the device. You can then save the programming file or burn another PLD with it. -- richard_damon@iname.com (Redirector to my current best Mailbox) rdamon@beltronicsInspection.com (Work Adddress) Richad_Damon@msn.com (Just for Fun)Article: 18752
Oops, I missed the fact that you only need 5 bits. A very fast modulo 1 to 16 LFSR can be put in two CLBs, and can be programmed by changing the contents of a single 4 input LUT. Normally this would require reconfiguration, however, by using the RAM mode of the LUT, you can reload it's look-up function in sixteen clock cycles (this can corrupt the count sequence while changing the program). This can be extended to 5 bits, but the feedback equation becomes a function of 5 bits instead of 4, so changing the count modulus involves re-writing two LUTs, which can still be done in 16 clocks. The "programs" can be stored in additional CLBs configured as ROM cells, one program per LUT. Alternatively, you can control the feedback from each coutner output with an and gate for the xor and the and (error recovery) terms. If you need on-the-fly reprogramming, and don't need absolute speed (which for 103 MHz, you don't), you are probably better off area-wise with the loadable binary downcounter (should take 3 CLBs). Peter Alfke wrote: > Theron Hicks wrote: > > > Can any one point me to a design for a programmable divide-by-n using an > > XC4002xl device? I plan on using the fastest speed grade available in > > this part. I need to divide by n, where n can be any integer from 2 to > > 32. I don't care if the counter is up or down or whatever but it needs > > to count with a 50% clock at 102.4 MHz. > > In the 1992 Xilinx Data Book ( page 6-28) I published a design called: > "Fully Synchronous 5-Bit Counter Uses Only Three CLBs." > > This design would easily run at >150 MHz in XC4002, and even faster in the > newer 'XL devices.There is no carry involved, it's a Linear-Feedback Shift > Register Counter. Output wave-shape is also programmable. > > This particular design defines the modulus during configuration, but it can > easily be made programmable from a 5-bit input at the expense of a few more > CLBs. > > If you want, I can fax you the design, it's very simple, but non-obvious, > something a grad student might appreciate. > > Today I would use a 3.3 V device (XL), either XC4000XL or Spartan XL. > But that may depend on your power supply situation. For purely digital > designs, 5 V is history ( albeit a long history!) > > Peter Alfke, Xilinx Applications -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18753
SRL16E had the address bits backwards in 1.5i in the unisim library eml@riverside-machines.com.NOSPAM wrote: > ...i occasionally > have problems, but i haven't seen a model error in at least the last > year. there have certainly been none of the verilog LUT problems, but > i can't speak for the blockRAM problem. > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18754
Hi, I'm looking for data concerning the evolution of FPGA density over the years. If anyone knows about some paper/link/book ... Specifically i'd like to make a comparison between FPGA, DRAM and Asic technologies. Thanks StevenArticle: 18755
This is a multi-part message in MIME format. --------------34B48F0040967FDD0E67AF09 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello, can someone please tell me what are the steps involved in the developement of a CAD tool for the P&R problem, for FPGAs. I am new to this area and would very much appreciate a few tips in this regard.. Thank you very much Regards Anup --------------34B48F0040967FDD0E67AF09 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup kumar raghavan Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:0061-7-38761962 tel;work:0061-7-33658849 x-mozilla-html:FALSE url:www.csee.uq.edu.au org:University of Queensland;Computer Science and Electrical Engineering adr:;;;;;;Australia version:2.1 email;internet:anup@elec.uq.edu.au fn:Anup Kumar end:vcard --------------34B48F0040967FDD0E67AF09--Article: 18756
This is a multi-part message in MIME format. --------------42EBCD09952C09E0CFCAA409 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit We are currently using the Synopsys FPGA Express, and I can summarize like this: Installation/license: Terrible! We are using a floating license, and we have spent more time on installing/uninstalling the program + making the license manager (FlexLM) work properly than we have spent on our designs. I think that licensing the program must be a great cost for Xilinx who we bought it from. Using the tool: I think it is ok once it works. Have had some trouble not finding the library even though all of them are installed an still on the disk. The only way I found to solve this was to reinstall the program. Overall, if there had been no license problems, I would hesitate to recommend it. Still, I think we have spent so much time on this that the cheep price of the tool doesn't matter anymore. Greg Neff wrote: > We are evaluating these tools. I would appreciate any comments from > those of you that have experience with at least two of the following > tools: > > Synopsys FPGA Express > Synplicity Synplify > Exemplar Leonardo Spectrum > -- ------------------------------------------ Olav Gundersen Development Engineer --------------42EBCD09952C09E0CFCAA409 Content-Type: text/x-vcard; charset=us-ascii; name="og.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Olav Gundersen Content-Disposition: attachment; filename="og.vcf" begin:vcard n:Gundersen;Olav tel;fax:+47 67 24 30 80 tel;work:+47 67 24 36 80 x-mozilla-html:FALSE org:R&D Land Earth Stations version:2.1 email;internet:og@satcom.nera.no title:Development Engineer adr;quoted-printable:;;Bergerveien 12=0D=0AP.O. Box 91=0D=0A;Billingstad;Norway;N-1375;Norway end:vcard --------------42EBCD09952C09E0CFCAA409--Article: 18757
Olav Gundersen <og@satcom.nera.no> wrote in message news:382BFAA9.613E3EC@satcom.nera.no... > We are currently using the Synopsys FPGA Express, and I can summarize > like this: > > Installation/license: Terrible! We are using a floating license, and we > have spent more time on installing/uninstalling the program + making the > license manager (FlexLM) work properly than we have spent on our > designs. I think that licensing the program must be a great cost for > Xilinx who we bought it from. My experience with FPGA Express was similar but I don't expect that the competitors' license managers are any better. As far as I know, they are also using FlexLM. Once you have it going, the license server doesn't seem to be too much trouble. > Using the tool: I think it is ok once it works. Have had some trouble > not finding the library even though all of them are installed an still > on the disk. The only way I found to solve this was to reinstall the > program. I haven't used Synplify but we evaluated it a few months ago. Synplify has some cool features but it didn't support all the VHDL language features that FPGA Express did at that time. A more serious problem was that Synplify's error messages were hard to interpret. In one case, Synplify crashed when it ran into something it didn't understand so we got no error message at all. An important consideration for any of these tools is, "How good is the support?" Any of these tools is likely to crash occasionally and you need to know what to do when it happens. Synplify runs faster than FPGA Express but I'm satisfied with the run times I have. Good language support and good error messages are more important to me and probably save more time anyway. My overall impression is that Synplify has rushed to add features before the basics operations are working well. > Overall, if there had been no license problems, I would hesitate to > recommend it. Why would you hesitate? What else went wrong? Paul Butler c_paul_butler@yahoo.comArticle: 18758
"Pin locking problem" is when the pins prevent a place and route solution that meets timing. What happens is you do a design and assign pins. At some point a board is made using the pin assignments you provided. Now, you go in and make a small change to the design but when you try to do the place and route, it won't route. The problem is not unique to Altera, although it is more acute because of the routing structure and the fact there is less you can do about it. Altera's routing structure is not complete in the sense that LE's only have direct connections to a limited number of other LE's on the same row. The pins have each connections to a limited number of row/column wires. When an LE needs to connect to one that it can't reach directly, it needs to use a third LE to make that connection, which uses up additional routing resources. The Altera device has about 3 row wires for every 4 LEs, so if all the LEs are connected to LEs in other LABs you run out of routing long before you run out of logic. When you start having to make connections through LEs, the problem is compounded. The place and route program tries to place the LE's to minimize the second level connections, which works reasonably well when both ends of the route can be moved. When the pins have been 'locked', one end of the pin nets are locked into position, which in turn limits the most favorable positions of the LEs connected to the pins. giuseppe giachella wrote: > Can someone explain me what is exactly the "pin locking" problem > in Altera fpga ? > > ______________________________________________________ > Get Your Private, Free Email at http://www.hotmail.com > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18759
Greg Neff wrote: > We are evaluating these tools. I would appreciate any comments from > those of you that have experience with at least two of the following > tools: > > Synopsys FPGA Express > Synplicity Synplify > Exemplar Leonardo Spectrum One of the biggest differences is the lack of RAM inference in FPGA Express. Both Synplify & Spectrum can at least infer the smaller 16x1, 32x1 devices in the Xilinx FPGAs. This makes is possible to design a parametrizable NxM RAM block in Synplify/Spectrum but, at least for Verilog designs, this is difficult under F-Exp. You could use LOGIBlox but it doesn't support Virtex parts. At least for v3.3 [maybe v3.2] FPGA Express now supports Verilog `ifdef. This was a real necessity for us as we had to make an ASIC and an FPGA from the same HDL sources. Since this was not the case in January we bought Synplify. I'm now going to try and build the FPGA under Express & I'll post the comparisons.Article: 18760
Hi,
I needed to implement a look up table in an Altera MAX7000. There
is a magafunction lpm_rom which is what I need, but the documentation
says that it is only for Flex 10k series. Is there any other
magafunction which allows me to do a ROM look up table (5-bit address
and 5-bit data)?
Artur
11.12.99
Article: 18761Can someone explain me what is exactly the "pin locking" problem in Altera fpga ? ______________________________________________________ Get Your Private, Free Email at http://www.hotmail.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18762
Senior Systems Hardware Engineer
DTI Network's Product Development Center located in Boca Raton, Florida is
looking for a senior systems hardware engineer for a full-time position. The
individual will be a member of the R&D team, and will be primarily
responsible for the architecture and design along with implementation and
testing of complex telecommunication systems/modules. System level
architecture with communication protocols, as per how they relate to next
generation networks are strongly preferred.
This position requires the following:
· A college degree in BSEE or equivalent.
· 10 to 15+ years' experience in system architecture, design and
implementation.
· New product specification and design.
· System architecture including hardware/software trade-offs.
· High Speed Digital Design methods, helpful with compliance experience.
· Programmable logic design and simulation, preferably utilizing VHDL.
· Experience with system or board level simulation tools.
· Working knowledge of Motorola MPC860 or other High MIPs RISC processors.
· Familiarity with related FCC, NEBS, ANSI or BellCore standards.
· The ability to work in a team environment as well as lead projects.
This is a Pre-IPO opportunity with generous stock options. We are moving
into a new 27,000 sqft facility on the Florida Atlantic University campus
with access to college facilities. This is an excellent career opportunity
to be involved in a Pre-IPO start-up, visit our website at
www.dtinetworks.com.
Regards,
Norm Ebsary
Director Hardware Engineering
-->
DTI Networks
6601 Lyons Road, Suite E1
Coconut Creek, Florida
33073-3636
Email: norm@dticorp.com
WWW: www.dtinetworks.com
Tel: 954-247-4116
Fax: 954-247-4050
The best approach for next generation network solutions
-->
Over the Top!
Article: 18763I have used all three tools and have no problem rating them. Synplicity Synplify Exemplar Leonardo Spectrum about equal Synopsys FPGA Express a distant third. Greg Neff <gregneff@my-deja.com> wrote in message news:80f06r$4pi$1@nnrp1.deja.com... > We are evaluating these tools. I would appreciate any comments from > those of you that have experience with at least two of the following > tools: > > Synopsys FPGA Express > Synplicity Synplify > Exemplar Leonardo Spectrum > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 18764
I am a newbie using Xilinx Foundation Series 1.5 with XC9536VQ44-15 CPLD. With a deadline fast looming. Writing in some panic. I have used schematic editor entry tool and done implementation successfully without errors. But trying to download to device through the JTAG programmer I get the following error: ------------------------------------------------------------------- JTAG Programmer Started 1999/11/13 01:53:25 Loading Boundary-Scan Description Language (BSDL) file 'C:/fndtn/data/xc9536.bsd'.....completed successfully. Checking boundary-scan chain integrity...done. Verifying device positions in boundary-scan chain... Instance 'ect(Device1)' at position '1'...verified. Verification completed. Boundary-scan chain validated successfully. 'ect(Device1)': Checking boundary-scan chain integrity... ERROR:basut - Unable to locate BSDL file 'xc9536_v2.bsd'. Check that your XILINX variable is properly set and that the BSDL file is located along its path. 'ect(Device1)': Programming terminated due to errors. --------------------------------------------------------------------- Where can I find xc9536_v2.bsd file ? Foundation has only xc9536.bsd. Does JTAG detect version of XC9536 soldered to PCB ? In desparation I tried renaming the xc9536.bsd as xc9536_v2.bsd, but that does not help. A search on Xilinx website proved futile, and a websearch on three engines could not locate this file :( Would really appreciate any help! UdayArticle: 18765
anup kumar raghavan <anup@elec.uq.edu.au> writes: > Hello, can someone please tell me what are the steps involved in the > developement of a CAD tool for the P&R problem, for FPGAs. I am new to > this area and would very much appreciate a few tips in this regard.. (1) find out who is doing it for free. (grep for "gEDA".) (2) work w/ those people. thiArticle: 18766
Say for a relatively low end part like a Xilinx XC4005 as seen in the XESS board, just how many bits is the "bitstream" file that is loaded into it for configuration? Hundreds, thousands, tens of thousands? Sorry if this is a really basic question. I'm exploring tying a microcontroller to an FPGA, and I'm wondering how much space I need to worry about dedicating to the config stream. It might change over the life of the system so a fixed configuration EPROM isn't in the cards. RobArticle: 18767
On Sun, 17 Oct 1999 02:22:54 +0200, "Ulf Samuelsson" <ulf.samuelsson@atmel.spamme.com.not> wrote: > > >avms@my-deja.com skrev i meddelandet <7ua4gb$djg$1@nnrp1.deja.com>... >>In article <iLMN3.2748$lz4.5538@nntpserver.swip.net>, >> "Ulf Samuelsson" <ulf.samuelsson@atmel.spamme.com.not> wrote: >>> If someone want to have a look at the FPSLIC, >>> The FPGA+40 Mhz AVR RISC+Peripherals + Memory chip >>> under development at Atmel, Here's the link: >>> http://www.atmel.com/atmel/products/prod39.htm >> >> When it will be in production? >Early next millenium :-) >> And what price is expected for unit >Slightly more expensive than the equivalent sized AT40k FPGA. >Definitely dollars and not cents. > > > > >-- >This is a personal view which may or may not be shared >by my employer Atmel Sweden >Ulf Samuelsson ulf 'a't atmel 'd'o't com > >> >>Sent via Deja.com http://www.deja.com/ >>Before you buy. > > ============================================= I didn't see 40 MHz on the site. Nevertheless . . . FPSLIC devices combine 10K to 40K gates of Atmel's patented AT40K FPGA architecture, a 30 MIPS AVR 8-bit RISC microprocessor core, numerous fixed microcontroller peripheries and a total of 36K Bytes of program and data SRAM. However, it's sad to see that while ATMEL has all the necessary technology in hand to make a field-programmable device which is both secure, i.e. no EXTERNAL configuration prom, and an on-board processor which could decrypt, or whatever, the incoming configuration data, they're not interested in protecting any IP other than their own. Anyone who faithfully copies my product gets the fruit of my labor for free, and has to buy ATMEL's parts to do it. DickArticle: 18768
XILINX Data Book (page 6-49) specifies XC4005E configuration array length as 95008 bits = 11876 bytes. Rob Barris wrote in message ... > > Say for a relatively low end part like a Xilinx XC4005 as seen in the >XESS board, just how many bits is the "bitstream" file that is loaded into >it for configuration? Hundreds, thousands, tens of thousands? ...Article: 18769
Where did you get it, what did you pay, and why are you selling it? That seems like "too good of a deal" <fidonews2@my-deja.com> wrote in message news:80dahd$u4a$1@nnrp1.deja.com... > Hi, > > I'm selling a full Altera MAX+Plus II package, V9.01. It's new and still > sealed (I never used it). This package is their "Magnum" product which > supports full VHDL. Great for DSP design. Includes manual, CD-ROM and > dongle. The standard 3-month maintainance has expired. I can transfer > registration to you upon purchase. Originally $7000, will sacrifice for > $1000 including shipping. > > - Chris > fidonews2@my-deja.com > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 18770
On Sat, 13 Nov 1999 09:17:00 GMT, rbarris@quicksilver.com (Rob Barris) wrote: | | Say for a relatively low end part like a Xilinx XC4005 as seen in the |XESS board, just how many bits is the "bitstream" file that is loaded into |it for configuration? Hundreds, thousands, tens of thousands? | | Sorry if this is a really basic question. I'm exploring tying a |microcontroller to an FPGA, and I'm wondering how much space I need to |worry about dedicating to the config stream. It might change over the |life of the system so a fixed configuration EPROM isn't in the cards. | |Rob Rob, a 4005EX or XL needs 151,960 bits. We commonly put the microprocessor code and the Xilinx config data into a single eprom, and let the uP load the FPGA(s) at powerup. It's very clean... we can send a customer one eprom that updates everything. The smallest we've done (an embedded digital delay generator) is a product using an MC68332 and an XCS20, all in a single 27256 eprom. We have a PowerBasic program that builds an eprom image from a Motorola S28 file plus a Xilinx .RBT file, if anybody's interested. John = = = = = = = = = = = Visualize Whirled Peas!Article: 18771
Andreas Barthel wrote: > > Does anyone know a FPGA evaluation (demonstration) board for Xilinx > FPGA's > larger PC84 packages or reprogrammable Actel FPGA's ? > Where can I get it ? Here is a list of demo boards: http://www.fernuni-hagen.de/IT/FPGA/boards.html The list includes also German/European manufacturers. MarkusArticle: 18772
I wrote: : > I have a little behavioural VHDL FSM which analyzes ok; when I try to : build : > it Orcad Express generates an error message telling me I have too many : > product terms for a couple of rows. On inspecting the vhdl netlist : > its generated, there are actually not many PTs in the expressions : > its complaining about - well within the powers of a 22V10! : > Is there a common user error which could generate this? Or is this : > a known problem for which a patch is available? (I have v. 7.1) : > : > Thanks for any advice, : > : > Graham Seaman : > OK, I found the problem (with some help ;-). The error message itself is misleading: its actually complaining because the registers used for state bits in an FSM haven't been assigned pins [so ANY PTs would be too many in this case]. This is because I went from a behavioural (case-statement) style design for the FSM, and as far as I can see means that I can't use this style of design for state machines going into PLDs and have to revert to hand minimisation. Since this must be one of the most common applications for PLDs, and since IIRC even ABEL used to be able to handle this, I'm now curious about how common a problem this is. Is VHDL synthesis generally worse than old ABEL/CUPL/Palasm synthesis? Or is it just that little PLDs are so unsexy that no-one bothers much developing the tools? GrahamArticle: 18773
Rob Barris wrote: > Say for a relatively low end part like a Xilinx XC4005 as seen in the > XESS board, just how many bits is the "bitstream" file that is loaded into > it for configuration? 95,008 bits ( NOT bytes!) in the XC4005 and XC4005E, but 151,960 in the XC4005XL. See Xilinx data book, page 6-49, tables 20 and 21. Peter Alfke, Xilinx ApplicationsArticle: 18774
John Larkin <jjlarkin@highlandSnipSniptechnology.com> wrote:
>We commonly put the microprocessor code and the Xilinx config data
>into a single eprom, and let the uP load the FPGA(s) at powerup. It's
>very clean... we can send a customer one eprom that updates
>everything. The smallest we've done (an embedded digital delay
>generator) is a product using an MC68332 and an XCS20, all in a single
>27256 eprom.
A nice approach. We do the same with a Z180 processor and an XCS30. The 180's
clocked serial port is great for bitsteaming the XCS.
Richard
------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
Spamtrapped: Remove the XY
---------------------------------------
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z