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Messages from 53800

Article: 53800
Subject: Quartus-II, how to use a user package
From: creon100@yahoo.com (Sean)
Date: 24 Mar 2003 06:42:45 -0800
Links: << >>  << T >>  << A >>
In my current design I have a small VHDL file that is a package
containing some math functions.  However, I can't figure out how to
use this in Quartus-II because it doesn't find the library.  I've
tried copying the package file into a folder with a library name in
the main quartus library directory, but that doesn't work.  I then
tried specifying that folder in the user libraries settings, but it
still didn't find it.  At this point I can't synthesize anything since
it can't find this package, does anyone have any suggestions?  Thanks.

Article: 53801
Subject: Re: FPGA FFT Questions
From: already5chosen@yahoo.com (Michael S)
Date: 24 Mar 2003 06:46:13 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote in message news:<3E7CD5DA.A8DA1854@andraka.com>...
> Even in that case it would probably be desirable to at least move away from 
> IEEE floats inside the co processor, as they are a pain to deal with in 
> hardware. But you are correct, without knowing the bounds of the problem it 
> is very difficult to recommend an optimal course of action.

[O.T.]
I was always interested in the analysis of the relative impact of the
rounding error in the floating-point and the fixed-pointed
implementations of the (Radix-2) FFT. However I was too lazy to look
for an answer in the literature or to do the analysis myself (also,
likely,  I am not properly equipped for the later).
My intuition says that at comparable precision both approaches are
about equal for SNR, but floating-point is significantly better for
SFDR . Then again, using intuition is not a good approach to rely on.
Would you be so kind to give me a pointer to the analysis I am looking
for ?

Article: 53802
Subject: CLKDLL synthesized with synplify pro
From: tote_last@yahoo.de (tote)
Date: 24 Mar 2003 08:10:54 -0800
Links: << >>  << T >>  << A >>
Hi,

in my design i'm using 2 clock signals, CLK and CLK2x. I'm generating
these 2 clocks from a "input-clock" with a DLL like:

IBUFG U1 (.I(Clk_in), .O(CLKIN));
CLKDLL U2 (.CLKIN(CLKIN), .CLKFB(CLKB), .RST(~nReset1),
	.CLK0(Clk), .CLK90(), .CLK180(), .CLK270(),
        .CLK2X(CLK2x), .CLKDV(), .LOCKED(LOCKED));
BUFG U3 (.I(Clk), .O(CLKB));

That's basically how it's described in the xilinx application notes.
Working fine for simulation.
However, does anybody know, how to write this to synthesize it with
synplify pro?

Thanx for your help
Thorsten

Article: 53803
Subject: Which Prom for Spartan-II?
From: "Stefan Schulte" <St_Schulte@web.de>
Date: Mon, 24 Mar 2003 17:12:26 +0100
Links: << >>  << T >>  << A >>
Hi all!

Do anyone know which serial prom (EEPROM) I can use on a
digilent inc. D2-Board (8pin DIP)?

Thanks!

Stef@n



Article: 53804
Subject: Re: synthesizability question
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Mon, 24 Mar 2003 16:23:01 GMT
Links: << >>  << T >>  << A >>
"Jimmy Zhang" <crackeur@attbi.com> wrote in message

>   I have a simple question regarding to the synthesizability of the
> following expression
>      Data[index+1]  ?

You have to think hardware, not software.  If the functionality is what is
desired, then the problem might be reduced to addressing (index) into a
memory array (Data).  You FPGA could implement this through a block memory
resource along with support logic.  You could have, for example, a 2Kx8
"Data" array being addressed by your "index" after incrementing it by one.
Of course, you wouldn't write the expression exactly as you did because
you'd need to, at the very least, have an output, clock/s and other control
signals.

I'm just a newbie at this (not hardware or software, FPGA's) and one of the
things that I keep reminding myself of is something I learned in school
twenty years ago:  "The representation of the problem is the most
significant factor in finding a solution".  That's why I say "think
hardware, not software".  If you think of problems like the above question
in terms of possible hardware representations of the problem you will
undoubtedly come out of it with a more appropriate solution.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"




Article: 53805
Subject: Xilinx FPGAs available?
From: "Brendan Lynskey" <brendan@comodogroup.com>
Date: Mon, 24 Mar 2003 16:49:54 -0000
Links: << >>  << T >>  << A >>
Hi.

I need to buy 5 Xilinx...

    XC2V4000-6FF1152 or
    XC2V6000-6FF1152

Can anyone out there help?

Thanks in advance,


--
Brendan Lynskey
Comodo Research Lab

Click on www.comodogroup.com/secure-email to keep your emails
confidential with a complementary FREE personal Secure Email Certificate



Article: 53806
Subject: Re: Difference between static and active partial reconfiguration of
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 24 Mar 2003 09:09:48 -0800
Links: << >>  << T >>  << A >>
Normal reconfiguration ( apparently it is called static, i.e. not the
partial reconfiguartion) works the same way as the power-on configuration.
Outputs are 3-stated, internal flip-flops are held ( set or reset), etc.

Gruß
Peter Alfke, Xilinx Applications
=============
Rainer Schmidt wrote:
> 
> Hi,
> 
> What is the difference between static and active partial
> reconfiguration? Xilinx application notes say the remaining part of the
> design does still work in active reconfiguration mode. But what happens
> to the remaining part in static reconfiguration mode? Is the global
> clock stopped? Are the IOBs disabled during reconfiguration? Anything else?
> 
> Thanks,
> Rainer

Article: 53807
Subject: Re: Xilinx FPGAs available?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Mon, 24 Mar 2003 17:18:23 +0000 (UTC)
Links: << >>  << T >>  << A >>
Brendan Lynskey <brendan@comodogroup.com> wrote:
: Hi.

: I need to buy 5 Xilinx...

:     XC2V4000-6FF1152 or
:     XC2V6000-6FF1152

: Can anyone out there help?

: Thanks in advance,

Look at e.g. www.nuhorizons.com

It seems that only the FF1517 packages are on stock. A call to Xilinx
distributors might however be justified, as the price of the parts is quite
considerable. 

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 53808
Subject: Re: Xilinx FPGAs available?
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 24 Mar 2003 09:22:56 -0800
Links: << >>  << T >>  << A >>
Those parts are plentifully available. 
Talk to your distributor. It's his job to help you !

Peter Alfke
========================
Brendan Lynskey wrote:
> 
> Hi.
> 
> I need to buy 5 Xilinx...
> 
>     XC2V4000-6FF1152 or
>     XC2V6000-6FF1152
> 
> Can anyone out there help?
> 
> Thanks in advance,
> 
> --
> Brendan Lynskey
> Comodo Research Lab
> 
> Click on www.comodogroup.com/secure-email to keep your emails
> confidential with a complementary FREE personal Secure Email Certificate

Article: 53809
Subject: Re: synthesizability question
From: "zhengyu" <zhengyu@attbi.com>
Date: Mon, 24 Mar 2003 17:51:21 GMT
Links: << >>  << T >>  << A >>
what if I have logic such as
  Data[index] = 0x101;
  Data[index+1] = 0x100;
  Data[index+2] = 0x1000;
  Data[index+6] = 0x111;

Will it still be taken care of by synthesizer?

Jimmy

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:FhGfa.692$ZQ3.326@newssvr19.news.prodigy.com...
> "Jimmy Zhang" <crackeur@attbi.com> wrote in message
>
> >   I have a simple question regarding to the synthesizability of the
> > following expression
> >      Data[index+1]  ?
>
> You have to think hardware, not software.  If the functionality is what is
> desired, then the problem might be reduced to addressing (index) into a
> memory array (Data).  You FPGA could implement this through a block memory
> resource along with support logic.  You could have, for example, a 2Kx8
> "Data" array being addressed by your "index" after incrementing it by one.
> Of course, you wouldn't write the expression exactly as you did because
> you'd need to, at the very least, have an output, clock/s and other
control
> signals.
>
> I'm just a newbie at this (not hardware or software, FPGA's) and one of
the
> things that I keep reminding myself of is something I learned in school
> twenty years ago:  "The representation of the problem is the most
> significant factor in finding a solution".  That's why I say "think
> hardware, not software".  If you think of problems like the above question
> in terms of possible hardware representations of the problem you will
> undoubtedly come out of it with a more appropriate solution.
>
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
>
>
>



Article: 53810
(removed)


Article: 53811
(removed)


Article: 53812
Subject: Re: synthesizability question
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Mon, 24 Mar 2003 18:22:00 GMT
Links: << >>  << T >>  << A >>
Again, if we are thinking about a block of memory being the "Data" array,
then your assignments are nothing more than writing these values into
specific memory locations.  Yes, all of this is attainable.  However, I
insist, you need to think in terms of hardware.

There are many, many ways to approach some of these problems.  I see from
your last post that the number added to your index might not be constant.
However it is that you generate those numbers, the software and  hardware
approachs could be radically different.  As an example, let's say that your
data array is 400 nibbles long (your assigments seem to show four-bit
values).  In hardware, rather than try to manage the loading of the offset
and calculation of the resultant index it might be much more sensible to use
an address counter running at 100MHz and "gate" or select which addresses
are actually written to based on a 400 bit mask that is generated through
some algorithm.  By the same token any number of other approaches are
equally valid and might be more or less appropriate.

Maybe you have the wrong idea as to what a synthesizer does.  It doesn't
turn C programs into hardware, although there are packages out there that
take this approach to a certain level (Handel C).  I looked at Handel C when
I was getting started and my conclusion (and fear) was that there was a real
chance of creating really bloated and overly-complex hardware with this
approach.  Being old-school I have a preference for being closer to the
gates and structures that are being interconnected.  Then again, I feel the
same way about using C for embedded programming.  Every time I've looked at
an embedded C program there's so much architecture-specific stuff in it that
you might as well do it in assembler, which is what I prefer, by far.

But I could be wrong.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





"zhengyu" <zhengyu@attbi.com> wrote in message
news:tAHfa.202704$L1.34938@sccrnsc02...
> what if I have logic such as
>   Data[index] = 0x101;
>   Data[index+1] = 0x100;
>   Data[index+2] = 0x1000;
>   Data[index+6] = 0x111;
>
> Will it still be taken care of by synthesizer?
>
> Jimmy
>
> "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
> news:FhGfa.692$ZQ3.326@newssvr19.news.prodigy.com...
> > "Jimmy Zhang" <crackeur@attbi.com> wrote in message
> >
> > >   I have a simple question regarding to the synthesizability of the
> > > following expression
> > >      Data[index+1]  ?
> >
> > You have to think hardware, not software.  If the functionality is what
is
> > desired, then the problem might be reduced to addressing (index) into a
> > memory array (Data).  You FPGA could implement this through a block
memory
> > resource along with support logic.  You could have, for example, a 2Kx8
> > "Data" array being addressed by your "index" after incrementing it by
one.
> > Of course, you wouldn't write the expression exactly as you did because
> > you'd need to, at the very least, have an output, clock/s and other
> control
> > signals.
> >
> > I'm just a newbie at this (not hardware or software, FPGA's) and one of
> the
> > things that I keep reminding myself of is something I learned in school
> > twenty years ago:  "The representation of the problem is the most
> > significant factor in finding a solution".  That's why I say "think
> > hardware, not software".  If you think of problems like the above
question
> > in terms of possible hardware representations of the problem you will
> > undoubtedly come out of it with a more appropriate solution.
> >
> >
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > Martin Euredjian
> >
> > To send private email:
> > 0_0_0_0_@pacbell.net
> > where
> > "0_0_0_0_"  =  "martineu"
> >
> >
> >
>
>



Article: 53813
Subject: Re: Xilinx FPGAs available?
From: nospam <nospam@nospam.invalid>
Date: Mon, 24 Mar 2003 18:45:56 +0000
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:

>Those parts are plentifully available. 
>Talk to your distributor. It's his job to help you !

A distributer's job is to tell you they have no stock then quote
manufacturer MOQs and lead times. 

That way you can wait till the manufacturer gets round to making some then
you must buy more parts than you need and get to pay the distributer a
premium for the privilege. 

(Actually the last Xilinx distributor I used was OK, but, the above seems
to apply generally). 



Article: 53814
Subject: Permanent Local Damage to FPGA
From: Michael Garvie <mmg20@cogs.susx.ac.uk>
Date: Mon, 24 Mar 2003 18:54:46 +0000
Links: << >>  << T >>  << A >>
Dear All,
Do you know of any evidence suggesting a permanent failure mode
affecting a local area (CLB or routing) of an FPGA which doesn't go away
with reconfiguration or rebooting?  Perhaps manufacturing defects only
appearing after a year of deployment,  damage due to extreme operating
conditions or general degradation after decades of deployment?

Single Event Latch-Up seems to be extremely uncommon and when it does
happen reconfiguration restores correct functionality.

Yours Sincerely,
Miguel Garvie


Article: 53815
Subject: Does Xilinx have self-boot option like Cypress?
From: "Brad Smallridge" <bsmallridge@dslextreme.com>
Date: Mon, 24 Mar 2003 11:27:07 -0800
Links: << >>  << T >>  << A >>
Hi y'all,

I am looking at the Xilinx lines and was wondering if they have a self-boot
package.  Cypress offers this in their BGA packages.  If they don't, is this
a serious security issue?

Thanks,

Brad Smallridge





Article: 53816
Subject: Re: Does Xilinx have self-boot option like Cypress?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Mon, 24 Mar 2003 19:36:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <v7un19b17bpm7b@corp.supernews.com>,
Brad Smallridge <bsmallridge@dslextreme.com> wrote:
>Hi y'all,
>
>I am looking at the Xilinx lines and was wondering if they have a self-boot
>package.  Cypress offers this in their BGA packages.  If they don't, is this
>a serious security issue?

What do you mean by "Self boot"?  Having configuration and part in the
same package?

Also, I don't see how that really affects security, it isn't that much
harder to dig a separate piece of flash memory out of a package.


-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 53817
Subject: Re: CLKDLL synthesized with synplify pro
From: "Avrum" <avrum@sympatico.ca>
Date: Mon, 24 Mar 2003 14:51:50 -0500
Links: << >>  << T >>  << A >>
Pretty much exactly like that.

However, from your naming convention, you may be confusing which signal to
use as the main clock to clock logic. The clock that should be fed to the
flip-flops is the output of the BUFG, in this case, named CLKB, not the
signal named Clk - this is a local, dedicated connection from the DLL to the
BUFG. The BUFG component is the main "clock buffer" - conceptually, it
drives the load of the clock distribution network.

In addition, you need a second BUFG to drive the flops being driven on the
CLK2x domain. You would need to add

BUFG U4 (.I(CLK2x), .O(CLK2XB));

Again, remember, CLK2XB is the clock that should be used to drive flops on
the 2X domain (not CLK2x).

Also, (I don't have the specs in hand, and you don't say which architecture
you are using), there may be a requirement as to which clock needs to be
used for the CLKFB of the DLL when you are using both CLK and CLK2X - you
may need to use the output of the CLK2X BUFG (which I called CLK2XB).

Avrum

"tote" <tote_last@yahoo.de> wrote in message
news:91e0be86.0303240810.46e23d89@posting.google.com...
> Hi,
>
> in my design i'm using 2 clock signals, CLK and CLK2x. I'm generating
> these 2 clocks from a "input-clock" with a DLL like:
>
> IBUFG U1 (.I(Clk_in), .O(CLKIN));
> CLKDLL U2 (.CLKIN(CLKIN), .CLKFB(CLKB), .RST(~nReset1),
> .CLK0(Clk), .CLK90(), .CLK180(), .CLK270(),
>         .CLK2X(CLK2x), .CLKDV(), .LOCKED(LOCKED));
> BUFG U3 (.I(Clk), .O(CLKB));
>
> That's basically how it's described in the xilinx application notes.
> Working fine for simulation.
> However, does anybody know, how to write this to synthesize it with
> synplify pro?
>
> Thanx for your help
> Thorsten



Article: 53818
Subject: Re: Does Xilinx have self-boot option like Cypress?
From: "Brad Smallridge" <bsmallridge@dslextreme.com>
Date: Mon, 24 Mar 2003 11:58:13 -0800
Links: << >>  << T >>  << A >>
I believe that the PROM chip is separate but encased in
the same package as the CPLD chip.  Correct me if I am
wrong anybody.  So someone would have to open the
package and probe the silicon instead of just probing the
external pins.

Brad Smallridge




Article: 53819
Subject: Re: Does Xilinx have self-boot option like Cypress?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Mon, 24 Mar 2003 20:15:05 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <v7uorm4j554l59@corp.supernews.com>,
Brad Smallridge <bsmallridge@dslextreme.com> wrote:
>I believe that the PROM chip is separate but encased in
>the same package as the CPLD chip.  Correct me if I am
>wrong anybody.  So someone would have to open the
>package and probe the silicon instead of just probing the
>external pins.

Which is hardly a barrier at all.

The Virtex 2/V2Pro have a better solution, a 3DES key with dedicated
battery backup used to decrypt the bitfile.  3DES is effectively
brute-force immune, and it is harder to read the contents of an SRAM
cell than it is t odepackage and read a PROM chip.

The cost is a dedicated lithium battery on the board to keep those
SRAM bits powered.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 53820
Subject: Re: Xilinx FPGAs available?
From: "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com>
Date: Tue, 25 Mar 2003 09:06:46 +1200
Links: << >>  << T >>  << A >>
"nospam" <nospam@nospam.invalid> wrote in message
news:9uju7vohr8kk9u8if6vaduf54gookigl6f@4ax.com...
> Peter Alfke <peter@xilinx.com> wrote:
>
> >Those parts are plentifully available.
> >Talk to your distributor. It's his job to help you !
>
> A distributer's job is to tell you they have no stock then quote
> manufacturer MOQs and lead times.
>
> That way you can wait till the manufacturer gets round to making some then
> you must buy more parts than you need and get to pay the distributer a
> premium for the privilege.

It's a tough job but someone has to do it. :-)

I now try to use parts that I can

A. Source from the manufacturers web site
B. Source from Digikey

As you can tell we build in the 100's to 1000's not the 10k's to 100k's

Ralph



Article: 53821
Subject: Re: Does Xilinx have self-boot option like Cypress?
From: "Steve Casselman" <sc@vcc.com>
Date: Mon, 24 Mar 2003 21:08:07 GMT
Links: << >>  << T >>  << A >>
I was just wondering how secure 3DES is if you know the bits it is trying to
encode? The first 64-bits in a bitstream are pretty much the same.

http://www.cl.cam.ac.uk/~rnc1/descrack/cracker.html

http://www.cl.cam.ac.uk/~rnc1/descrack/sums.html


I'm wondering what kind of machine it would take based on these numbers.

Steve

"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message
news:b5np09$2esm$1@agate.berkeley.edu...
> In article <v7uorm4j554l59@corp.supernews.com>,
> Brad Smallridge <bsmallridge@dslextreme.com> wrote:
> >I believe that the PROM chip is separate but encased in
> >the same package as the CPLD chip.  Correct me if I am
> >wrong anybody.  So someone would have to open the
> >package and probe the silicon instead of just probing the
> >external pins.
>
> Which is hardly a barrier at all.
>
> The Virtex 2/V2Pro have a better solution, a 3DES key with dedicated
> battery backup used to decrypt the bitfile.  3DES is effectively
> brute-force immune, and it is harder to read the contents of an SRAM
> cell than it is t odepackage and read a PROM chip.
>
> The cost is a dedicated lithium battery on the board to keep those
> SRAM bits powered.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu



Article: 53822
Subject: Re: Xilinx FPGAs available?
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 24 Mar 2003 13:13:41 -0800
Links: << >>  << T >>  << A >>
Brendan, you are asking for the fastest speed grade, and a particular
package option.
Trust your distributor, but ask him for alternatives ( like a slower
speed grade, or a different package).
The multinational distributors like memec and avnet ship across national
borders without any trouble...

Peter Alfke 
===================
Peter Alfke wrote:
> 
> Those parts are plentifully available.
> Talk to your distributor. It's his job to help you !
> 
> Peter Alfke
> ========================
> Brendan Lynskey wrote:
> >
> > Hi.
> >
> > I need to buy 5 Xilinx...
> >
> >     XC2V4000-6FF1152 or
> >     XC2V6000-6FF1152
> >
> > Can anyone out there help?
> >
> > Thanks in advance,
> >
> > --
> > Brendan Lynskey
> > Comodo Research Lab
> >
> > Click on www.comodogroup.com/secure-email to keep your emails
> > confidential with a complementary FREE personal Secure Email Certificate

Article: 53823
Subject: Re: Using FPGAs as coprocessors in a PC - findings
From: roy hansen <royhansen@removethis_norway.online.no>
Date: Mon, 24 Mar 2003 22:14:34 +0100
Links: << >>  << T >>  << A >>
Michael S wrote:

> How many units do you plan to produce ? What is target time to market

Only a few and at least one this year. It is for 
internal postprocessing of data from a sonar and not
something we plan to sell (see http://www.ffi.no/hugin for 
a description of our program). 

> ? Sometimes it sounds like you just want to make fun...

Well, my boss sometimes thinks I am having too much fun :-)

> 
> BTW, C67 is a wrong DSP to compare with FPGA. Compare apples with
> apples (fix-point FPGA with fix-point DSP). C64 is a DSP to compare.
> x8 600MHz C64 boards are not uncommon.

Actually not. I was hoping to do the math in single precision and not
fixed point so the comparison is a P4 CPU vs a c67. About fixed point
arithmetics - how simple is it to do 64 bit fixed point on a FPGA?
I will also look into the c64. 

-Roy


Article: 53824
Subject: Re: Does Xilinx have self-boot option like Cypress?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Mon, 24 Mar 2003 21:16:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <XsKfa.3296$SA5.122512529@newssvr14.news.prodigy.com>,
Steve Casselman <sc@vcc.com> wrote:
>I was just wondering how secure 3DES is if you know the bits it is trying to
>encode? The first 64-bits in a bitstream are pretty much the same.
>
>http://www.cl.cam.ac.uk/~rnc1/descrack/cracker.html
>
>http://www.cl.cam.ac.uk/~rnc1/descrack/sums.html
>
>I'm wondering what kind of machine it would take based on these numbers.

DES is 56 bits.  3DES brute-forced is probably at least 100+ bits,
lets say 106 bits as a good number (its probably a little higher, but
thats a nice number, 3DES is usually E(K1,D(K2,E(K3,M))) with K3 often
but not always the same as K1).

So at an expected time of an hour for a DES key, the same machine
would take 2^50 hours for 3DES (assuming that trying a 3DES key cost
the same amount).  In base 10, thats about 1,000,000,000,000,000
hours.

So even if you can crack a DES key using brute force in 1 second (easy
to do, actually), it would take 1,000,000,000,000,000 seconds, or
36,000,000 years to brute force 3DES.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu



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