Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 53275

Article: 53275
Subject: Re: Need help! Any experienced Handel-C user?
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 10 Mar 2003 11:51:47 +1000
Links: << >>  << T >>  << A >>
Hi Tom,

Tom Hawkins wrote:
> Unlike Handel C, where a program describes the behavior of a
> system, a Confluence program is an algorithm, or generator, that
> constructs an architecture from a set of logic primitives.

 > Like HDL, this approach still forces the designer to think
 > in terms of components and dataflow, rather than sequential
 > algorithms.  The resulting RTL is a direct translation
 > of your specified logic structure; it's not an embedded
 > machine to emulate a sequential process.

Sounds a bit like the Pam/Pamette architecture from Compaq research.  I 
think there you describe your hardware system using C++ templates that, 
when compiled and run, output VHDL that synthesises into the target 
hardware.

I think Jan Gray at www.fpgacpu.org has done some experiments with a 
similar concept.

> Though Confluence is still a proprietary language, our company
> has little overhead so we can afford to provide our tools
> at low cost (students and universities receive cf for free).
> 
> Give cf a try; you may like it!

Thanks.  I don't really have time at the moment - can you post some 
Confluence "code" to generate, e.g. a counter, or a simple state machine?

Cheers,

John


Article: 53276
Subject: Minimum Real-state K-multiplier/divider
From: dementepr@hotmail.com (JDS)
Date: 9 Mar 2003 18:48:54 -0800
Links: << >>  << T >>  << A >>
Hi gurus,

I'd like to have some advice in a way to implement a FPGA logic that
may reuse some gates, and minimize the required space. I have to
design two blocks with 2 outputs each:

1. Y1=25*X ; Y2=X/25 
2. Y1=24*X ; Y2=X/24

where X is 13 bits vector.

I got an idea to implement those by mean of constant operation
aproximation using JUST add & shift operations.

I'd appreciate any help.

JDS

Article: 53277
Subject: PCI specification
From: praveenkumar1979@rediffmail.com (praveen)
Date: 9 Mar 2003 19:54:12 -0800
Links: << >>  << T >>  << A >>
Hello Sir/Friends.

 I am designing a PCI target. I am presently reading specification and
 i didnot understand certain things which i have listed it.


1. I didnot understand why cacheline register required. I have read
that its length is same as processor cacheline length. what is the
exact function of this cacheline register. If you can give me an
example it will be wonderful.


2. How can understand how can PCI have multiple function? please can
you give me multiple function PCI?


3.what is use cardbus line register in configuration header?Is this
used only for PCMCIA cards? i have read that this is used for hot plug
devices where the initialisation code is on expansion ROM is this
true?Please give me more information about it?


4. why is cache wrap mode of addressing required ?where is mode used?


5. In PCI cache support protocol how is the next address information
given to cache controller because cache latches only the starting
address and snoops it. Thereafter its the function of target PCI to
give the next address addressed (in burst mode as target PCI latches
the starting address and thenafter it increments it withinself). How
this incremented address given to cachecontroller?


6.what is the value to be written for header type zero(ie bit[6:0]),
header type one , and header type two in the header type register in
configuration register ?I mean what value to be written in bit[6:0]
for header type zero/one/two?



7. Where is built in self test code located whether in expansion ROM
or where?how can you conduct a built in self test whether by doing a
configuration write on the BIST register or how?


8. what is the use Cardbus CIS pointer in configuration register? It
is said it is implemented by devices that share silicon between
cardbus and PCI.I didnot understand what that share silicon means? can
please give me more information about it?



9. What is use of max_lat register in configuration register?what i
have read is that value written in MIN_gnt register is read by BIOS
and load the latency timer with value in terms of PCI clock to it?
what is the use Max_lat register?Is it the priority?If so what is the
weightage of the bit?



10. what is this user defined features(UDF)?Can you please give me
example for this?

11.what is the difference between HIT and D_done in PCI target state machine?

 waiting for Your reply   
 thank in advance
 praveen

Article: 53278
Subject: Re: Cyclone power up problem
From: "Thorsten Bunte" <t.bunte@beckhoff.de>
Date: Mon, 10 Mar 2003 07:28:38 +0100
Links: << >>  << T >>  << A >>
Hello Martin,

the higher current is not a problem for cyclone devices only. You can find
this kind of behaviour at all kind of SRAM based FPGA. I experienced a
similiar problem with Altera FLEX 6000. Xilinx names the problem "Power-On
Surge". For Spartan IIe this current can go up to 2amps according with the
Spartan II datasheet. You can ask your Altera FAE what the maximum power on
surge is for Cyclone devices.

Xilinx provides a nice app note which describes you problem (Power on surge)
and gives an advices how to deal with it.
Xilinx app notes 450 (Power-On requirements for the Spartan II and Spartan
IIe famlies)
and 451 (Power Assist circuits for the Spartan II and Spartan IIe families)

Best regards,
Thorsten

"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag
news:TP5aa.79536$AV5.998926@news.chello.at...
> I've built a board with the Cyclone from Altera. First board was ok, but
on
> some of the following there was a problem with startup of the Cyclon.
>
> For the core voltage (1.5V) I use a drop-down regulator from Linear
> Technology (LTC3405) as described in the app. note (AN257). But the core
> voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I
> examined the problem by building an extern regulator.
>
> Starting the regulator without load and than attaching the VCCINT pins
from
> the FPGA leads to a successfull start. The output capacitor (4u7) supplies
> enough initial current.
>
> Measuring the current during startup yields to following results:
> First few us the Cyclone needs about 0.7A! Falling down to 200 mA and
> staying there for about 15 us (I think for internal startup). After that
it
> dropps to a few mA.
> The LCT3405 is a 300 mA regulator with a peak current of about 650 mA. It
> can not deliver this peak current during it's own start.
>
> Just wanted to tell this story (of hidden problems of a new family) for
> others who want to work with this new (still exciting) FPGAs to not run
into
> the same troubles.
>
> Martin Schoeberl
>
>



Article: 53279
Subject: Time constraint of bit-stream file
From: "Liao Jirong" <iscp1097@nus.edu.sg>
Date: Mon, 10 Mar 2003 15:58:49 +0800
Links: << >>  << T >>  << A >>
After I generate the bit-stream file, Xilinx tools returns two time
constraints

One is Default period analysis, another is Default net enumeration.

Which one determines the frequency of the bit-stream file?



Thx.



Article: 53280
Subject: Timing Simulation Glitches
From: "LIJO" <lijo_eceNOSPAM@hotmail.com>
Date: Mon, 10 Mar 2003 13:48:35 +0530
Links: << >>  << T >>  << A >>
Hi all,
  I am trying to implement a logic into FPGA. I have functionally verified
the logic and have synthesised the logic and verfied the post synthesis
simulation output.
After Implementation I have done the Timing Simulation with SDF files and
have found a lot of  invalid transitions between transition from one valid
state to another valid state. I have no idea why this happens.. Is there any
problem if I download the code to the FPGA . Will it work properly.

Please see the attached file.

thanks
Lijo




Article: 53281
Subject: Re: Timing Simulation Glitches
From: Muzaffer Kal <kal@dspia.com>
Date: Mon, 10 Mar 2003 08:42:11 GMT
Links: << >>  << T >>  << A >>
On Mon, 10 Mar 2003 13:48:35 +0530, "LIJO"
<lijo_eceNOSPAM@hotmail.com> wrote:

>Hi all,
>  I am trying to implement a logic into FPGA. I have functionally verified
>the logic and have synthesised the logic and verfied the post synthesis
>simulation output.
>After Implementation I have done the Timing Simulation with SDF files and
>have found a lot of  invalid transitions between transition from one valid
>state to another valid state. I have no idea why this happens.. Is there any
>problem if I download the code to the FPGA . Will it work properly.
>
>Please see the attached file.
>
>thanks
>Lijo

This is perfectly normal as long as the last change in the state
happens before the setup time of the accepting register which can be
verified with static timing analysis basically what the P&R tells you
as your designs maximum period as opposed to what they synthesis
output tells you. Timing simulation with SDF is good except when your
testbench may not be able to exercise all the paths your design might
take in real life and you may be missing some long paths.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 53282
Subject: Re: PCI specification doubt
From: Rick Filipkiewicz <rickXYZspamXYZ@mips.com>
Date: Mon, 10 Mar 2003 09:17:46 +0000
Links: << >>  << T >>  << A >>


praveen wrote:
> 12.what is the difference between HIT and D_done in PCI target state machine?
> 
>  waiting for Your reply   
>  thank in advance
>  praveen

Design your own PCI i/f from the spec. instead of usaing the cookbook 
and then you'll know.


Article: 53283
Subject: Re: scripting leonardo spectrum
From: Rick Filipkiewicz <rickXYZspamXYZ@mips.com>
Date: Mon, 10 Mar 2003 09:23:35 +0000
Links: << >>  << T >>  << A >>


Petter Gustad wrote:
> lishu99@yahoo.com (Lis Hu) writes:
> 
> 
>>I'm using the LeonardoSpectrum that comes with the Altera software 
>>subscription.  Is there a way to run it on the command line without
>>going through the GUI?  (Mostly I want to use a Makefile to manage
>>the synthesis flow.)
> 
> 
> Yes. You can write Tcl scripts to control Leonardo. I've only used it
> under Solaris, but I guess the same feature would exist under Windows.
> Consult your documentation.
> 
>

To run command line under Windoze its best to install Cygwin first, at 
least then you get a decent make & shell.


Article: 53284
Subject: Re: Issues in Outsourcing?
From: Rick Filipkiewicz <rickXYZspamXYZ@mips.com>
Date: Mon, 10 Mar 2003 10:34:41 +0000
Links: << >>  << T >>  << A >>


john jakson wrote:

> 
>>Hello 
>>we are an ASIC/FPGA company currently understaffed but with a very 
>>limited budget; so I wonder under what circumstances and what type of 
>>projects(non crucial?) we could consider outsourcing to some(which?) 
>>developing country team? 
>>Thanks 
>>MA 
> 
> 
> This is one of a long series of questions which confuse the hell out
> of me as to what & where & who you really are. What is your real
> agenda? It seems like you are gathering ASIC related business info for
> a paper? Are you a student or EE or what?
> 
> 
> 
>

Hey its obvious, he/she is doing an MBA.

Def.: MBA = Yesterday's solutions to last years problems.

Their major contribution to the world has been the coining of new and 
varied synonyms for the acts "to fire" or "to layoff".



Article: 53285
Subject: Re: PCI specification
From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
Date: Mon, 10 Mar 2003 05:25:47 -0600
Links: << >>  << T >>  << A >>
Praveen,

See my comments below.


praveen wrote:
> 
> Hello Sir/Friends.
> 
>  I am designing a PCI target. I am presently reading specification and
>  i didnot understand certain things which i have listed it.
> 
> 1. I didnot understand why cacheline register required. I have read
> that its length is same as processor cacheline length. what is the
> exact function of this cacheline register. If you can give me an
> example it will be wonderful.
> 

        Ignore CacheLine Size register.
A target only device doesn't use it at all.




> 2. How can understand how can PCI have multiple function? please can
> you give me multiple function PCI?
> 

        By hardwiring bit 7 of the Header Type register to 1, you are
identifying that your device is a multi-function device.
A good example of a multi-function device is a PCI-to-ISA bridge that
supports bus master IDE, USB, and ISA bus functionality. 



> 3.what is use cardbus line register in configuration header?Is this
> used only for PCMCIA cards? i have read that this is used for hot plug
> devices where the initialisation code is on expansion ROM is this
> true?Please give me more information about it?
> 

        I don't know the details, so ignore this for the moment.



> 4. why is cache wrap mode of addressing required ?where is mode used?
> 

        I think it is fair to say that almost no one uses Cacheline Wrap
mode during a burst memory access.
However, if an initiator attempts to do so, simply signal Disconnect
with Data during the first data phase.




> 5. In PCI cache support protocol how is the next address information
> given to cache controller because cache latches only the starting
> address and snoops it. Thereafter its the function of target PCI to
> give the next address addressed (in burst mode as target PCI latches
> the starting address and thenafter it increments it withinself). How
> this incremented address given to cachecontroller?
> 

        PCI cache support has largely been removed from the newer
specification (i.e., Rev. 2.2).



> 6.what is the value to be written for header type zero(ie bit[6:0]),
> header type one , and header type two in the header type register in
> configuration register ?I mean what value to be written in bit[6:0]
> for header type zero/one/two?
> 

        bit[6:0] should be equal to 000000B, 000001B, or 000010B,
depending on what you want, however, in your case, it should be 000000B
because you are not developing a PCI-to-PCI bridge or a CardBus bridge.




> 7. Where is built in self test code located whether in expansion ROM
> or where?how can you conduct a built in self test whether by doing a
> configuration write on the BIST register or how?
> 

        I didn't bother to deal with the BIST register.
You should ignore it for the time being.



> 8. what is the use Cardbus CIS pointer in configuration register? It
> is said it is implemented by devices that share silicon between
> cardbus and PCI.I didnot understand what that share silicon means? can
> please give me more information about it?
> 

        An example will be a PCI device that can be used as a CardBus
device.
A chip manufacture won't want to develop another silicon (chip) if the
PCI version and the CardBus version of such a chip is largely identical.




> 9. What is use of max_lat register in configuration register?what i
> have read is that value written in MIN_gnt register is read by BIOS
> and load the latency timer with value in terms of PCI clock to it?
> what is the use Max_lat register?Is it the priority?If so what is the
> weightage of the bit?
> 

        A target only device doesn't implement these registers.



> 10. what is this user defined features(UDF)?Can you please give me
> example for this?
> 

        I am not too familiar about that feature, so I won't comment on
it.
If you don't have to, I don't believe you have to implement it.



> 11.what is the difference between HIT and D_done in PCI target state machine?
> 

        HIT signals that the the address decoder detected an address
match.
D_done is implemented if the PCI device cannot perform medium DEVSEL#
decoding.
A PCI IP core I developed can easily decode the address in two 
clock cycles, so I didn't have to implement D_done in my implementation
(It does medium DEVSEL# decoding.).



>  waiting for Your reply
>  thank in advance
>  praveen


        Praveen, I personally think the problem you are having is that,
you are getting bogged down by trying to implement everything, and is
trying to understand every aspect of the PCI specification.
Especially in your case (Since it is a target only device.), that's not
needed.
Start implementing the basic functionality first (Configuration
Registers vital even for a target only device) before worrying about the
optional stuff.


Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)

Article: 53286
Subject: Re: Time constraint of bit-stream file
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Mon, 10 Mar 2003 11:25:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
Liao Jirong <iscp1097@nus.edu.sg> wrote:
: After I generate the bit-stream file, Xilinx tools returns two time
: constraints

: One is Default period analysis, another is Default net enumeration. 

: Which one determines the frequency of the bit-stream file?

In the ISE flow, change the properities of the bitstream generation tool
(right mouse)  

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 53287
Subject: Partial Reconfigration:Active Module of MD
From: "Eduardo Wenzel Brião" <briao@inf.pucrs.br>
Date: Mon, 10 Mar 2003 04:12:56 -0800
Links: << >>  << T >>  << A >>

Hi. 
I developed a small design to test Modular Design Flow. I designed a project used two modules. One fixed and one reconfigurable module. I followed all steps described in XAPP404 and
XAPP290. I was able to complete the first step: Initial Budgeting of Modular Design. All lower-level modules have been synthesized as black boxes, through Leonardo Spectrum software. But
when I try to perform the second step of flow (Active Module Implementation Phase of Modular Design), it happens errors. 

When I perform the command below: 
Command Line: ngdbuild -p xc2v1000fg456-4 -aul -modular module -active 
contador_A ..\..\Top\Initial\top.ngo 

It issued these errors: 
ERROR:NgdBuild:647 - instance 'cA' of module 'contador_A' has not yet been 
   defined. 
ERROR:NgdBuild:559 - Cannot find active block 'contador_A' in the design. 

What it could be happening with the Flow? 
My design is very simple. If someone want to get it to analyzed the code source in VHDL, I'll send it without any problem. 

Regard 

Eduardo Wenzel Brião 
briao@inf.pucrs.br 
Catholic University of Rio Grande do Sul State. 
Porto Alegre City - Brazil 




Article: 53288
Subject: Atmel FPGA uk
From: j.p.murphy@ncl.ac.uk (jools)
Date: 10 Mar 2003 05:54:58 -0800
Links: << >>  << T >>  << A >>
Hi

Can someone tell me where I can buy Atmel FPGA's in the UK, ive
farnell etc but they dont sell them, I also need to buy the
development kit too.

Cheers

Article: 53289
Subject: Static Tming Analysis
From: J_Jeniffer@excite.com (Jeniffer)
Date: 10 Mar 2003 06:11:34 -0800
Links: << >>  << T >>  << A >>
Hi,
When I implement the design and look at the static timing analysis
report,
I find paths which are not broken at bidirectional pin. I have given a
single constraint, of minimum clock period. The implementation tool
reports that the constraint is violated on some paths. When I look at
the paths in
the FPGA editor, they are paths which include bidirectional pads: They
start
from some internal logic, traverse to the pad (output path), fold at
the
bidirectional pin and traverse back inside (input path). My concern is
-- Can I substract the input path delay from the total delay and if 
   it is less than the clock to output delay I require, conclude that
timing
   is met?
-- Is there a way, I can tell the software that the path is to be
broken
   at bidirectional pin (though the documentation on xilinx site
mentions
   that for path analysis, paths are broken at bidirectional pad)
-- The path consumes around 10-12 ns at the pad. Is this delay o.k? Or
   can I reduce it in some way?

Thanx,
Jeniffer

Article: 53290
Subject: Re: Partial Reconfigration:Active Module of MD
From: "Emil Blaschek" <emil.blaschek@siemens.at>
Date: Mon, 10 Mar 2003 15:19:12 +0100
Links: << >>  << T >>  << A >>

You forgot the module 'contador_A' ,
You must have got a mesage like " Black Box 'contador_A'  when compiling
the Design.
  "Eduardo Wenzel Bri=E3o" <briao@inf.pucrs.br> wrote in message
news:ee7c42b.-1@WebX.sUN8CHnE...
  Hi.
  I developed a small design to test Modular Design Flow. I designed a
project used two modules. One fixed and one reconfigurable module. I
followed all steps described in XAPP404 and XAPP290. I was able to
complete the first step: Initial Budgeting of Modular Design. All
lower-level modules have been synthesized as black boxes, through
Leonardo Spectrum software. But when I try to perform the second step of
flow (Active Module Implementation Phase of Modular Design), it happens
errors.
  When I perform the command below:
  Command Line: ngdbuild -p xc2v1000fg456-4 -aul -modular module -active

  contador_A ..\..\Top\Initial\top.ngo

  It issued these errors:
  ERROR:NgdBuild:647 - instance 'cA' of module 'contador_A' has not yet
been
     defined.
  ERROR:NgdBuild:559 - Cannot find active block 'contador_A' in the
design.

  What it could be happening with the Flow?
  My design is very simple. If someone want to get it to analyzed the
code source in VHDL, I'll send it without any problem.

  Regard

  Eduardo Wenzel Bri=E3o
  briao@inf.pucrs.br
  Catholic University of Rio Grande do Sul State.
  Porto Alegre City - Brazil




Article: 53291
Subject: CF Code Examples (Was: Need help! Any experienced Handel-C user?)
From: tom1@launchbird.com (Tom Hawkins)
Date: 10 Mar 2003 06:21:45 -0800
Links: << >>  << T >>  << A >>
Hi John,

> > 
> > Give cf a try; you may like it!
> 
> Thanks.  I don't really have time at the moment - can you post some 
> Confluence "code" to generate, e.g. a counter, or a simple state machine?
> 

Here's an intro and a few code examples.

Confluence is a functional programming language--Confluence "components"
are analogous to functions in FP languages and modules (entity/arch pairs)
in HDL.

Components can have multiple inputs and multiple outputs, and are
instantiated using the following syntax:

  {ComponentExpression, InputArguments, OutputArguments}

The argument place holder ($) is used to return a value:

  A <- {Sin, 3.14, $}   (* "A" becomes a floating point number near 0.0. *)
  {Sin, 3.14, A}        (* This statement is equivalent to the previous. *)


The following creates a 4-bit register:

  {Reg, 4 DataIn, DataOut}

Confluence automatically connects CLK, CE, and RST.

Using "Reg" we can construct a counter:

  Counter <-
    comp +Width -Value
      :One
      :NextValue
      One       <- '0' '#' (Width - 1) '++' '1'   (* Constructs ..0001. *)
      NextValue <- Value '+' One
      Value     <- {Reg, Width NextValue, $}
    end

Now an 8-bit "Counter" can be instantiated:

  CountValue <- {Counter, 8, $}

Again, CLK, CE, and RST are automatically connected.


"StateMachine" is part of our Logic.cf library and is built from other low
level components.  Here is how to create a toggle (moore) machine:

  ToggleMoore <-
    comp +T -Q
      {StateMachine, [["0" 0 0 "0"]    (* input, state, nextstate, output *)
                      ["1" 0 1 "0"]
                      ["0" 1 1 "1"]
                      ["1" 1 0 "1"]] T, Q}
    end

To drop in a ToggleMoore, simply write:

  {ToggleMoore, ButtonPress, SwitchState}


Like all functional programming languages, Confluence components are
first class.  The following illustrates high-order components by implementing
a fully pipelined adder tree, using the "Tree" library component:

  AdderTreePiped <-
    comp +Elements -Result
      :BinOp :UnOp
      BinOp <- comp +A +B -X {Delay, 1 (A '+' B), X} end
      UnOp  <- comp +A -X    {Delay, 1 A, X}         end
      {Tree, BinOp UnOp Elements, Result}
    end

AdderTreePiped takes a list of signals, constructs a pipelined binary tree,
and produces the resulting signal.

  {AdderTreePiped, [Sig1 Sig2 Sig3 Sig4 Sig5], SigResult}

Notice the flexibility of "AdderTreePiped": it handles any signal precision
and any length input list.  The instantiated system can also be assigned
an independent clock domain, or locally enabled or reset.

You'll find several code examples in the Confluence installation, including
the FFT and CORDIC cores.

Regards,
Tom

--
Tom Hawkins                             tom1@launchbird.com
Launchbird Design Systems, Inc.         http://www.launchbird.com/

Article: 53292
Subject: Re: Multipliers Architectures use on FPGA COREGEN
From: Ray Andraka <ray@andraka.com>
Date: Mon, 10 Mar 2003 14:49:33 GMT
Links: << >>  << T >>  << A >>
They use the computed partial products scheme discussed on the
multipliers page on my website.

JDS wrote:

> Hi all,
>
> I'd like to know which multiplication schemes (among Wallace, Booth,
> shift-add, etc) are used on Xilinx CoreGen modules, taking in account
> the speed vs area tradeoff. Or if those generated modules use more
> technology specific features like fast-carry chains, RPM, LUT, etc.
>
> Thank you in advance,
> JDS

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53293
Subject: Re: Motion Control IP Cores , anyone do them ?
From: Ray Andraka <ray@andraka.com>
Date: Mon, 10 Mar 2003 14:54:59 GMT
Links: << >>  << T >>  << A >>
Yes, quite possible.  We've done such designs in the past using Xilinx 4K and
earlier parts.  The exact requirements tend to be process specific, so each
design is pretty much a custom design.  I'm sure most of the consultants
listed in the Xilinx or Altera expert consultants listings could  handle this
for you.

"=·MoLe=" wrote:

> Hi all,
>
> Absolute newbie to Fpga's, I am looking at building a high speed 3D
> router/engraver, based on step & direction  input AC servo's.
> I'm looking for what is essentially a variable frequency pulse generator,
> from 1 to about 600Khz, a few 32 bit counters, acceleration
> generation, linear & circular interpolation , a few inz and outz for limit
> switches etc, There are plenty of motion control ASIC vendors
> out there but none of them seem to be just what i need. Is an Fpga
> implementation for this type of function possible ? are there any vendors
> that
> do this sort of stuff ?
>
> Any help / advice would be most welcome.
>
> Thanks.
>
> Martin Vellemax.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53294
Subject: Re: Timing Simulation Glitches
From: "Andre Powell" <andre.powell@ntlworld.com>
Date: Mon, 10 Mar 2003 15:11:59 -0000
Links: << >>  << T >>  << A >>
HI Lijo,
If you are simulating with Modelsim you can turn off the glitch detection
using -noglitch as one of the simualation options.

Best Regards

Andre'
"LIJO" <lijo_eceNOSPAM@hotmail.com> wrote in message
news:b4hhdm$1u7l6h$2@ID-159866.news.dfncis.de...
> Hi all,
>   I am trying to implement a logic into FPGA. I have functionally verified
> the logic and have synthesised the logic and verfied the post synthesis
> simulation output.
> After Implementation I have done the Timing Simulation with SDF files and
> have found a lot of  invalid transitions between transition from one valid
> state to another valid state. I have no idea why this happens.. Is there
any
> problem if I download the code to the FPGA . Will it work properly.
>
> Please see the attached file.
>
> thanks
> Lijo
>
>
>



Article: 53295
Subject: Re: Motion Control IP Cores , anyone do them ?
From: "=·MoLe=" <flumpah@yahoo.com>
Date: Mon, 10 Mar 2003 15:28:04 -0000
Links: << >>  << T >>  << A >>
Thanks very much for responding to this post, I will get myself a FPGA dev
board and have a go!

Thanks all.
Martin Vellemax



Article: 53296
Subject: Re: conditional `include
From: Ken McElvain <ken@synplicity.com>
Date: Mon, 10 Mar 2003 15:41:25 GMT
Links: << >>  << T >>  << A >>
I've included an example.   I did have to change one thing.
For some reason our black box file .../synplicity722/lib/xilinx/virtex2.v
is missing the parameters for the block rams so I had to
make my own black box shell.   The black box shell
should go in a separate file that is included only for
synthesis.   For simulation you would want to use the
Xilinx model.  I'm going to pass the missing
parameter statements problem on to the dev team.

- Ken


// Shell for Block ram that lists parameters and ports
// This should be placed in a separate file which is used
// only for synthesis
module RAMB16_S4(DO, ADDR, DI, EN, CLK, WE, SSR);
/* synthesis syn_black_box */
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
output [3:0] DO;
input [11:0] ADDR;
input [3:0] DI;
input EN;
input CLK;
input WE;
input SSR;
endmodule


module mytop(DO, ADDR, DI, EN, CLK, WE, SSR);
output [3:0] DO;
input [11:0] ADDR;
input [3:0] DI;
input EN;
input CLK;
input WE;
input SSR;

RAMB16_S4 r1(DO, ADDR, DI, EN, CLK, WE, SSR);

defparam r1.INIT_00
  256'hffffeeeeddddccccbbbbaaaa9999888877776666555544443333222211110000;

endmodule



Kevin Neilson wrote:

> Ken,
> That would be great, but I'm not sure how it works.  I found an old design
> in which I initialize blockRAM using both defparams and the 'xc_props'
> comments, and I deleted the comments and synthesized on 7.2.2.  I found that
> there were no initialization data in the EDIF netlist when I did that, but
> that the init data reappeared when I put the comments back in.  Am I doing
> something incorrectly?  I couldn't find any hints on the Synplicity website
> or in the release notes.
> -Kevin
> 
> "Ken McElvain" <ken@synplicity.com> wrote in message
> news:3E694B85.1070406@synplicity.com...
> 
>>
>>Kevin Neilson wrote:
>>
>>
>>>When using Synplify, you have to specify the initial contents twice:
>>>
> using
> 
>>>defparams (for the simulator) and using comments (for Synplify).
>>>
> Synplify
> 
>>>won't read the defparams for RAM initialization.  I think XST works
>>>
> exactly
> 
>>>the same way, according to this solution on the Xilinx website:
>>>
>>
>>Try Synplify 7.2.2, it supports defparams as a way to send properties on
>>black boxes into the EDIF.   This way you don't have to duplicate the
>>INIT info.  It should work for both synthesis and simulation.
>>
>>
>>
>>>
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
> 
>>>1&getPagePath=10695
>>>
>>>-Kevin
>>>
>>>"Paulo Dutra" <paulo@xilinx.com> wrote in message
>>>news:3E665040.225B2306@xilinx.com...
>>>
>>>
>>>>The RAMB models use the Verilog "parameter" to initialize the INIT
>>>>
>>>>
>>>strings.
>>>
>>>
>>>>Since defparams are based on the scope hierarchy, you would need to know
>>>>the location of the Rambs in your design.
>>>>
>>>>This would work for synthesis/simulation, as XST does read defparams.
>>>>
>>>>
>>>>
>>>>>$readmem would work for simulation, but not synthesis.  The only
>>>>>synthesizable way to initialize a blockRAM in a Xilinx that is is to
>>>>>
> use
> 
>>>>>comments or a particular syntax that the synthesizer passes on to the
>>>>>place&route tool.  The FPGA synthesizers aren't yet smart enough to use
>>>>>$readmem; they just ignore it completely.
>>>>>
>>>>>
>>>>--
>>>>/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
>>>>\ \ `  Xilinx                              hotline@xilinx.com
>>>>/ /    2100 Logic Drive                    http://www.xilinx.com
>>>>\_\/.\ San Jose, California 95124-3450 USA
>>>>
>>>>
>>>
> 
> 


Article: 53297
Subject: Re: Atmel FPGA uk
From: "Jonathan Bromley" <jonathan.bromley@doulos.co.uk>
Date: Mon, 10 Mar 2003 16:07:33 -0000
Links: << >>  << T >>  << A >>
"jools" <j.p.murphy@ncl.ac.uk> wrote

> Can someone tell me where I can buy Atmel FPGA's in the UK, ive
> farnell etc but they dont sell them, I also need to buy the
> development kit too.

Take a look at http://www.gd-technik.com/

I don't specifically endorse that company, although I've had
good service from them in the (distant) past.  And there may
well be other Atmel distis in the UK - I would have thought
that the Atmel website would help out...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Article: 53298
Subject: Chip release dates
From: "Stephen Melnikoff" <s.j.melnikoff@REMOVE-THIS-BIT.iee.org>
Date: Mon, 10 Mar 2003 16:41:13 -0000
Links: << >>  << T >>  << A >>
Hi.

Can anyone confirm that these are the correct years in which the following
chips were released? By released, I mean actually in general production and
available to the public.

Virtex: 1998
Virtex-E: 1999
Virtex-II: 2001
Virtex-II Pro: 2002;

Pentium III 450: 1999
Athlon XP 2000+: 2002

Thanks,

Steve Melnikoff
--
Steve Melnikoff - s.j.melnikoff@REMOVE-THIS-BIT.iee.org




Article: 53299
Subject: Re: Static Tming Analysis
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 10 Mar 2003 16:47:32 GMT
Links: << >>  << T >>  << A >>
"Jeniffer" <J_Jeniffer@excite.com> wrote in message
news:ded21c45.0303100611.2feda73a@posting.google.com...
<snip>
> -- Is there a way, I can tell the software that the path is to be
> broken at bidirectional pin
<snip>

When you open the timing analyzer (rather than relying only on the report
generated after place & route) you can select the menu item "Analyze" and
choose "Against Timing Constraints..." (the menu brings up options, the
button does not).  The "Path Tracing" tab lists several path types.  If your
I/O Output to Input is checked, this is where you can turn it off.  If it
isn't checked, I'm not sure what your timing report is telling you.





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search