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Is there anyone ever tried to resynthesize the standard cell ASIC netlist (Verilog) targeting to Xilinx FPGA using FPGA synthesizer (e.g. Synplicity/Exemplar)? ASIC Verilog netlist is merged with synthesizable Verilog RTL model of the cell libraries to yield a complete synthesizable Verilog. How's the quality of the result comparing with direct RTL sysnthesis? Is there anyone from Synplicity/Exemplar can answer this question? TIA HT ChangArticle: 57976
Hi Jared, There are 2 variable which you can set to prevent this behaviour, they are "append_generics_to_blackbox" and "append_generic_to_toplevel. Settings these variables to 0 should solve your problem. You can also use the "move" command to rename the instance. Regards, Hans. www.ht-lab.com "Jared" <jaz_shnat@hotmail.com> wrote in message news:98bc4967.0307082238.2879b984@posting.google.com... > Hey, > > I'm trying to create a 20-bit pipelined adder using the lpm_add_sub > megafunction, but when I try and compile my project in leonardo it > changes the name in the .edf file from lpm_add_sub to > lpm_add_sub_20_add_no_5 which Altera Max+PLUS does not recognize. In > order for it to place and route correctly, I have to manually change > the name back to lpm_add_sub. Does anybody know if there is a way to > prevent this from happening. I've already tried setting the noopt and > dont_touch attribute in the architecture block. > > Thanks in Advance, > Jared HolzmanArticle: 57977
After meaningless changes the code gives tristate buffers under Foundation.
See below - changed lines are commented out.
Dz.
-- VHDL created by Rick Collins
-- modified by Dziadek
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.STD_LOGIC_ARITH;
ENTITY Test1 is
PORT (
-- ADC Board Signals
Data : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
CSN : IN STD_LOGIC;
RDN : IN STD_LOGIC;
WRN : IN STD_LOGIC;
LED : OUT STD_LOGIC;
Reset : IN STD_LOGIC;
SysClk : IN STD_LOGIC); -- 50 MHz Clock
END Test1;
ARCHITECTURE behavior OF Test1 IS
constant SysClkRate : real := 50000.0; -- Rate in KHz
signal DataIn : STD_LOGIC_VECTOR (7 downto 0);
signal DataOut : STD_LOGIC_VECTOR (7 downto 0);
signal ScratchReg : STD_LOGIC_VECTOR (7 downto 0);
signal ReadScratchReg : STD_LOGIC;
attribute keep: boolean;
attribute keep of DataIn: signal is true;
attribute keep of DataOut: signal is true;
attribute keep of ReadScratchReg: signal is true;
BEGIN
ReadScratchReg <= (not RDN) WHEN (Addr = "00001000") and (CSN = '0')
ELSE '0';
Data <=
DataOut WHEN (ReadScratchReg = '1')
-- ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z');
ELSE (others => 'Z');
-- DataIn <= Data;
DataOut <= ScratchReg;
ScratchRegister: process (SysClk, Reset) begin
if (Reset = '1') then
ScratchReg <= (others => '0');
elsif (rising_edge(SysClk)) then
if (Addr = "00001000") THEN
if (WRN = '0' and CSN = '0') THEN
-- ScratchReg <= DataIn (7 downto 0);
ScratchReg <= Data (7 downto 0);
end if;
end if;
end if;
end process ScratchRegister;
LED <= ScratchReg(0) AND ReadScratchReg;
END behavior;
Article: 57978"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F0DC966.43F838F6@yahoo.com... > When I compile my program I get a warning on the range of these two > constants under Quartus 3.0 web edition. I checked some other copies of > NUMERIC_STD that I have on my hard drive and found them all to be the > same. What is this about? What are these constants for and why are > they defined this way? Should this report as a warning? > > package body NUMERIC_STD is > > -- null range array constants > > constant NAU: UNSIGNED(0 downto 1) := (others => '0'); > constant NAS: SIGNED(0 downto 1) := (others => '0'); > > From my days of C programming, I am uncomfortable with warning > statements. If there are warnings, even if they are not problems, I get > rid of them so that they don't obscure warnings about *real* problems. > I've had warnings about these from Leonardo Spectrum as well. I believe they are deliberately declared to represent "not a number" for unsigned and signed vectors. For instance if you look at the overload for + that takes unsigned left and right arguments and returns unsigned, the function checks if either of the arguments has a length less than 1, and returns NAU if so. I personally don't think it should be a warning, as it's quite legal to declare null vectors - however I guess it would require more careful perusal of the standard to be absolutely sure, regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 57979
Hi ! I have a question about DDS. I discovered that most of DDS application in SDR use the SFDR factor around 60dBc and frequency resolution around 1 Hz. Why is so, and Why don't use SFDR around 120 dBc and freq. resolution about 0.02 Hz. Yes I know there is a space trade-off and I wan to know how to decide parameters I need for my specific application. Thanks, SasaArticle: 57980
"Peter Alfke" <peter@xilinx.com> wrote in message news:3F0CB323.4D275C37@xilinx.com... > In the 'sixties, the Wang calculators ( with Nixie-tube read-out) did > just that. I think they used a very efficient algorithm for log and antilog > Peter Alfke I did use a Wang calculator around 1974 or so, which I think used Nixie tubes. I have an HP 9810A, which I believe was competition for some of the Wang calculators. When I got it it was pretty dirty inside, it might have been rained on. I took it apart, carefully washed and dried all the parts, and put it back together. The one thing that doesn't work is the on/off switch, so I bypassed that. Just to get back on the subject, I did think about tracing the logic, writing it in verilog, and programming an FPGA to do it. It probably wouldn't take too big of FPGA to fit it all in. The microcode is 256x28, seven TTL PROMs. The program ROMs are somewhat bigger, but still pretty small. Implementing a thermal printer and magnetic card reader in an FPGA is still pretty hard, though. It would be interesting to know more about that algorithm, and its possible implementation in an FPGA. -- glenArticle: 57981
> I found this on xilinx website: > http://www.xilinx.com/support/programr/files/0380507.pdf > > Seems to be what I need (it's different from the cable I got...specially for > the feedback signals). However, I'm wondering about the power supply. The > parallel port is 5V and my XC18V02 is 3.3V. Do I simply supply the 74HC125 > with 3.3V and hope the parallel port will work with that ? more than 3.3V signal levels are never required, sometimes higher levels may destroy the inputs. So any circuitry that eliminites a possibility of smoke coming from computer or FPGA would do fine. I was real lazy so used the same schematics but replaced the buffers with series currentlimiting resistors, and it works also. with buffers will also work. anttiArticle: 57982
Hello, I have a design for the VIRTEX -II chip with two I/O standards (3.3V and 2.5V). Selected banks have switching I/O voltage after configuration. The voltage depends on project type. One VIRTEX configuration has 3.3V standard and other configuration has 2.5V standard. I have to switch the appropriate voltage after configuration of the VIRTEX. My problem is if I can switch the I/O voltage form 3.3V to 2.5V after configuration of the VIRTEX with I/O (input, output and input-output) pasd's standard set to 2.5V? In this case selected VCCO power pins will have 3.3V for several mil. seconds. Is the opposite situation possible when I have default 2.5V VCCO? Then I switch form 2.5V to 3.3V after configuration (project have 3.3V I/O standard and VIRTEX pins are connected to other system pins with 3.3V). Regards, KrzysiekArticle: 57983
It might not be so bad... The latest Platform Flash PROMs announced support for ALL Xilinx FPGAs, and I did read in one of the customer presentations that it supports SpartanXL, though there were no documents or such claims when I searched the website. I have this requirement for one of my customers too... I'll try to find out more, but if anybody else knows about this, please enlighten us. --Neeraj "Spam Hater" <spam_hater_7@email.com> wrote in message news:dtgsgv08qo38jbsomsde27v77b9pj4bul1@4ax.com... > > If the little XC18V's will do it, the big ones will too. Just ignore > the extra bits. The Spartan will stop clocking when it's done. > > What you're really looking for doesn't exist, and won't. The Spartan > and the SpartanXL are dead parts (in Xilinx's view). > > Sorry, > SH > > On Thu, 10 Jul 2003 12:36:57 +0930, Anup Kumar Raghavan > <araghava@asc.corp.mot.com> wrote: > > >I need to select a Configuration solution for programming the Spartan XL > >XCS10XL device. I have chosen to use the Master Serial Mode > >configuration using the PROM XC17S10XL, which is OTP. I havent found any > >reference to ISP (EPROM) solutions for the Spartan XL and hence need > >some advice on this. I know there is this device XC18V256PC20C, but > >Xilinx mentions that this is not supported anymore. > > > >Thanks and regards > >Anup >Article: 57984
Does anyone see a weakness in this circuit? (inputs,outputs in capital)
What if I put a timing ignore attribute on restrig?
It should create a one clock pulse in the NEWCLK domain when OLDCLK rises.
-----
signal trig,restrig,delrestrig,
if(restrig='1') then
trig<='0';
elsif(OLDCLK'event and OLDCLK='1') then
trig<='1';
end if;
if(NEWCLK'event and NEWCLK='1') then
restrig<=trig;
delrestrig<=restrig;
if(delrestrig='0' and restrig='1') then --Positive edge detector
OUTTRIG='1';
else
OUTTRIG='0';
end if
end if;
---------
Article: 57985lecroy <lecroy7200@chek.com> wrote: > If the code were structured, supporting the older devices would not be > a problem. Can you tell us why it's such a hardship to use an older tool version? Don't say they don't co-exist, because that's not true. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57986
Hello everyone, I can't use Foundation 4.2 Aldec simulator to simulate CLKFX, no matter what I set the M and D, the CLKFX is always 4x. The "Answer Record # 11736" doesn't help much. What kind of simulator do I need to work with Foundation SW? pleaseArticle: 57987
Why did you have to make those changes? The first one (removing the type cast STD_LOGIC_VECTOR (7 downto 0)') seems to be what makes it work here. I take it under ISE it also did not work with the type cast in? I think I put that in because I vaguely recalled there were some problems with not being able to figure out the width of the others. Like I said, it has been awhile... Thanks for the help. Dziadek wrote: > > After meaningless changes the code gives tristate buffers under Foundation. > See below - changed lines are commented out. > > Dz. > > -- VHDL created by Rick Collins > -- modified by Dziadek > Library ieee; > Use ieee.std_logic_1164.all; > Use ieee.numeric_std.all; > Use ieee.STD_LOGIC_ARITH; > > ENTITY Test1 is > PORT ( > -- ADC Board Signals > Data : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); > Addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); > CSN : IN STD_LOGIC; > RDN : IN STD_LOGIC; > WRN : IN STD_LOGIC; > > LED : OUT STD_LOGIC; > > Reset : IN STD_LOGIC; > SysClk : IN STD_LOGIC); -- 50 MHz Clock > END Test1; > > ARCHITECTURE behavior OF Test1 IS > > constant SysClkRate : real := 50000.0; -- Rate in KHz > signal DataIn : STD_LOGIC_VECTOR (7 downto 0); > signal DataOut : STD_LOGIC_VECTOR (7 downto 0); > signal ScratchReg : STD_LOGIC_VECTOR (7 downto 0); > signal ReadScratchReg : STD_LOGIC; > > attribute keep: boolean; > attribute keep of DataIn: signal is true; > attribute keep of DataOut: signal is true; > attribute keep of ReadScratchReg: signal is true; > > BEGIN > > ReadScratchReg <= (not RDN) WHEN (Addr = "00001000") and (CSN = '0') > ELSE '0'; > > Data <= > DataOut WHEN (ReadScratchReg = '1') > -- ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z'); > ELSE (others => 'Z'); > > -- DataIn <= Data; > DataOut <= ScratchReg; > > ScratchRegister: process (SysClk, Reset) begin > if (Reset = '1') then > ScratchReg <= (others => '0'); > elsif (rising_edge(SysClk)) then > if (Addr = "00001000") THEN > if (WRN = '0' and CSN = '0') THEN > -- ScratchReg <= DataIn (7 downto 0); > ScratchReg <= Data (7 downto 0); > end if; > end if; > end if; > end process ScratchRegister; > > LED <= ScratchReg(0) AND ReadScratchReg; > > END behavior; -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57988
Alan Fitch wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F0DC966.43F838F6@yahoo.com... > > When I compile my program I get a warning on the range of these two > > constants under Quartus 3.0 web edition. I checked some other > copies of > > NUMERIC_STD that I have on my hard drive and found them all to be > the > > same. What is this about? What are these constants for and why are > > they defined this way? Should this report as a warning? > > > > package body NUMERIC_STD is > > > > -- null range array constants > > > > constant NAU: UNSIGNED(0 downto 1) := (others => '0'); > > constant NAS: SIGNED(0 downto 1) := (others => '0'); > > > > From my days of C programming, I am uncomfortable with warning > > statements. If there are warnings, even if they are not problems, I > get > > rid of them so that they don't obscure warnings about *real* > problems. > > > > I've had warnings about these from Leonardo Spectrum as well. > I believe they are deliberately declared to represent "not a number" > for unsigned and signed vectors. For instance if you look at > the overload for + that takes unsigned left and right arguments and > returns unsigned, the function checks if either of the arguments has > a length less than 1, and returns NAU if so. > > I personally don't think it should be a warning, as it's quite legal > to declare null vectors - however I guess it would require more > careful > perusal of the standard to be absolutely sure, > > regards > > Alan The bad thing about how Quartus handles it is that it *reverses* the values in the range to make it 1 downto 0 rather than making a null array. I hope this does not create problems later. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57989
Morten Leikvoll wrote:
>
> Does anyone see a weakness in this circuit? (inputs,outputs in capital)
> What if I put a timing ignore attribute on restrig?
> It should create a one clock pulse in the NEWCLK domain when OLDCLK rises.
I have used a design similar to this that does not require async reset
of the FFs. But I see nothing wrong with your design depending on the
rate of the pulse and the clocks.
signal trig,restrig,delrestrig,
if(RESET='1') then
trig <= '0';
elsif(OLDCLK'event and OLDCLK='1') then
trig <= not retrig;
end if;
if(NEWCLK'event and NEWCLK='1') then
restrig<=trig;
delrestrig<=restrig;
if(delrestrig xor restrig) then -- Any edge detector
OUTTRIG='1';
else
OUTTRIG='0';
end if
end if;
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 57990hamish@cloud.net.au wrote: > > lecroy <lecroy7200@chek.com> wrote: > > If the code were structured, supporting the older devices would not be > > a problem. > > Can you tell us why it's such a hardship to use an older tool version? > > Don't say they don't co-exist, because that's not true. There are a lot of issues concerning co-compatibility. I have seen older software that won't run under the newer OS and the newer software is not supported under the older OS. Even those issues aside, it is hard to maintain proficiency on the older tools since they change the GUI and even the synthesis tool every few years. This can make it very hard to maintain an older design since under a newer tool a design can get much larger. But if you try to run the older tools, they require different tweeks to get a design to run at all. Of cource this can be dealt with by good documentation of each design, but often there are a number of little quirks that no one thinks of putting in the documentation at the time since it is just part of running the tool at the time. I have been there, done that! Try getting an answer from FPGA support on a five year old tool! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57991
Hi fellows I want to compile multiple *.vhd files one by one using Makefile and I have done for single file but not for multiple . I want to generate one *.rbt files after compiling all *.vhd at the same time one by one using make file. Any help would be highly appreciated. cheers Macei'Article: 57992
Hi VHDL GNU men, Amontec is interested to build an auto-documentation of our VHDL libraries, cell-by-cell. The documentation will stay basic, like : general description port description generic description implementation description license description note description The goal is to do a interface documentation for the end-user. Now, we know the power of XML for this kind of documentation. The advantage of XML is the structural view like VHDL. Having a VHDL library documented in a XML format, we will be able to describe the hardware of a SoC very quickly, and to ask XML to re-generate a VHDL concatenated file of our XML description ... oopps) The start-point will becomes the end-point (VHDL bottom-up design to XML up-down design) I will be interested if some VHDL men have a VHDL to XML parser, thinking documentation only. Or is that better to do a parser to correct my VHDL libraries inserting directly the XML format in the vhdl comment. Let me know if some are interested to work with Amontec on this JOB. Laurent Gauch Amontec Team Manager www.amontec.comArticle: 57993
Peter, In which package for the XC3S1000 sample? Thanks Laurent www.amontec.com Peter Alfke wrote: > Check with your distributor. The XC3S50J ( that is the one without > BlockRAM and DCM) should be available, and the price will not break > anybody's budget... > The XC3S1000 is also available, but in much tighter supply. The rest is > coming soon. > Peter Alfke > =========== > rickman wrote: > >>millim wrote: >> >>>Hi, >>> >>>I have a question on Spartan-3 devices. Does anybody know if there is >>>a possibility to request some free samples if those devices. >> >>Not likely. Xilinx does not provide *free* samples to the best of my >>knowledge. >> >>-- >> >>Rick "rickman" Collins >> >>rick.collins@XYarius.com >>Ignore the reply address. To email me use the above address with the XY >>removed. >> >>Arius - A Signal Processing Solutions Company >>Specializing in DSP and FPGA design URL http://www.arius.com >>4 King Ave 301-682-7772 Voice >>Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57994
John Pham wrote: > If anyone interest in a FPGA DIMM module using Xilinx Virtex (XCV600) with > 512K SRAM, onboard 10/100 Ethernet + Flash + JTAG/ROM/CPLD and 16bit PCM > Codec please email me. The board size is 5.25" x 3" 168 pins DIMM module. > The next batch of production run is due in 3 weeks, bare board PCB and semi > assemble board are available now > Interesting, did you have a reference page ? Laurent www.amontec.comArticle: 57995
rickman wrote: > I have been away from VHDL for a while since my last few projects were > Verilog. Now I am trying to get Quartus working (which I am not overly > familiar with either) and my simple test program won't give me the > hardware I want. It is not making the tristate buffers and connecting > them up like they should. I expect I am doing something very simple > wrong, but I have been looking at this code for hours as well as putting > in all sorts of things to try to show me my problem. But it keeps doing > the same thing, no tristate buffers (well, they are there, but they are > not driven with anything). > > I added some "KEEP" directives to try to force it to retain some of the > signals and now it *tells* me it is deleting them. But it is still the > same result. Here is the full code. Everything other than the register > read and write logic is added to try to debug something. The only > register bit that is synthesized is bit 0 and both the signal and the > control inputs to the tristates are ground. > > I am guessing that it has something to do with the fact that the INOUT > is both the input and the output of the register and the tristates. Or > do I need to do something special for chip IOs? > > > -- VHDL created by Rick Collins > Library ieee; > Use ieee.std_logic_1164.all; > Use ieee.numeric_std.all; > Use ieee.STD_LOGIC_ARITH; > > ENTITY Test1 is > PORT ( > -- ADC Board Signals > Data : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); > Addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); > CSN : IN STD_LOGIC; > RDN : IN STD_LOGIC; > WRN : IN STD_LOGIC; > > LED : OUT STD_LOGIC; > > Reset : IN STD_LOGIC; > SysClk : IN STD_LOGIC); -- 50 MHz Clock > END Test1; > > ARCHITECTURE behavior OF Test1 IS > > constant SysClkRate : real := 50000.0; -- Rate in KHz > signal DataIn : STD_LOGIC_VECTOR (7 downto 0); > signal DataOut : STD_LOGIC_VECTOR (7 downto 0); > signal ScratchReg : STD_LOGIC_VECTOR (7 downto 0); > signal ReadScratchReg : STD_LOGIC; > > attribute keep: boolean; > attribute keep of DataIn: signal is true; > attribute keep of DataOut: signal is true; > attribute keep of ReadScratchReg: signal is true; > > BEGIN > > ReadScratchReg <= (not RDN) WHEN (Addr = "00001000") and (CSN = > '0') ELSE '0'; > > Data <= DataOut WHEN (ReadScratchReg = '1') > ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z'); > > DataIn <= Data; > DataOut <= ScratchReg; > > ScratchRegister: process (SysClk, Reset) begin > if (Reset = '1') then > ScratchReg <= (others => '0'); > elsif (rising_edge(SysClk)) then > if (Addr = "00001000") THEN > if (WRN = '0' and CSN = '0') THEN > ScratchReg <= DataIn (7 downto 0); > end if; > end if; > end if; > end process ScratchRegister; > > LED <= ScratchReg(0) AND ReadScratchReg; > > END behavior; > > For myself, I never use both ieee.numeric_std.all and ieee.STD_LOGIC_ARITH together ... can produce many troubles since there describe same functions. It is very dangerous, because the compiler or syntheziser can interprete different things. For your code, why ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z'); and not ELSE (others => 'Z'); maybe this casting can be not so nice, try to skip it, you very don't need that! Laurent Gauch www.amontec.com ------------ And now a word from our sponsor --------------------- For a secure high performance FTP using SSL/TLS encryption upgrade to SurgeFTP ---- See http://netwinsite.com/sponsor/sponsor_surgeftp.htm ----Article: 57996
> "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F0DC966.43F838F6@yahoo.com... > > When I compile my program I get a warning on the range of these two > > constants under Quartus 3.0 web edition. I checked some other > copies of > > NUMERIC_STD that I have on my hard drive and found them all to be > the > > same. What is this about? What are these constants for and why are > > they defined this way? Should this report as a warning? > > > > package body NUMERIC_STD is > > > > -- null range array constants > > > > constant NAU: UNSIGNED(0 downto 1) := (others => '0'); > > constant NAS: SIGNED(0 downto 1) := (others => '0'); > > "Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<belqfe$rna$1$8300dec7@news.demon.co.uk>... > I personally don't think it should be a warning, as it's quite legal > to declare null vectors - however I guess it would require more > careful > perusal of the standard to be absolutely sure, > The compiler is complaining because of the range (0 downto 1) and 0 is less than 1, right? Alan Nishioka alann@accom.comArticle: 57997
HT Chang wrote: > Is there anyone ever tried to resynthesize the standard cell ASIC netlist > (Verilog) targeting to Xilinx FPGA using FPGA synthesizer (e.g. > Synplicity/Exemplar)? > ASIC Verilog netlist is merged with synthesizable Verilog RTL model of the > cell libraries to yield a complete synthesizable Verilog. > How's the quality of the result comparing with direct RTL sysnthesis? > Is there anyone from Synplicity/Exemplar can answer this question? > TIA > HT Chang > > We did this JOB before, and I saw no difference between the RTL post-synthesis result and the standard cell ASIC netlist post-synthesis result. By my experience, I think the standard cell ASIC netlist post-synthesis result will stay better than RTL post-synthesis result, all is depending on the 'how' your RTL code was written, on which 'Hardware Abstraction Level' it was written. To know the true, you have to try both synthesis. But if you are thinking your RTL is good enough (low HAL), keep the RTL solution : - better for debug - better for code reuse - better for future - ... Amontec Team www.amontec.com (The future will be code reuse, do today reusable code)Article: 57998
Alan Fitch wrote:
>
> I personally don't think it should be a warning, as it's quite legal
> to declare null vectors
I agree.
A bad assignment to a null vector will cause other errors.
A null vector declaration alone is innocuous.
If one bit is 0 to 0 then
no bits must be 0 to -1
Let's see:
-------------------
entity null_string is
end null_string;
architecture sim of null_string
is
constant null_vec : std_logic_vector := "";
constant one_vec : std_logic_vector := "0";
constant two_vec : std_logic_vector := "00";
begin
what : process is
begin
report "null_vec is "& integer'image(null_vec'left)
& " to "& integer'image(null_vec'right);
report " one_vec is "& integer'image( one_vec'left)
& " to "& integer'image( one_vec'right);
report " two_vec is "& integer'image( two_vec'left)
& " to "& integer'image( two_vec'right);
wait;
end process what;
end sim;
--VSIM 1> run
--# ** Note: null_vec is 0 to -1
--# ** Note: one_vec is 0 to 0
--# ** Note: two_vec is 0 to 1
------------------------
I suppose that null vectors are rare as signals
but null vector constants and variables are necessary to make
clean vector functions.
--Mike Treseler
Article: 57999Amontec Team wrote: > > For myself, I never use both ieee.numeric_std.all and > ieee.STD_LOGIC_ARITH together ... can produce many troubles since there > describe same functions. It is very dangerous, because the compiler or > syntheziser can interprete different things. > > For your code, why > ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z'); > > and not > ELSE (others => 'Z'); > > maybe this casting can be not so nice, try to skip it, you very don't > need that! I need to sit back down with my books! It has been so long since I have written VHDL that I don't remember what all the libraries do. I do remember that you want to use numeric_std rather than the Synopsis signed and unsigned libraries. The type cast was held over from where I started with this example. I started with a 16 bit data bus and an 8 bit register. I had it written to force the unused bits to 0 like this... Data <= STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z') & ScratchReg; This is the sort of thing that is not always obvious in VHDL since the strong typing can get in the way of what you want to do. I remember that aggregates and concatenation could give errors very easily between the language *features* and the compiler bugs. Now my work is to build this up into a useful circuit while mapping out all the quirks of the tools. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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