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"PO Laprise" wrote: > I have seen much conflicting advice w.r.t timing constraints on this > newsgroup, and I was hoping that the proponents of both camps might > make explicit their reasons so that others (meaning I ;) can benefit > from their experience. Sometimes you use over constraining to force the tools to produce a certain layout or routing. For example, a 100MHz design where you take a data path and call for something like a 600ps MAXDELAY. There are only a few ways to accomplish this. You are effectively saying that you want the tools to use short routing lines as well as close packing of data path elements. Another case might be --a bit of conjecture here-- a design where you have not taken the time to fully constrain all paths. This meaning that there might be multi-cycle paths as well as flat out TIG's. These paths and those that truly must make timing will compete for routing/placement. By over constraining you might be able to ensure that design iterations (as the project evolves) don't necesarily break the important paths. Like I said, this might be stretching things a bit, but I've definetly seen designs that don't work when constrained according to exact period values suddenly work very well when over-constrained just a tad. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63751
Hi I have a design in which ADC data is clocked into a Virtex II using a clock provided by the ADC chip. The ADC data lags the rising edge of the ADC clk by 13 ns. In order to compensate for this delay, I use a fixed phase shift in a DCM to generate the clock on which the data is registered and the internal logic runs. After registering and processing the ADC data, I send it off the Virtex to external SRAM chips which are clocked by the DCM'ed and phase shifted version of the adc clk. I would like to create the constraint that data to the SRAM must be valid 5 ns after the clk edge of the internal adc_clk (which has been DCM'ed and phase shifted). I tried as shown below: TIMEGRP "SRAM_DATA" OFFSET = OUT 5 ns AFTER "pad_adc_clk" The Xilinx timing ananlysis tools take the phase shift into account, reporting errors in the post map static timing. The phase shift in the DCM shows up in the fact that the source clock is reported as being at 6.5ns instead of 0ns. This makes perfect sense. My question is this: what is the best way to create an OFFSET OUT constraint that takes the phase shift into account? Should I add 6.5 ns onto my original constraint (ie. "out 11.5 ns after pad_adc_clk") ? I can't use the clk0 output of the DCM instead of "pad_adc_clk" because "An OFFSET specification must use a pad signal to designate the clock" (quoted from Xilnx ISE error message ;) ) Many thanks Sam --Article: 63752
Marcus Svensson <NoTheSpamMosnterWillNotHaveMyMail@no.com> wrote: > When i try to add signals to the Wave window Modelsim freeks out creating > a corrut call stack error. WHY? and any ideas on how to fix that? BTW i'm > running Windows XP.. Start the ModelSim in the command line (vsim) and when it crashes it'll give something like this: ** Fatal: vsim is exiting with code X. If the X is 7, then deleting "vsim.wlf" file might help. (The log file is locked by a previously crashed vsim). If the X is 11, then solution might be trickier. Booting sometimes helps, but once the reason was that vsim was not compliant with my NVidia display card! Quality SW. Check also all error messages carefully (in elaboration and when crashing). Vsim can crash if some of the files are missing. -- Tero Rissa tpr at doc ic ac ukArticle: 63753
*** french version below *** Hello all, When I use the loadfpga function to load a .bit (for example a null bitstream gived by xilinx) to the board there is no problem. But with the same .bit file using XHWIFDemo, XHWIF or BoardScope I get the following error : "Error Configuring the Bitstream. Exiting" or with XHWIF : "Downloading bitstream to device 0 (one packet at a time). <DUMMY> Could not download bitstream packet 0 to device 0. Exiting. (-4097)" The error 4097 from RC1000pp api correspond to INTERNAL_ERROR : error while talking to driver. I don't have the source code from the rc1000pp.dll, so I can't know more about the error. The connection with the board and the resetting are ok (I don't get any error). Some more information: os : Windows NT pentium II 500 128 Mo RAM So if anybody can help me I will be very very grateful to him, Regards Barthélémy von Haller student at the EPFL (Switzerland) *** french version *** Bonjour tout le monde, Quand j'utilise la fonction loadfpga pour loader un .bit (par exemple un bitstream vide fourni par xilinx) sur la carte il n'y a aucun problem. Mais quand j'utilise XHWIFDemo, XHWIF ou Boardscope avec le même bitstream je reçois l'erreur suivante : "Error Configuring the Bitstream. Exiting" or with XHWIF : "Downloading bitstream to device 0 (one packet at a time). <DUMMY> Could not download bitstream packet 0 to device 0. Exiting. (-4097)" L'erreur 4097 de l'api rc1000pp correspond à l'INTERNAL_ERROR :error while talking to driver. Je n'ai pas le code source de la librairie dynamique rc1000pp.dll, donc je ne peux pas en savoir plus sur l'erreur et ce qui la provoque. La connection avec la carte et le reset marche correctement (en tout cas je ne reçois pas d'erreur). Some more information: os : Windows NT pentium II 500 128 Mo RAM Donc si quelqu'un pouvait m'aider je lui serais éternellement reconnaissant, je commence à désespérer ! Merci Barthélémy von HallerArticle: 63754
Hi, I've tried to understand exactly which clocks a DCM will phase align when I do external or internal feedback by the book. I've read every bit of documentation I could find, but came out empty-handed. So maybe someone out there can help me out... This is the structure I have for internal feedback: module int_fb(clki, clko); input clki; output clko; wire clki_buf, clk_fb, clk_2x; assign clko = clk_fb; IBUFG ibufg0(.I(clki), .o(clki_buf)); DCM dcm0(.CLKIN(clki_buf), .CLKFB(clk_fb), .CLK2X(clk_2x)); BUFG bufg0(.I(clk_2x), .O(clk_fb)); endmodule Which wires are phase-aligned clocks here? External feedback: module ext_fb(clki, clkfb, clko); input clki, clkfb; output clko; wire clki_buf, clk2x, clkfb_buf; IBUFG ibufg0(.I(clki), .O(clki_buf)); IBUFG ibufg1(.I(clkfb), .O(clkfb_buf)); DCM dcm0(.CLKIN(clki_buf), .CLKFB(clkfb_buf), .CLK2X(clk2x)); OBUF obuf0(.I(clk2x), .O(clko)); endmodule clko is connected to clkfb outside the FPGA. I've omitted reset and locks for simplicity. Again, which wires are phase-aligned clocks here? Also related: what does the DESKEW_ADJUST attribute do? The documentation I found says only how you set it, but not what it does... Thanks, GernotArticle: 63755
Hi, Can anyone recommend any 1.2V voltage regulators (for use with a Spartan III). Input voltage is likely to be 3.3V. What is the maximum current a Spartan III 400 is likely to require? Cheers, JonArticle: 63756
Yes, it is as you predicted, the cycle to cycle jitter of my signal is much lower, and within the DLL specs. Thanks a lot, Tullio On Mon, 1 Dec 2003, Austin Lesea wrote: > Tullio, > > The spec is for cycle to cycle jitter, not for peak to peak. > > If your signal has 1 ns of cycle to cycle jitter, it would all but > unusable for just about anything. Hopefully, that is not the case, and > the signal has 1 ns of peak to peak jitter. > > If you were to measure the cycle to cycle jitter of this signal, it will > have to be less than the 300 ps +/- DCM input specification (which is > most likely). There is also the "jitter filter" attribute which should > be set to 0xFFFFh for real jittery input signals, as this will allow the > DCM to track the incming signal the fastest (to prevent one cycle jitter > to the next cycle of jitter from affecting the phase detector). > > The status signals will properly indicate the operation: if locked does > not go high at all, or if it goes high, and then goes low a few thousand > clock cycles later, it is an indication of too much jitter. > > I have tested the DCM with sine wave jitter (at one frequency) from 100 > KHz to 20 MHz with much more than 1 ns of p-p jitter, and have seen no > issues at all, because the cycle to cycle jitter is much less than the > input specification. The DCM is completely insensitive to input jitter > frequency (within the range that was tested). > > For example, if in 1 microsecond (1 megahertz), a 100 MHz clock signal > had 1ns of jitter, peak to peak, then there are 100 clock cycles per > jitter modulation period (1 us), and the cycle to cycle clock jitter is > 1/100 of the peak to peak (or 10 ps). > > Austin > > Tullio Grassi wrote: > > > The VirtexII data sheet requires an input jitter for > > the DCM smaller than + or - 300 ps (in Low Frequency Mode). > > Obviously this ensures the proper behavior across all > > permitted frequencies and modes. > > > > In my case I have an input clock with 1ns of pk-pk jitter, but > > it is a 40 MHz clock, that I only need to shift by 90 (clk90), > > and to multiply by 2 (clk2x) other than having a locked version > > (clk0) of the original clock. > > How can I verify if it still works reliabily ? > > Or is the going to DCM loose lock ? > > Or will the phase relationships btw the output clocks not met ? > > -- Tullio Grassi ====================================== Univ. of Maryland-Dept. of Physics | College Park, MD 20742 - US | Tel +1 301 405 5970 | Fax +1 301 699 9195 | ======================================Article: 63757
Hello! I'm trying to configure two Spartan IIE (XC2S300E) in a daisy chain using two PROMs (XC18V02) but I cannot seem to make any configuration data reach the second (slave) FPGA. As a result, the DONE pin will be held low by the second FPGA and the system will never start. That was the short version, here is the long one: The four components, two XC18V02 and two XC2S300E, are connected exactly according to figure 5 in the XC18V00 data sheet, that is: * /CF of both PROMs are connected to /PROGRAM of both FPGAs * DONE of both FPGAs are connected to /CE of first PROM * /CEO of first PROM is connected to /CE of second PROM * INIT of both FPGAs are connected to /RESET of both PROMs * D0 of both PROMs are connected to DIN of master FPGA * DOUT of master FPGA is connected to DIN of slave FPGA * CCLK of master FPGA is connected to CLK of both PROMs and to CCLK of slave FPGA. So at power up, I expect the following: 1. Both FPGAs pull DONE low, enabling first PROM. 2. Both FPGAs release /INIT when initialization is done, the wire is pulled up and /RESET on both PROMs go high. 3. First PROM sends data from D0 to DIN of master FPGA, clocked by CCLK of master FPGA. 4. When done, /CEO of first PROM goes low, enabling second PROM. At the same time, master FPGA releases the DONE pin; however, slave FPGA keeps it down since it is not yet configured. 5. Second PROM sends data from D0 to DIN of master FPGA, which should forward the data from its DOUT into DIN of slave FPGA. 6. When done, slave FPGA should release DONE, the wire should be pulled up and both FPGAs should go into normal function. Things go wrong at step 5. The problem is that master FPGA never forwards any data. In fact, DOUT is high constantly as soon as power is on. Having read some earlier posts, I think that DOUT should not only copy all bits dedicated for slave FPGA at step 5, but it should also present the first 32 or 40 synchronization bits when master FPGA itself is being configured at step 3. This doesn't happen either. Anyone has any ideas about what is wrong? Does the above description make sense, or have I misunderstood anything? Here are some more clues: * We use Xilinx iMPACT for configuration. DONE and /INIT are both pulled up by 3.3kOhm resistors, but we have also tried 4.7kOhm. * We have two boards to experiment with and the same thing happens with both boards, so it's unlikely that there's something wrong with the FPGAs. * When disconnecting the DONE pin of slave FPGA, the DONE wire goes high after configuration of master FPGA, which works fine afterwards. * The MODE pins are actively held 000 on master and 111 on slave. Thanks in advance! /JerkerArticle: 63758
Hello, I still try to configure a Dual Port RAM (Xilinx Spartan-IIE) I use the CoreGenerator of ISE. I wonder, why there is a Data Out Port and a Data In Port. If I understand things right, data at the IN-port will by visible at the OUT-port (in case of configuring a port for READ/WRITE-operation). Is it true that I have to install two ports ???? I mean - this a big amount of pins which I have to use, isn't it 16 for DIN and 16 for DOUT? But if I want to jumper DIN and DOUT I will get a problem, won't I ?? Is there a solution? Is there someone with experiences with DPRAM's. If there is an example design - this would be very nice to get it. Tobias MöglichArticle: 63759
What do you folks use as a command line shell in Windows? I know several people are working outside of Project Navigator (Xilinx) for builds and it Windows is just not a very comforting environment for shell folks. What 'make' utility do you use? JakeArticle: 63760
I don't use the Navigator. I just make little batch files and execute them from the command line. I'm told that the Cygwin environment is very nice; it allows Unix-like shells on Windows, but I haven't tried it. -Kevin "Jake Janovetz" <jakespambox@yahoo.com> wrote in message news:d6ad3144.0312030941.60ffcc97@posting.google.com... > What do you folks use as a command line shell in Windows? I know > several people are working outside of Project Navigator (Xilinx) for > builds and it Windows is just not a very comforting environment for > shell folks. What 'make' utility do you use? > > JakeArticle: 63761
Gernot Koch wrote:
> Hi,
>
> I've tried to understand exactly which clocks a DCM will phase align when I do
> external or internal feedback by the book. I've read every bit of documentation
> I could find, but came out empty-handed. So maybe someone out there can help me
> out...
>
> This is the structure I have for internal feedback:
>
> module int_fb(clki, clko);
> input clki;
> output clko;
> wire clki_buf, clk_fb, clk_2x;
> assign clko = clk_fb;
> IBUFG ibufg0(.I(clki), .o(clki_buf));
> DCM dcm0(.CLKIN(clki_buf), .CLKFB(clk_fb), .CLK2X(clk_2x));
> BUFG bufg0(.I(clk_2x), .O(clk_fb));
> endmodule
>
> Which wires are phase-aligned clocks here?
The output of the BUFG (clk_fb) will be phase aligned with your input
clock (clki). By connecting to the CLKFB input, the DCM removes the
phase offset introduced by routing, the BUFG, and the DCM itself.
This results in the rising edge internal to the FPGA occurring at nearly
the same time as the rising edge of the clock feeding the FPGA... hence
you maintain a completely synchronous system.
> External feedback:
>
> module ext_fb(clki, clkfb, clko);
> input clki, clkfb;
> output clko;
> wire clki_buf, clk2x, clkfb_buf;
> IBUFG ibufg0(.I(clki), .O(clki_buf));
> IBUFG ibufg1(.I(clkfb), .O(clkfb_buf));
> DCM dcm0(.CLKIN(clki_buf), .CLKFB(clkfb_buf), .CLK2X(clk2x));
> OBUF obuf0(.I(clk2x), .O(clko));
> endmodule
>
> clko is connected to clkfb outside the FPGA.
> I've omitted reset and locks for simplicity.
>
> Again, which wires are phase-aligned clocks here?
clko, at the point on the trace that it enters the FPGA, will be phased
aligned with your input clock (clki). If the trace continues on for
another six inches past the FPGA pin, the end of the trace will of
course have an additional small phase offset due to flight time.
HOWEVER, Xilinx is considering changing the rules so that you can't do
what you've coded up in your two examples, at least in a V2-Pro. The
restriction they are considering is that CLKFB can't come from a CLK2X
output anymore. For off-chip deskew, this really throws a monkey wrench
into things. I don't know if it is too late (or useful) to complain to
your FAE about this or not.
> Also related: what does the DESKEW_ADJUST attribute do? The documentation I
> found says only how you set it, but not what it does...
The first two hits when typing in DESKEW_ADJUST in the Xilinx search
page seem to explain it pretty well:
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0086_39.html
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14743
Marc
Article: 63762Tero Rissa <no.spam@thanks.invalid> skrev den Wed, 3 Dec 2003 11:25:27 +0000 (UTC): > Marcus Svensson <NoTheSpamMosnterWillNotHaveMyMail@no.com> wrote: >> When i try to add signals to the Wave window Modelsim freeks out >> creating >> a corrut call stack error. WHY? and any ideas on how to fix that? BTW >> i'm >> running Windows XP.. > > Start the ModelSim in the command line (vsim) and when it crashes > it'll give something like this: > > ** Fatal: vsim is exiting with code X. > > If the X is 7, then deleting "vsim.wlf" file might help. > (The log file is locked by a previously crashed vsim). > > If the X is 11, then solution might be trickier. Booting > sometimes helps, but once the reason was that vsim was not > compliant with my NVidia display card! Quality SW. > > Check also all error messages carefully (in elaboration and > when crashing). Vsim can crash if some of the files are > missing. > Tnx for the reply! the error number is 211?? -- Använder M2, Operas banbrytande e-postklient: http://www.opera.com/m2/Article: 63763
Hello, I get the following error when I run Par during the assemble stage of the Partial Reconfiguration Flow. The command I used was par -w blinky_map.ncd blinky.ncd blinky.pcf The error is Starting Guide File Processing. Loading device database for application Par from file "../../Pims/configcontroller/configcontroller.ncd". "blinky" is an NCD, version 2.38, device xc2v4000, package ff1152, speed -5 The STEPPING level for this design is 0. FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.1.14.1:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1_57 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com When I bring up the active module implementation in the FPGA editor, this GND signal is inside the bounderies of the module. It has been inserted by the Xilinx tools and is not something I explicitely used in my design. I will really appreciate if someone can give me a pointer on how to resolve this. I have seached the Xilinx Answer database but did not find any useful tips.Article: 63764
Jake Janovetz wrote:
> What do you folks use as a command line shell in Windows? I know
> several people are working outside of Project Navigator (Xilinx) for
> builds and it Windows is just not a very comforting environment for
> shell folks. What 'make' utility do you use?
Consider adding linux with dual boot for windows.
Then you can use any shell you like
and the real make.
-- Mike Treseler
Article: 63765Tobias, maybe this helps: The two ports are completely independent, they only share the stored data. So you can use either of both ports as write or read. (Yes, even both simultaneously as write ports!) That explains the clocking, addressing, and the Enables. If (like in a FIFO) one port is permanently Write and the other is permanently read, you just ignore (leave unconnected) the Din on the Read port, as well as the Dout on the Write port. Those data lines are of no interest in this FIFO situation. Dout on a Write port reflects the data that you are writing ( in Virtex and Spartan-II), but in Virtex-II and Spartan3 you have some interesting options: Dout can be configured to reflect the data just being written ( as in Virtex/Spartan2), or it can reflect the old data that you just wrote over, or it can remain unchanged by the write operation, just keep showing what it showed before, whatever that was. Most users ignore the Dout of the Write port; and the Din on a read port is inherently ignored by the BlockRAM. But remember, you can make any port a read or a write port, and change that assignment on any clock cycle. You are in control ! And a last reminder: Every operation requires a clock edge, even a read. This is a synchronous RAM, different from the traditional SRAM, where the read usually is a combinatorial operation. This clock requirement for read is sometimes nice and desirable, sometimes a PITA. But it is non-negotiable. Peter Alfke, Xilinx Applications ================================= Tobias Möglich wrote: > > Hello, > > I still try to configure a Dual Port RAM (Xilinx Spartan-IIE) > I use the CoreGenerator of ISE. > > I wonder, why there is a Data Out Port and a Data In Port. > If I understand things right, data at the IN-port will by visible at > the OUT-port > (in case of configuring a port for READ/WRITE-operation). > > Is it true that I have to install two ports ???? I mean - this a big > amount of pins which I have to use, isn't it > 16 for DIN and 16 for DOUT? > > But if I want to jumper DIN and DOUT I will get a problem, won't I ?? > Is there a solution? > > Is there someone with experiences with DPRAM's. > If there is an example design - this would be very nice to get it. > > Tobias MöglichArticle: 63766
ALuPin wrote:
> Simulation might be a good first step in order to prove
> first correct functionality
Best first, second and third step.
> but what if there are
> some components which cannot be reproduced my models so
> easily?
Inside the FPGA, don't use vendor core generators.
Write your own code that infers what you need.
For memory and other external parts, choose devices
with free models or write some code.
You may not need a very fancy external model to verify
your own synth code.
Once you're done, you can "probe" wherever
you like with sim waveforms, and have the
freedom to make changes fearlessly.
-- Mike Treseler
Article: 63767Great! Good luck. Austin Tullio Grassi wrote: > Yes, it is as you predicted, the cycle to cycle jitter > of my signal is much lower, and within the DLL specs. > > Thanks a lot, > > Tullio > > On Mon, 1 Dec 2003, Austin Lesea wrote: > > >>Tullio, >> >>The spec is for cycle to cycle jitter, not for peak to peak. >> >>If your signal has 1 ns of cycle to cycle jitter, it would all but >>unusable for just about anything. Hopefully, that is not the case, and >>the signal has 1 ns of peak to peak jitter. >> >>If you were to measure the cycle to cycle jitter of this signal, it will >>have to be less than the 300 ps +/- DCM input specification (which is >>most likely). There is also the "jitter filter" attribute which should >>be set to 0xFFFFh for real jittery input signals, as this will allow the >>DCM to track the incming signal the fastest (to prevent one cycle jitter >>to the next cycle of jitter from affecting the phase detector). >> >>The status signals will properly indicate the operation: if locked does >>not go high at all, or if it goes high, and then goes low a few thousand >>clock cycles later, it is an indication of too much jitter. >> >>I have tested the DCM with sine wave jitter (at one frequency) from 100 >>KHz to 20 MHz with much more than 1 ns of p-p jitter, and have seen no >>issues at all, because the cycle to cycle jitter is much less than the >>input specification. The DCM is completely insensitive to input jitter >>frequency (within the range that was tested). >> >>For example, if in 1 microsecond (1 megahertz), a 100 MHz clock signal >>had 1ns of jitter, peak to peak, then there are 100 clock cycles per >>jitter modulation period (1 us), and the cycle to cycle clock jitter is >>1/100 of the peak to peak (or 10 ps). >> >>Austin >> >>Tullio Grassi wrote: >> >> >>>The VirtexII data sheet requires an input jitter for >>>the DCM smaller than + or - 300 ps (in Low Frequency Mode). >>>Obviously this ensures the proper behavior across all >>>permitted frequencies and modes. >>> >>>In my case I have an input clock with 1ns of pk-pk jitter, but >>>it is a 40 MHz clock, that I only need to shift by 90 (clk90), >>>and to multiply by 2 (clk2x) other than having a locked version >>>(clk0) of the original clock. >>>How can I verify if it still works reliabily ? >>>Or is the going to DCM loose lock ? >>>Or will the phase relationships btw the output clocks not met ? >> >> >Article: 63768
In article <3FCE28FD.7000408@flukenetworks.com>, Mike Treseler <mike.treseler@flukenetworks.com> wrote: >Jake Janovetz wrote: >> What do you folks use as a command line shell in Windows? I know >> several people are working outside of Project Navigator (Xilinx) for >> builds and it Windows is just not a very comforting environment for >> shell folks. What 'make' utility do you use? > >Consider adding linux with dual boot for windows. >Then you can use any shell you like >and the real make. Also, cygwin is not that bad. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 63769
> What do you folks use as a command line shell in Windows? I know > several people are working outside of Project Navigator (Xilinx) for > builds and it Windows is just not a very comforting environment for > shell folks. What 'make' utility do you use? CygWin is OK, but it's large and slow. For a faster and smaller unix-like shell you can consider Msys (from www.mingw.org) or actually Services for Unix from MS (http://www.microsoft.com/windows/sfu/default.asp). I myself use GNU make under plain vanilla CMD.EXE. It works fine for me, though it's a bit annoying that Xilinx changes the command-line options in every single release of their toolchain. Regards, Andras TantosArticle: 63770
Related Thread: http://groups.google.com/groups?q=trust+synchronizer+violate+downstream -- Mike TreselerArticle: 63771
algous2002@yahoo.com.cn (algous) wrote in message news:<1e71fcd5.0311291829.7637f13d@posting.google.com>... > I write a module as below. Let's look the last ALWAYS block. > In the case statement, It worked not as expected when I replaced the > binary form's condition(2'b00,2'b01,2'b11, etc) with > Parameter(IDLE_PHASE,NONSEQ_PHASE, SEQ_PHASE) each other, the FSM's > state(ahb_state) always loop in the last state(default 2'b11). while > writing as below, It seemed worked well. Simulating in the modsim SE > PLUS 5.6, the waves showed the value of ahb_state always be 2'b00. > whys? [snip code] You might get a better response if you ask in comp.lang.verilog. --aArticle: 63772
> CygWin is OK, but it's large and slow. For a faster and smaller unix-like > shell you can consider Msys (from www.mingw.org) or actually Services for > Unix from MS (http://www.microsoft.com/windows/sfu/default.asp). I myself > use GNU make under plain vanilla CMD.EXE. It works fine for me, though it's > a bit annoying that Xilinx changes the command-line options in every single > release of their toolchain. What does 'make' do for you that batch files to run the tools doesn't? Not being aggressive - just curious in case I am missing out on some labour saving functionality! Cheers, Ken --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.545 / Virus Database: 339 - Release Date: 27/11/2003Article: 63773
> > > Howdy folks. > > > > > > I've got a recent BS in computer sytems engineering, which is a like > > > EE with some compsci mixed in. I've used CPLDs, and really want to > > > get a good start in FPGAs so I can build my career in the 'embedded' > > > direction. > > > > > > How does one start out in fpga development given that funds are > > > limited ? > > > > > > thanks > > > > > > - moi > > > Hi, > > http://www.altera.com/products/devkits/kit-dev_platforms.jsp lists > Altera's development kits and many 3rd party kits using Altera parts. > Prices go from $99 to $7500. The Stratix 1S10 based board at $395 and > the Cyclone 1C20 board at $495 look like pretty good choices to me for > someone on a budget. They're supported by the free Quartus web > edition software. > > You can go all the way down to the $99 MAX based board though if you > really want to keep costs down. > > If you're still a university student, you can get a UP2 board which > has a 10K70 device along with Quartus and MaxPlus2 included, for $149 > US. See http://www.altera.com/education/univ/kits/unv-kits.html for > details. I would strongly recommend you learn Quartus rather than > MaxPlus2 though -- while both support the 10K, Quartus is more > powerful and you will learn more using it. > > Vaughn You can find a reasonable priced Cyclone board (EP1C6) with some additional memory for about $200 at: http://www.jopdesign.com/cyclone/index.jsp MartinArticle: 63774
Ken wrote:
>
> What does 'make' do for you that batch files to run the tools doesn't?
Nothing, if you don't use a program that generates makefiles.
Modelsim and emacs-vhdl-mode can generate makefiles
to recompile just
the right files in just the right order after
you edit a few.
But it requires having "make" in the path.
-- Mike Treseler
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