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Messages from 64550

Article: 64550
Subject: Xilinx Question
From: stanandsue2000REMOVE@yahooREMOVE.com (stan)
Date: Wed, 07 Jan 2004 15:14:16 GMT
Links: << >>  << T >>  << A >>
hi , 

basic question on the free xilinx tools you can download from the web
( may be designing for spartan )

i thought , perhaps mistakenly , that the free tools included at least
a limited simulation capability for using VHDL test benchs ,  i
thought it had a limited form of Modelsim or something ??

but the free tools seem to indicate that it is a $945 option ?

so what good are free tools if i can't even write a small VHDL test
bench to verify my design ?

stan


Article: 64551
Subject: Re: Xilinx Question
From: "Andreas Sch." <no_reply@yahoo.com>
Date: Wed, 07 Jan 2004 16:36:26 +0100
Links: << >>  << T >>  << A >>
Hi,

stan wrote:
> ...
> basic question on the free xilinx tools you can download from the web
> ( may be designing for spartan )
> 
> i thought , perhaps mistakenly , that the free tools included at least
> a limited simulation capability for using VHDL test benchs ,  i
> thought it had a limited form of Modelsim or something ??
> ...

AFAIK there is a free Modelsim version you can
download which has reduced simulation speed.
Search the Mentor website.

RU,
Andreas
No HTML mails, please.

Article: 64552
Subject: Re: Clock domains
From: Patrik Eriksson <patrik.eriksson@netinsight.net>
Date: Wed, 07 Jan 2004 16:36:30 +0100
Links: << >>  << T >>  << A >>
Beregnyei Balazs wrote:
> Hi,
> 
> I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20 MHz.
> My problem: data transport between domains create deadlock.
> (When I use the same clock in all domains, this send/receive primitive
> works fine, but I need different clocks...)
> Can somebody help me? URL, FAQ, RTFM? :)
> 
> Thanks,
> BB
> 
> // send @ 33 MHz
>  data_reg = 4;
>  data_ready <= data_ready ^ 1;
> 
> // receive @ 20 MHz
>  case (state)
>  0: if (data_ready != last_data_ready)
>       begin
>       last_data_ready = last_data_ready ^ 1;
>       state <= 1;
>       end
>  1: // READ data_reg

I don't exactly know what you want to do but maybe this could be helpful.
Read this: At www.xilinx.com -> TechXclusive -> "Moving Data Across 
Asynchronous Clock Boundaries" by Peter Alfke

Patrik Eriksson


Article: 64553
Subject: Re: Clock domains
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Wed, 7 Jan 2004 16:01:54 -0000
Links: << >>  << T >>  << A >>
"Beregnyei Balazs" <bereg@impulzus.sch.bme.hu> wrote in
message news:Pine.LNX.4.58.0401071544160.10548@impulzus.sch.bme.hu...
> I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20
MHz.
> My problem: data transport between domains create deadlock.
> (When I use the same clock in all domains, this send/receive primitive
> works fine, but I need different clocks...)
> Can somebody help me? URL, FAQ, RTFM? :)

Your circuit is (approximately) Weinstein's Flancter.
Read the details in this URL:
   http://www.xilinx.com/xcell/xl37/xcell37_54.pdf

> // send @ 33 MHz
>  data_reg = 4;
>  data_ready <= data_ready ^ 1;
>
> // receive @ 20 MHz
>  case (state)
>  0: if (data_ready != last_data_ready)
>       begin
>       last_data_ready = last_data_ready ^ 1;
>       state <= 1;
>       end
>  1: // READ data_reg

A couple of questions:

1) did you remember to initialise data_ready and
   last_data_ready?

2) did you stop the 33MHz side from sending, by having
   it look at the value of last_data_ready?  If you send
   two values, then data_ready will toggle twice and the
   20MHz side will not see it.

HTH
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 64554
Subject: Re: XST cant compile with blaxkboxes.
From: Steven Elzinga <steven.elzinga@xilinx.com>
Date: Wed, 07 Jan 2004 10:07:40 -0700
Links: << >>  << T >>  << A >>
Kelvin,

Based off of your description it sounds like compiled modules are 
remaining in the work directory after you remove the modules.  This 
should not be normal XST behavior.

As for the black box problem, whenever you instantiate a black box in 
Verilog you have to have a "module declaration."  This is required so 
that the synthesis tool will know which ports are input/output/inout 
ports.  A module declaration is an empty module that contains only the 
port listing and port declarations:

   module top (a,b,c);
    input a,b;
    output c;

    black_box u1 (.a(in1), .b(in2), .c(out1));

   endmodule


   module black_box (in1,in2,out1);
    input in1,in2;
    output out1;

   endmodule


Steve


Kelvin @ SG wrote:
> MyProj\xst\work\vlg## latency?
> 
> I found that, if I perform re-synthesis after deleted some modules from
> my source codes, the MyProj\xst\work\vlg## doesn't reflect this change.
> As a result, at re-synthesis, even if I have a question mark on some
> modules,
> meaning the module source files are absent, the XST is still able to
> synthesize
> the design, does it mean it searches the MyProj\xst\work\vlg## to look for
> the
> missing modules?
> 
> Hope somebody can explain this mystery...
> 
> Best Regards,
> Kelvin
> 
> 
> Kelvin @ SG <kelvin8157@hotmail.com> wrote in message
> news:3ffa04a7$1@news.starhub.net.sg...
> 
>>Hi, there:
>>
>>I am using ISE6.1 in office and ISE6.1Webpack at home. Both have service
>>park 3 I think.
>>
>>How come on Webpack, I can synthesize with XST and instantiate black boxes
>>at top level,
>>however in original ISE6.1 it gave me error, complaining the that it can't
>>find the bm_4b_v2...
>>The bm_4b_v2 is in the same running directory.
>>
>>ERROR:HDLCompilers:87 - ../hdl/top_bt.v line 487 Could not find
>>module/primitive 'bm_4b_v2'
>>
>>Is there any settings for XST to read in NMC macros as blackboxes?
>>
>>Could anybody teach me how to handle this situation?
>>
>>Best Regards,
>>Kelvin
>>
>>
>>
> 
> 
> 


Article: 64555
Subject: Re: Virtex and Spartan
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 07 Jan 2004 09:20:39 -0800
Links: << >>  << T >>  << A >>
Bhadri,
somebody gave you bad information.
Virtex and Spartan are very similar, sometimes even almost identical.
Virtex emphasizes size and performance, Spartan is the more frugal
(hence the name) brother.
SpartanXL is almost identical with XC4000XL,
Spartan-II is almost identical with Virtex
Spartan-IIE is almost identical with Virtex-E
Spartan3 has many of the features of Virtex-II, but has reduced the chip
size and therefore eliminated some features, and it has a newer version
of the DCM.

Then there is technological evolution, which determines chip size and
price, as well as performance and supply voltage.
There is no substitute to studying the data sheets.

But, to paraphrase Annie Oakley: 
"Anything Spartan can do, Virtex can do also". 
Often faster, sometimes in a different package, usually at a higher price...
Peter Alfke 
=======================
Bhadri wrote:
> 
> Hello
> can anyone say me what is the difference between virtex and spartan
> fgpa chips.
> It is just the number of gates in them, voltage levels or anything
> more than that.
> I have used spartan chips.i configured the chip with different vhdl
> files again and again on the same chip.But somebody said it is not
> possible in the xcv1000 virtex chips.(dynamically reconfigurable).Is
> it true.Then,y are they called FPGA's.
> 
> Thanks in advance
> bhadri

Article: 64556
Subject: plb_sdram, timing error
From: Christian Haase <nospams@today.de>
Date: Wed, 07 Jan 2004 18:22:46 +0100
Links: << >>  << T >>  << A >>
Hello (world),

I've a dodgy problem with a plb_sdram_v1_00_c connected to
the PLB with a PowerPC as single master and a second slave
(a plb2opb_bridge).

The SDRAM is a HYB/E 25L128160AC 128-MBit-Mobile-RAM at a
Memec-X2VP7-Eval-Board. I use the settings as stated in
the appendix (the really interesting part of this posting).
They are taken from a tutorial design that comprise a
OPB-sdram (and already worked with a coregen generated
sdram controller connected to a selfmade opb-like bus).

Writing to the SDRAM works fine. Reading from SDRAM yields
an error ratio of about 800/4194304:
In the error cases the 9th Bit of data is '1' instead of '0'.
A second subsequent read from an "error address" gives the
correct data value.

Obviously (?) it's some kind of timing problem.
The timing report says that the overall period constraint
is met. The only thing that perplexes is:

WARNING:Timing:2666 - Constraint ignored: PATH "FROM U_CLK TO D_CLK"  TIG ;

(Xilinx-Answer says it can be safely ignored)


Thanks to those how read this posting (and even the appendix)
and thanks to any kind of advice

Christian



(The APPENDIX:)
  PARAMETER C_SDRAM_REFRESH_NUMROWS = 4096
  PARAMETER C_SDRAM_TMRD = 2
  PARAMETER C_SDRAM_TCCD = 1
  PARAMETER C_SDRAM_TRAS = 48000
  PARAMETER C_SDRAM_TRC = 70000
  PARAMETER C_SDRAM_TRFC = 75000
  PARAMETER C_SDRAM_TRCD = 19000
  PARAMETER C_SDRAM_TRRD = 16000
  PARAMETER C_SDRAM_TRP = 25000
  PARAMETER C_SDRAM_TREF = 64
  PARAMETER C_SDRAM_CAS_LAT = 2
  PARAMETER C_SDRAM_COL_AWIDTH = 9
  PARAMETER C_SDRAM_BANK_AWIDTH = 2
  PARAMETER C_SDRAM_AWIDTH = 12
  PARAMETER C_SDRAM_DWIDTH = 32


Article: 64557
Subject: DPRAM using the CoreGenerator, VHDL-example
From: Tobias =?iso-8859-1?Q?M=F6glich?= <Tobias.Moeglich@gmx.net>
Date: Wed, 07 Jan 2004 19:11:14 +0100
Links: << >>  << T >>  << A >>
Hello,
I'm using Xilinx ISE 6.1.
I'm using the CoreGenerator for designing a dual port RAM (block RAM).
Is there an example in VHDL how to access the RAM and read the RAM?
How can I say ISE to use the generated core and not for example
distributed single port RAM or what ever he want's?

And since I use the CoreGenerator I can say how wide port A and how wide
port B should be. (I.e : port A: 8 bit; port B: 16 bit).
ISE doesn't know at all (I suppose) that I want to use my generated core
where I already defined the width of port A and port B.
He criticizes it .

Can someone help me?

Tobias Möglich


Article: 64558
Subject: Re: Xilinx Question
From: Chris Carlen <crcarle@BOGUS.sandia.gov>
Date: Wed, 07 Jan 2004 10:14:19 -0800
Links: << >>  << T >>  << A >>
stan wrote:
> hi , 
> 
> basic question on the free xilinx tools you can download from the web
> ( may be designing for spartan )
> 
> i thought , perhaps mistakenly , that the free tools included at least
> a limited simulation capability for using VHDL test benchs ,  i
> thought it had a limited form of Modelsim or something ??
> 
> but the free tools seem to indicate that it is a $945 option ?
> 
> so what good are free tools if i can't even write a small VHDL test
> bench to verify my design ?
> 
> stan
> 

I was perplexed by this same question the other day, but after probing 
around Xilinx's website for a little longer before asking what's up 
here, I discovered that the free simulator is indeed available, just not 
so obvious depending on what sequence of link clicking you use.

So, look harder, and you will find the free ModelSim download at xilinx.com.

Good luck!


-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov


Article: 64559
Subject: Synthesis in VHDL vs. Verilog
From: Chris Carlen <crcarle@BOGUS.sandia.gov>
Date: Wed, 07 Jan 2004 10:21:46 -0800
Links: << >>  << T >>  << A >>
Greetings:

I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog 
Primer" in order to learn not only Verilog, but how to make sure I can 
model designs in a way that is synthesizable.

What I have just learned is that the synthesis system (such as if I am 
using Xilinx ISE Webpack and it's associated synthesis tools) dictates 
what style must be followed, because one system might be able to 
synthesize model 'A' and not 'B', whereas another system might be able 
to synthesize 'B' and not 'A', even though models 'A' and 'B' are 
functionally equivalent.

Thus, this leads to the question of how to I learn about what modeling 
style will be synthesizable for my particular tools?

The text won't be able to teach me this, since it is just dealing with 
the problem in general.  Obviously this must be in the tooll 
documentation, so I would ask:

Is there good modeling style info in Xilinx tools so that one can learn 
how to make synthesizable models for Xilinx tools reliably?

Finally, how to VHDL and Verilog compare in terms of *inherent* 
synthesizability of models, or does the same problem essentially exist 
for both?

Thanks for input.

Good day!
-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov


Article: 64560
Subject: Tutorials for ISE and Quartus
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Wed, 07 Jan 2004 18:48:59 GMT
Links: << >>  << T >>  << A >>
I've posted 2 (very graphical) tutorial for ISE and Quartus.

ISE: http://www.fpga4fun.com/ISEQuickStart.html
Quartus: http://www.fpga4fun.com/QuartusQuickStart.html

These are very simple - covers only device selection, pin assignment, and
how to get the bit file.
Still if you never saw the particular software in action, that might be the
occasion.
Have fun!
Jean



Article: 64561
Subject: Re: Generate the first interrupt for MB XMK
From: mohan <mohan@xilinx.com>
Date: Wed, 07 Jan 2004 11:15:47 -0800
Links: << >>  << T >>  << A >>
Jari,
  Your code looks mostly fine so this could be a hardware problem. Check your MHS file to see if the interrupt pin of MicroBlaze is hooked up to the interrupt controller, and the interrupt controller
is hooked up to the timer.
Once you begin to see the interrupts, there are a few small issues 
that should be fixed before everything works.
1) MAX_PROCS should be set to at least 1 more than the number of procs you specify in the table because 
 there is a default system idle process that needs to be created.
2) you don't need to specify the interrupt handler in the MSS file. XMK always goes to the timer interupt handler 
 in timer_intr.S when an interrupt occurs. After the call to the process_scheduler in that code, you will need to add code to
 ack/clear the timer interrupt. If you want to avoid assembly language programming, the simplest thing to do is to write 
 all this new code as a C function and use a single assembly instruction brlid to call this C function. If you want 
 to handle additional interrupts, you could replace timer_intr.S with your own code to handle the other interrupts and 
 call the process scheduler as appropriate.
 All of this has been automated in the upcoming release of our software if you would rather wait for it.
3) if you want to modify source code for XMK, please remember to copy the entire directory from  $EDK/sw/ProcessorIPLib/sw_services/xilkernel* to your project directory/sw_services/xilkernel* and do
not modify the sources
 in your project directory/<proc_name>/libsrc/xilkernel*
4) The value of 100 in the timer setup code could result in too many interrupts. You might want to increase the number of cycles before an interrupt to something bigger, like 0xffff.

You could also try to run everything from BRAM and see if things work correctly.

Best wishes,
  Mohan



Jari wrote:
> 
> Hi!
> 
> My question is long, but bare with me. I am using EDK 3.2 and trying
> to get Microblaze XMK working from external memory. I have bootloader
> in BRAM, which copies the context of FLASH memory to SRAM memory and
> then jumps to SRAM. This context includes Xilkernel.elf and two
> processes: Shell.elf (This is from test/arch/microblaze/Shell.c) and
> Print.elf, which is simple "Hello World". Here is a snippet of my .MSS
> file
> 
> BEGIN LIBRARY
>  PARAMETER LIBRARY_NAME = xilkernel
>  PARAMETER LIBRARY_VER = 1.00.a
>  PARAMETER MAX_PROCS = 2
>  PARAMETER CONFIG_PROCESS = true
>  PARAMETER CONFIG_PROCESS_EXIT = true
>  PARAMETER CONFIG_PROCESS_KILL = true
>  PARAMETER CONFIG_PROCESS_SLEEP = true
>  PARAMETER CONFIG_PROCESS_YIELD = true
>  PARAMETER THREAD_STACK_SIZE = 0x400
>  PARAMETER PROCESS_TABLE = ( (0x80806000, 1), (0x8080A000, 2))
>  PARAMETER SCHED_TYPE = 2
>  PARAMETER CONFIG_MUTEX = true
>  PARAMETER CONFIG_SEMA = true
>  PARAMETER CONFIG_MSGQ = true
>  PARAMETER CONFIG_THREAD_SUPPORT = true
>  PARAMETER MSGQ_TABLE = ( (10, 10), (15, 15) )
> END
> 
> Bootloader works correctly and I have 3 .ELF files in SRAM memory. My
> problem is how to generate the first interrupt to get the first
> process scheduled. Like said in xilkernel_v1_00_a/src/src/sys/main.c
> file
> 
>  * @file main.c
>  *
>  * The main routine, that starts the kernel.
>  *
>  * Enables the Interrupts and starts the timer Interrupt.
>  * Initialises the system by calling sys_init() and loops. On first
> timer
>  * interrupt the first process gets scheduled.
> 
> From MB_XILKERNEL part the code seems to be incomplete so I have tried
> to add following lines to main.c file
> 
> #ifdef MB_XILKERNEL
>         /* Enable microblaze interrupts */
>         microblaze_enable_interrupts();
> 
>      /* Start the interrupt controller */
>         XIntc_mMasterEnable(XPAR_MY_OPB_INTC_BASEADDR);
> 
>      /* Set the number of cycles the timer counts before interrupting
> */
>         XTmrCtr_mSetLoadReg(XPAR_MY_OPB_TIMER_BASEADDR, 0, 100);
> 
>      /* Reset the timer and clear interrupts */
>         XTmrCtr_mSetControlStatusReg(XPAR_MY_OPB_TIMER_BASEADDR, 0,
> XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
> 
>      /* Enable timer interrupt in the interrupt controller */
>         XIntc_mEnableIntr(XPAR_MY_OPB_INTC_BASEADDR,
> XPAR_MY_OPB_TIMER_INTERRUPT_MASK);
> 
>      /* Start the timer */
>         XTmrCtr_mSetControlStatusReg(XPAR_MY_OPB_TIMER_BASEADDR, 0,
> XTC_CSR_ENABLE_TMR_MASK  | XTC_CSR_ENABLE_INT_MASK |
>         XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
> #endif
> 
> I was hoping to set timer to count and give interrupt so I can get the
> first interrupt. But I am stuck in here, end of main.c file, waiting
> interrupt to occur.
> 
>         while(1) {      /* Keep looping....*/
>                  print("Hi!\r\n") ;
>         }
>         return 0 ;
> 
> I have checked every value of these XPAR_... and XTC_... variables and
> they are ok. I am guessing that I am missing Interrupt routine, like
> timer_int_handler or something like that. In the same folder where
> main.c is located there is also timer_intr.S file. If I have
> understood correctly this should be Microblaze Xilkernel
> timer_intr_handler? Why it is not working? What am I missing? Am I
> trying in a wrong way to get an interrupt to occur? Should there be
> line
> 
> PARAMETER INT_HANDLER = timer_intr_handler, INT_PORT = Interrupt
> 
> in my .MSS file?
> 
> Thanks,
> Jari

Article: 64562
Subject: Re: Synthesis in VHDL vs. Verilog
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 7 Jan 2004 19:50:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
Chris Carlen <crcarle@bogus.sandia.gov> wrote:
...
: Is there good modeling style info in Xilinx tools so that one can learn 
: how to make synthesizable models for Xilinx tools reliably?

Look on the XILINX site for xst.pdf amd lib.pdf

...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 64563
Subject: newbie question: speed grade + area constraint
From: "Yttrium" <Yttrium@pandora.be>
Date: Wed, 07 Jan 2004 19:52:33 GMT
Links: << >>  << T >>  << A >>
this might be a stupid question, but what does a speedgrade actually mean? i
haven't found a clear and short answer yet! and the second question (might
again be a stupid question) what does:

Found area constraint ratio of 100 (+ 5) on block uart_controller, actual
ratio is 1.

mean? i have got this after compiling and what does the 100, +5 and 1
exactly mean?

thanx in advance,

greetz

Yttrium



Article: 64564
Subject: Re: Tutorials for ISE and Quartus
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Wed, 07 Jan 2004 20:06:43 GMT
Links: << >>  << T >>  << A >>
I had to removed the Xilinx's screenshots, following Xilinx's notice that
they had to be reviewed by their legal department..
Let's hope that proves to be easy.

"Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message
news:vwYKb.7676$fB5.2422@newssvr25.news.prodigy.com...
> I've posted 2 (very graphical) tutorial for ISE and Quartus.
>
> ISE: http://www.fpga4fun.com/ISEQuickStart.html
> Quartus: http://www.fpga4fun.com/QuartusQuickStart.html
>
> These are very simple - covers only device selection, pin assignment, and
> how to get the bit file.
> Still if you never saw the particular software in action, that might be
the
> occasion.
> Have fun!
> Jean
>
>



Article: 64565
Subject: Xilinx ECS - connecting a single net to multiple bus lines?
From: ad.rast.7@nwnotlink.NOSPAM.com (Alex Rast)
Date: Wed, 07 Jan 2004 21:36:15 -0000
Links: << >>  << T >>  << A >>
What's the way to do this? It's common for me to run into situations where 
I have a bus or bus pin, and I need to connect the same net to different 
lines on the bus. Another common one is I have 2 busses, both of which have 
a line that should connect to a single net. The documentation doesn't seem 
to give any hints. Thanks for any input.

-- 
Alex Rast
ad.rast.7@nwnotlink.NOSPAM.com
(remove d., .7, not, and .NOSPAM to reply)

Article: 64566
Subject: Re: newbie question: speed grade + area constraint
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 07 Jan 2004 13:50:06 -0800
Links: << >>  << T >>  << A >>
Speed grade is the manufacturer's way of testing and classifying the
parts according to their actual speed. Memories have done that for decades.
So the only difference between  different speed grades of the same
device type is that some are faster than others. And Marketing sets the
prices accordingly, so the faster parts are sold for a higher price. No
other differences.
All ( i.e. each individual) Xilinx FPGAs are tested 100% for speed while
operating at their highest guaranteed temperature.  And testing means
reconfiguring hundreds of times, and running millions of test vectors
through each part. 
"We really sell used FPGAs"  :-)
I would imagine that our competitors do the same. It's the smart thing
to do...
Peter Alfke

Yttrium wrote:
> 
> this might be a stupid question, but what does a speedgrade actually mean? i
> haven't found a clear and short answer yet! and the second question (might
> again be a stupid question) what does:
> 
> Found area constraint ratio of 100 (+ 5) on block uart_controller, actual
> ratio is 1.
> 
> mean? i have got this after compiling and what does the 100, +5 and 1
> exactly mean?
> 
> thanx in advance,
> 
> greetz
> 
> Yttrium

Article: 64567
Subject: Re: Synthesis in VHDL vs. Verilog
From: Jeff Cunningham <jcc@sover.net>
Date: Wed, 07 Jan 2004 22:18:53 GMT
Links: << >>  << T >>  << A >>
Both VHDL and Verilog were originally developed as simulation languages 
with synthesis coming along later. Both languages have stuff that is 
synthesizable and stuff that is not.

My experience using several VHDL synth tools is that 98% of the stuff 
that is synthesizable under one tool will also be synthesizable under 
another one. Of a much greater variability is how well each tool maps 
the models to the underlying fabric.

IMHO a good generic book about writing synthesizable code will prepare 
you for whatever tool you want to use. Also Xilinx has a guide to 
writing code for synthesis somewhere on their web site that will tell 
you pretty much the same thing. The xilinx docs should also tell you 
what special FPGA constructs like shifters and memory can be inferred 
from your generic code without having to explicitly instantiate them, 
which is good to know.

Jeff


Article: 64568
Subject: Wierd problem with Xilinx XC9572 ID code
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Wed, 07 Jan 2004 17:16:33 -0600
Links: << >>  << T >>  << A >>
Hello,

I have been using Xilinx 9500 series CPLDs for some time.  Usually the
slowest grade is sufficient for the bus interfaces, etc. that I do.
I use the Parallel Cable III to program them, and know about the problems
with that, but I know how to make it work.

I just pulled some new XC9572PC84s out of the tube and got a wierd
error message while trying to program them with Impact from the
Ise 4.1.03i package.  The error was that the BSDL file didn't match
the device ID code.

The devices I have been using are marked XC9572 / PC84AMM0229 /
A1228011A / 15C

The parts that gave the error are marked XC9572 / PC84ASJ9737 /
A1025793A / 10C

The parts that won't program (or do anything else under Impact) are even 
older,
it seems, than the ones that work OK.

Any idea why these devices have an ID code that is unrecognized by Impact?
I got some more of the 15C devices and they still program OK.

Thanks,

Jon


Article: 64569
Subject: Re: SDRAM Controller timing problem
From: "Verilog USER" <anonymous@xxx.com>
Date: Thu, 08 Jan 2004 00:11:04 GMT
Links: << >>  << T >>  << A >>
You may need to "deskew" the clock that you feed to the SDRAM to get it to
work
by using a DLL in the Xilinx FPGA


"etrac" <etraq@yahoo.fr> wrote in message
news:c99b95c7.0401070133.38f7e294@posting.google.com...
> Hello,
>
> I have implemented my own SDRAM controller in a Virtex II component in
> order to use SDRAM modules Sodimm-PC133 (133 MHz frequency).
>
> My problem is that this block seems to work very well with MICRON
> Sdram modules, but it is not fully stable with SMART modules. It seems
> to be the burst reading which causes some bit errors (not many, we
> have at worst 25 bit errors on 32Mb files).
>
> I think the FPGA block is OK, routing timings are correct, and I think
> my problem may be on SDRAM timings. I used 180° phase of my DCM to
> generate control signals and bring back datas, in fact I work on the
> falling edge of the SDRAM clock. I have tried to work on the rising
> edge but then results are much uncertain !
>
> So my question is : Do you had some timing problems when controlling a
> Sdram ? On which edge do you work ?
>
> etrac



Article: 64570
Subject: Re: Wierd problem with Xilinx XC9572 ID code
From: Leon Heller <aqzf13@dsl.pipex.com>
Date: Thu, 08 Jan 2004 00:35:39 +0000
Links: << >>  << T >>  << A >>


Jon Elson wrote:

> Hello,
> 
> I have been using Xilinx 9500 series CPLDs for some time.  Usually the
> slowest grade is sufficient for the bus interfaces, etc. that I do.
> I use the Parallel Cable III to program them, and know about the problems
> with that, but I know how to make it work.
> 
> I just pulled some new XC9572PC84s out of the tube and got a wierd
> error message while trying to program them with Impact from the
> Ise 4.1.03i package.  The error was that the BSDL file didn't match
> the device ID code.
> 
> The devices I have been using are marked XC9572 / PC84AMM0229 /
> A1228011A / 15C
> 
> The parts that gave the error are marked XC9572 / PC84ASJ9737 /
> A1025793A / 10C
> 
> The parts that won't program (or do anything else under Impact) are even 
> older,
> it seems, than the ones that work OK.
> 
> Any idea why these devices have an ID code that is unrecognized by Impact?
> I got some more of the 15C devices and they still program OK.

I had a similar problem with XC9536 devices. Xilinx told me not to use 
Impact but to use the older JTAG programming software: Release 3.3WP8.x

That worked OK.

Leon
-- 
Leon Heller, G1HSM
Email: aqzf13@dsl.pipex.com
My low-cost Philips LPC210x ARM development system:
http://www.geocities.com/leon_heller/lpc2104.html


Article: 64571
Subject: iMPACT error : Done did not go high.
From: m_perez_gutierre@hotmail.com (Mois?s)
Date: 7 Jan 2004 17:11:48 -0800
Links: << >>  << T >>  << A >>
Hi everybody, I have been trying to configurate the Microblaze
processor in several boards, I use iMPACT and a JTAG cable to download
the bistream to the boards, but the process fails. The following is
the result message :

---------------------------------------------------------------------
// *** BATCH CMD : Program -p 2 
PROGRESS_START - Starting Operation.
Validating chain...
Boundary-scan chain validated successfully.
Validating chain...
Boundary-scan chain validated successfully.
'2':Programming  device...
done.
INFO:iMPACT:579 - '2': Completed downloading bit file to device.
INFO:iMPACT:580 - '2':Checking done pin ....done.
'2': Programming terminated, Done did not go high.
PROGRESS_END - End Operation.
Elapsed time =      5 sec.
---------------------------------------------------------------------


Somebody has experimented this error?

 or

Somebody know what are the common causes of this?


Thanks in advance

Article: 64572
Subject: Re: Questions about guard bits in CORDIC algorithm
From: freelait2000@yahoo.com (Jeff)
Date: 7 Jan 2004 17:19:24 -0800
Links: << >>  << T >>  << A >>
Thank you very much, Ray.
As what you say, I eventurely find that the auther realized multiply
and divide using CORDIC, then add the results from the paper.

Article: 64573
Subject: Re: Virtex and Spartan
From: Ray Andraka <ray@andraka.com>
Date: Wed, 07 Jan 2004 23:00:03 -0500
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> Bhadri,
> somebody gave you bad information.
> Virtex and Spartan are very similar, sometimes even almost identical.
> Virtex emphasizes size and performance, Spartan is the more frugal
> (hence the name) brother.
> SpartanXL is almost identical with XC4000XL,

little difference other than speed and package choices

>
> Spartan-II is almost identical with Virtex

Virtually no difference.  Some spartanII and VIrtex bit streams are
interchangeable.  The biggest difference I recall was the elimination of the
temp sense diode in spartanII

>
> Spartan-IIE is almost identical with Virtex-E

Differences are greater.  The most remarkable one is that the SpartanIIe has
considerably less memory than the equivalent sized virtexE.  The DLLs are also
different IIRC, still macros for one could be used in the other without change

>
> Spartan3 has many of the features of Virtex-II, but has reduced the chip
> size and therefore eliminated some features, and it has a newer version
> of the DCM.

Further divergence.  Half of the SRL16s / LUT RAM is gone, making it tricky to
reuse placed macros for VirtexII in spartan 3.

>

History shows that the spartan line is diverging from the virtex line.  Let's
hope the divergence does not continue to the point where design libraries are no
longer common between them.  It is already getting to be a pain to work a design
library to support both spartan3 and VIrtexII.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 64574
Subject: spartan 3 sample
From: anjanr@yahoo.com (Anjan)
Date: 7 Jan 2004 20:17:35 -0800
Links: << >>  << T >>  << A >>
Hi
Has anybody received spartan 3? The loc distributor claims that it
hasnt been shipped. Any idea on the availability
ANjan



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