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Messages from 64700

Article: 64700
Subject: Error message in Mapping while using Xilinx ISE 6.1.03i
From: gandhisn@ececs.uc.edu (Sachin)
Date: 11 Jan 2004 18:50:37 -0800
Links: << >>  << T >>  << A >>
Hello,
          I have a new project which I created in Xilinx ISE 6.1 which
accepts an edif top-level module type on virtex-II device family,
xc2v6000 Device, ff1517 package, speed grade -4. The edif file is
generated using SynplifyPro software.
          The first step to translate the edif file works fine and
generates no error messages. But, when I go to the next step and I do
the mapping, I get the following error:

Started process "Map".

Using target part "2v6000ff1517-4".
FATAL_ERROR:DeviceResourceModel:basnpdevice.c:620:1.23 - bad nph file 
 Process
   will terminate.  To resolve this error, please consult the Answers
Database
   and other online resources at http://support.xilinx.com. If you
need further
   assistance, please open a Webcase by clicking on the "WebCase" link
at
   http://support.xilinx.com
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fp_mul . . .
MAP command line:
map -intstyle ise -p xc2v6000-ff1517-4 -cm area -pr b -k 4 -c 100 -tx
off -o fp_mul_map.ncd fp_mul.ngd fp_mul.pcf
Mapping Module fp_mul: failed

           Can anyone please give me an insight on what the problem
can be. I suspect there is a problem with ISE installation.
           
Thanks and Regards,
Sachin Gandhi

Article: 64701
Subject: Altera NIOS cyclone edition development board problem
From: dreamguy007@hotmail.com (Jack)
Date: 11 Jan 2004 19:30:43 -0800
Links: << >>  << T >>  << A >>
hi. i am going through software dev. tutorial that came with nios dev.
kt for cyclone and whenever i tried to run insight debugger with
byteblaster II, it always said "failed to connect.
here is the command line:

nios-debug lcd_demo1.srec

# [nios-gdb-server] accepting gdb connection
# [nios-gdb-server] connecting to OCI, ocibase 0x00920800
# [nios-gdb-server] ...using byteblaster (altLPT1)
# [nios-gdb-server] mdi error: found 0 devices instead of 1
# [nios-gdb-server] failed to connect

I made sure the jtag cable and serial cable are connected to the right
places.
I also set the parallel port as EPP
Anyone knows what's going on?

Article: 64702
Subject: Re: Synthesis in VHDL vs. Verilog
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Mon, 12 Jan 2004 04:25:26 GMT
Links: << >>  << T >>  << A >>
On Sun, 11 Jan 2004 15:35:14 -0800, Jim Lewis <Jim@SynthWorks.com>
wrote:

>Verilog is a less consise language.  If you don't follow
>some adhoc methodology for coding styles, you will not
>get it right.  This fact has been proven time and time
>again by Verilog experts who have given numerous
>conference papers how they overcame yet another Verilog
>issue.  And by the way, according to my sources (Cliff C.)
>this is not a feature that is being fixed in SystemVerilog.

I'm hardly an expert in Verilog, yet I have no problems writing code
that's easily and correctly synthesized.

There are perfectly good reasons for coding in VHDL, perhaps the most
compelling of which to me is the ability to more easily include
placement information, e.g., RLOCs  (I'm going by what people I
respect tell me, not personal experience).  But writing synthesizeable
Verilog is not an issue.

I think that Janick Bergeron, the verification guru, came up with the
best answer to the which-is-better question.  When asked which of the
two languages he prefers, he said it's whichever one he isn't
currently using.

Bob Perlman
Cambrian Design Works
 

Article: 64703
Subject: Re: Altera Cyclone data is incomplete or messy
From: Ralph Malph <noone@yahoo.com>
Date: Sun, 11 Jan 2004 23:33:34 -0500
Links: << >>  << T >>  << A >>
Rene Tschaggelar wrote:
> 
> Browsing the 'cyclone device handbook' I spent a great
> length to find :
> -the max current for each supply ( VCCIO & VCCINT )
> -the expected clocking frequency at the input. I'm aware
>   that 1MHz may not be sufficient to PLL it up to 400MHz
>   or such.
> 
> to little avail. While I can live with 2 switchmode supplies
> generating 1.5V and 3.3V at 2A each, and a generic 8pin
> socket to swap oscillators for a prototype, the documentation
> is somehow inclomplete.

I don't think anyone publishes a *max* current for FPGAs.  This depends
greatly on the design and the clock speed.  It even depends on the
loading on the IO lines.  But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can
come from either of the two supplies.  The may be very conservative, but
it will give you a *maximum*.

Article: 64704
Subject: Re: Synthesis in VHDL vs. Verilog
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Mon, 12 Jan 2004 16:06:54 +1100
Links: << >>  << T >>  << A >>
On Mon, 12 Jan 2004 04:25:26 GMT, Bob Perlman
<bobsrefusebin@hotmail.com> wrote:

>I'm hardly an expert in Verilog, yet I have no problems writing code
>that's easily and correctly synthesized.
>
>There are perfectly good reasons for coding in VHDL, perhaps the most
>compelling of which to me is the ability to more easily include
>placement information, e.g., RLOCs  (I'm going by what people I
>respect tell me, not personal experience).  But writing synthesizeable
>Verilog is not an issue.

Verilog 2001 supports attributes.  However, even in this latest
version of the language, it still isn't possible to have an attribute
whose value is a string that is a function of e.g. a genvar.

Details here:
http://groups.google.com/groups?threadm=mB7gb.12033%24dH7.6968%40newssvr25.news.prodigy.com

[Sarcasm] Clearly the language committee understands the needs of
users.

>I think that Janick Bergeron, the verification guru, came up with the
>best answer to the which-is-better question.  When asked which of the
>two languages he prefers, he said it's whichever one he isn't
>currently using.

I dislike both VHDL and Verilog.  Neither do what I want, although
Verilog is much further away from the level of abstraction at which I
wish to work.
VHDL with some degree of OO would be nice.  I await the results of the
VHDL 200x committees.

Regards,
Allan.

Article: 64705
Subject: Re: Synthesis in VHDL vs. Verilog
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 12 Jan 2004 07:14:37 -0000
Links: << >>  << T >>  << A >>
>So going back to simple.  Verilog is simple to start
>producing code, however, if you fail to follow the
>adhoc rules of Verilog coding, it is very easy to
>get it wrong.  Note, this happens to Verilog experts.
>If you want to get it right with Verilog, you would
>be best to invest in a Lint tool.

Do such tools exist?  Any of them free/cheap?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 64706
Subject: How to generate a CSA tree?
From: "Sleep Mode" <karagiozhs@hotmail.com>
Date: Mon, 12 Jan 2004 10:19:36 +0200
Links: << >>  << T >>  << A >>
Hi all,

I am trying to design a 16-bit integer multiplier in VHDL and I want to use
a Carry-Save-Adder (CSA) tree for generating the interim subproducts
and -then- with an additional CPA (or other) adder to add them to the final
32-bit product; i.e. I want to build a full-tree multiplier.

My question is whether there is some automatic (core) generator for the
CSA-tree interconnections since it is rather complicated to do it by hand...
If not, is there any fast method of drawing it manually (pen-and-paper) so
that I can translate it to VHDL later on?


Thanks in advance guys,
Chris



Article: 64707
Subject: V2P7 Partial reconfiguration, FATAL_ERROR in par
From: Sean Durkin <23@iis.42.de>
Date: Mon, 12 Jan 2004 09:23:26 +0100
Links: << >>  << T >>  << A >>
Hi *,

I'm trying to do a module-based partial reconfiguration flow on a 
Virtex2Pro (xc2vp7) according to xapp290 (I'm using ISE6.1i w/SP3).

Par always fails in the final assembly phase with this error message:

"FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137 - Guide 
encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1_156 that does not 
have a driver or load within the module boundary. This problem may be 
caused by having a constant driving the input from outside the module 
boundary or because a driver or load comp did not meet the par-guiding 
criteria."

When I open the .ncd fo the placed and routed module in FPGAEditor and 
look at GLOBAL_LOGIC1_156, it's directly connected to a VCC site that is 
definitely WITHIN the module boundary, as is the entire signal and all 
components it is connected to.

Has anyone else encountered this? I could find nothing about this on 
Xilinx's website, and the error message itself is not particularly 
helpful. If a "driver or load comp did not meet the par-guiding 
criteria", how can I find out WHICH component is responsible, and what 
can I do about it?

cu,
Sean

-- 
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])

Article: 64708
Subject: Re: min propagation delay in xilinx cpld
From: guillerodriguez@terra.es (guille)
Date: 12 Jan 2004 01:00:19 -0800
Links: << >>  << T >>  << A >>
"John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<u_9Lb.154$M4.82@newsr2.u-net.net>...
> Generally you won't get minimum times. I have seen many customers fall over
> this aspect of CPLDs with their designs failing in the field after years of
> product production. Usually the timing of CPLDs change due to ageing,

Uh? That's the first time I heard about timing changing due to age
(unless you mean old technology is slower than new technology :)

> silicon process changes (usually faster) etc etc.
> 
> Best to register signals using a high speed clock to set minimum delays use
> rising or falling edges as best suits your design. Alternatively you can
> positively skew signal timing by altering pcb trace lengths.This usually
> gives a fairly stable result once you have got it sorted but can be a bit of
> fiddle as speed down traces depends on loading.

Good advice, thanks. However the design is closed at this stage and
no changes are possible -- I just need to derive the timing for the
current implementation.

Thanks anyway,
Guillermo Rodriguez

Article: 64709
Subject: Re: min propagation delay in xilinx cpld
From: guillerodriguez@terra.es (guille)
Date: 12 Jan 2004 01:04:27 -0800
Links: << >>  << T >>  << A >>
Peter,

Peter Alfke <peter@xilinx.com> wrote in message news:<3FFD91F8.5C4BA92A@xilinx.com>...
> Guille,
> your source promises a min delay that is 10% of its max delay. You are
> safe in assuming a similar ratio for the CPLD. That means max 10 ns, min
> 1.0 ns.
> This seemingly ridiculously loose specification is the result of many factors:
> Processing tolerances including "down-binning" where the manufacturer
> marks a faster ( and more valuable) part as a slower speed grade,
> because therehappens to be more demand for that grade.
> Then temperature ( cold is faster) and Vcc tolerances ( high is faster).
> Plus additional guardband, since the min parameter is not actually
> tested ( the max value is ), plus a lot of tester guardband if it were tested.
> 
> But 10% is a safe value, as long as you do not retrofit five years from
> now, when you might get surprised by a much faster part...
> 
> It is always safer to design in sucha way that min delays values do not matter.

Yes -- in fact the design _is_ done in such a way that it doesn't depend
on the min delays. I just need to work them out in order to document them
on the system's datasheet.

The 10% rule is OK although while we're at it I may as well take zero ns
for the propagation delay. As you say:

> You can always be sure that the min delay will never be less than zero.

Sure! ;)

> Peter Alfke, Xilinx

Thanks for your helpful answer!

Regards,
Guillermo Rodriguez

Article: 64710
Subject: Re: Altera Cyclone data is incomplete or messy
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Mon, 12 Jan 2004 09:09:38 -0000
Links: << >>  << T >>  << A >>
Rene Tschaggelar <none@none.none> wrote in message
news:41c489438e778508c6ca433ed9cabaf5@news.teranews.com...
> Browsing the 'cyclone device handbook' I spent a great
> length to find :
> -the max current for each supply ( VCCIO & VCCINT )

Rene, there's a power consumption spreadsheet
downloadable for the Cyclone which will give you
figures for your application.

> -the expected clocking frequency at the input. I'm aware
>   that 1MHz may not be sufficient to PLL it up to 400MHz
>   or such.

The PLL output is
Input MHz * M/(N * post_scale_counter)
where M = 2 to 32, N and post_scale_counter = 1 to 32

I'm pretty sure I got this from the data sheets.

Have you checked you've got the latest version, they seem
to update them fairly regularly.


Nial Stewart
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone based 'Easy PCI' dev board
www.nialstewartdevelopments.co.uk



Article: 64711
Subject: Re: image file reading in vhdl
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 12 Jan 2004 10:12:36 +0000
Links: << >>  << T >>  << A >>
Mike Treseler <mike_treseler@comcast.net> writes:

> suneetha wrote:
> > I want to read an image file into vhdl....how it could be done...can u
> > please explain it in detail...
> 
> http://groups.google.com/groups?q=vhdl+binary+file+read
> 

and
http://groups.google.com/groups?q=read+pgm+file+vhdl

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 64712
Subject: Modify Memory after P&R in Xilinx Virtex2
From: "Yann Thoma" <bidon@epfl.ch>
Date: Mon, 12 Jan 2004 11:24:02 +0100
Links: << >>  << T >>  << A >>
Hi all,

I am building a design for a Virtex2 3000, including a ROM. The problem is I
would like to be able to modify the ROM content, after placement and
routing, without doing the placement and routing everytime. I know about
FPGA editor, that allow to modify memories after P&R, but only by hand, word
after word.
Does somebody knows about a way to modify it from a .coe, .cfg, or .mif
file?

Thanks in advance,

Yann



Article: 64713
Subject: Re: Modify Memory after P&R in Xilinx Virtex2
From: steven derrien <steven_derrien@yahoo.fr>
Date: Mon, 12 Jan 2004 11:55:04 +0100
Links: << >>  << T >>  << A >>
Hi Yann,

You should have a look to the DATA2BRAM command line tool
provided with ISE. This tool directly modify the memory
content of a bitstream file.

Steven

Yann Thoma wrote:
> Hi all,
> 
> I am building a design for a Virtex2 3000, including a ROM. The problem is I
> would like to be able to modify the ROM content, after placement and
> routing, without doing the placement and routing everytime. I know about
> FPGA editor, that allow to modify memories after P&R, but only by hand, word
> after word.
> Does somebody knows about a way to modify it from a .coe, .cfg, or .mif
> file?
> 
> Thanks in advance,
> 
> Yann
> 
> 


Article: 64714
(removed)


Article: 64715
Subject: pci-x core
From: Matthias =?iso-8859-1?Q?M=FCller?= <*spam*mur@iis.fhg.de>
Date: Mon, 12 Jan 2004 13:03:03 +0100
Links: << >>  << T >>  << A >>
Hi all,
Doeas anyone know if the Xilinx PCI-X core includes pinout constraints,
so it is determined which PCI-X signal is connected to which pin of a
certain package (e.g. FF1517) ?
I don't have the core documentation yet and until now I have arranged
the pinout according to the connector-signal arrangement in order to
minimize trace lengths.
Thank you for answers.
Matthias


--
Please remove *spam* from my email address if you want to contact me.



Article: 64716
Subject: Re: pci-x core
From: Mark Schellhorn <mark@seawaynetworks.com>
Date: Mon, 12 Jan 2004 07:45:59 -0500
Links: << >>  << T >>  << A >>
In includes some example UCF files for different device/package combinations 
that are known to meet timing when you implement them. The latest build includes 
files for 2vp7ff672, 2v1000-fg456, and v300ebg432 devices.

You don't have to use these. I am working into a 2v500-fg456 and have no problem 
meeting timing. I chose my pinout to line up nicely with the PCI card edge 
fingers and minimize board track length and crossovers. I did create an 
AREA_GROUP constraint for the XPCI_WRAP module in my design. It seems to meet 
timing more easily if it has a smaller area to P&R in.

     Mark

Matthias Müller wrote:
> Hi all,
> Doeas anyone know if the Xilinx PCI-X core includes pinout constraints,
> so it is determined which PCI-X signal is connected to which pin of a
> certain package (e.g. FF1517) ?
> I don't have the core documentation yet and until now I have arranged
> the pinout according to the connector-signal arrangement in order to
> minimize trace lengths.
> Thank you for answers.
> Matthias
> 
> 
> --
> Please remove *spam* from my email address if you want to contact me.
> 
> 


Article: 64717
Subject: Re: Is the P&R processing time proportional to the FPGA gate count or the size of my logic?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Mon, 12 Jan 2004 21:05:40 +0800
Links: << >>  << T >>  << A >>
Thank you all for your response. Now I understand that for same design the
run time and RAM usage do
increase with the FPGA cip size.

Best Regards,
Kelvin




"Ray Andraka" <ray@andraka.com> wrote in message
news:3FFBAAEC.D224DF2F@andraka.com...
> PAR time is related to many factors including the complexity of your
design and
> aggressiveness of the timing constraints relative to the logic delays in
your
> design.  Good floorplanning can reduce an 8 hour run to a few minutes
(I've got
> a fairly sparse - 25% utilized 2V6000 I am working with right now)
without
> placing the BRAMs, I ws getting PAR runs in the 8-10 hour range.  By
simply
> placing the BRAMs and the output pipeline registers using floorplanning,
it
> reduces the par time to under 20 minutes.
>
> "Kelvin @ SG" wrote:
>
> > Hi, there:
> >
> > I am performing active-module P&R for partial reconfiguration. My fixed
> > logic is 30K (ASIC) gates, and the
> > variable logic modules are 0.5 & 2K gates only...Now I am P&R the
variable
> > modules with a blackbox
> > for fixed module, how come it takes over 30 minutes but still ISE 6.1
> > couldn't finish this small module.
> >
> > I want to know whether the P&R time is more related to my chip size OR
the
> > size of my FPGA(Virtex2, 6000K).
> >
> > Besides that, how may I derive the output file names in multi-pass P&R,
e.g.
> > 4_4_1.ncd from my par command
> > options?
> >
> > Best Regards,
> > Kelvin
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 64718
Subject: Re: iMPACT error : Done did not go high.
From: Egads <egadsNOJUNK@fnal.gov>
Date: Mon, 12 Jan 2004 07:08:46 -0600
Links: << >>  << T >>  << A >>
In article <97f0ebf9.0401071711.1c536775@posting.google.com>, 
m_perez_gutierre@hotmail.com says...
> Hi everybody, I have been trying to configurate the Microblaze
> processor in several boards, I use iMPACT and a JTAG cable to download
> the bistream to the boards, but the process fails. The following is
> the result message :
> 
> ---------------------------------------------------------------------
> // *** BATCH CMD : Program -p 2 
> PROGRESS_START - Starting Operation.
> Validating chain...
> Boundary-scan chain validated successfully.
> Validating chain...
> Boundary-scan chain validated successfully.
> '2':Programming  device...
> done.
> INFO:iMPACT:579 - '2': Completed downloading bit file to device.
> INFO:iMPACT:580 - '2':Checking done pin ....done.
> '2': Programming terminated, Done did not go high.
> PROGRESS_END - End Operation.
> Elapsed time =      5 sec.
> ---------------------------------------------------------------------
> 
> 
> Somebody has experimented this error?
> 
>  or
> 
> Somebody know what are the common causes of this?
> 

I see this error also with a SpartanII design I'm working on.  The DONE 
pin does go high but Impact for some reason is not seeing it.  I've had 
too much other stuff going on to track it down at this time.  If I 
figure it out, I'll let you know.  If you find the problem, please post 
it...

Good luck !!!

-- 
Greg Deuerling
Fermi National Accelerator Laboratory
P.O.Box 500 MS368  Batavia, IL 60510
(630)840-4629     FAX  (630)840-5406
Electronic Systems Engineering Group
Work: egads_AT_fnal.gov, remove '_AT_'

Article: 64719
Subject: Why won't Xilinx document their code??
From: lecroy7200@chek.com (lecroy)
Date: 12 Jan 2004 05:16:16 -0800
Links: << >>  << T >>  << A >>
If I look at your latest unisim_vital.vhd and the previous version of
the file, there have been some major changes that effected my
simulation.  Interesting, once again the headers did not change. They
still show the file not being updated after 1996, ending with change
86.

I brought this up with the models in the past. 

Is there a reason that you don't want to take the time to document
your work?

Article: 64720
Subject: fpga database?
From: bob <kmart@nospam.com>
Date: Mon, 12 Jan 2004 08:34:37 -0500
Links: << >>  << T >>  << A >>
Hi Has anyone found a fpga database?

I would like to compare (mostly xilinx) FPGA and CPLDs on
functionality and price and packaging  and other options.

Article: 64721
Subject: Re: fpga database?
From: Ralph Malph <noone@yahoo.com>
Date: Mon, 12 Jan 2004 09:29:25 -0500
Links: << >>  << T >>  << A >>
bob wrote:
> 
> Hi Has anyone found a fpga database?
> 
> I would like to compare (mostly xilinx) FPGA and CPLDs on
> functionality and price and packaging  and other options.

The only data base I have seen is the data sheet.  The only place you
are likely to find pricing is direct from the distributors or you could
use the prices marketing provides.  Pricing varies widely depending on
the customer.

Article: 64722
Subject: Re: Programming and debugging the Altera Cyclone family
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Mon, 12 Jan 2004 14:35:52 -0000
Links: << >>  << T >>  << A >>

Ben Popoola <b.popoola@ntlworld.com> wrote in message
news:qmkMb.4126$OA3.1018845@newsfep2-win.server.ntli.net...

> I think that you can also program the EPCS1 via the Cyclone chip itself
> but I do not know how off head.
>
> This might work:
>
> (1) Configure the FPGA through the JTAG port.
> (2) If you have an I/O connection between your logic in the Cyclone and
> a PC, download your configuration bitstream into the EPCS1 via your
> logic in the Cyclone.
> (3) Turn the power off then on. The Cyclone should boot from the EPCS1.


I don't think it's as easy as this.

There's an IP block AMSI which a NIOS processor can use to
acesss/reconfigure an AS device, but this can't easily be
accessed without the NIOS.

Details of how it's driven aren't published so it's probably
not impossible to use, but not easy.

This seems a daft move by Altera as easy access to the AS
device allowing in system up-dates would be a good marketing
point.


Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
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Article: 64723
Subject: Re: Modify Memory after P&R in Xilinx Virtex2
From: "Yttrium" <Yttrium@pandora.be>
Date: Mon, 12 Jan 2004 15:31:54 GMT
Links: << >>  << T >>  << A >>
thanx, i was looking for the same thing!


"steven derrien" <steven_derrien@yahoo.fr> wrote in message
news:bttudc$78d$1@news.irisa.fr...
> Hi Yann,
>
> You should have a look to the DATA2BRAM command line tool
> provided with ISE. This tool directly modify the memory
> content of a bitstream file.
>
> Steven
>
> Yann Thoma wrote:
> > Hi all,
> >
> > I am building a design for a Virtex2 3000, including a ROM. The problem
is I
> > would like to be able to modify the ROM content, after placement and
> > routing, without doing the placement and routing everytime. I know about
> > FPGA editor, that allow to modify memories after P&R, but only by hand,
word
> > after word.
> > Does somebody knows about a way to modify it from a .coe, .cfg, or .mif
> > file?
> >
> > Thanks in advance,
> >
> > Yann
> >
> >
>



Article: 64724
Subject: Re: Synthesis in VHDL vs. Verilog --Thanks folks
From: Chris Carlen <crcarle@BOGUS.sandia.gov>
Date: Mon, 12 Jan 2004 07:41:01 -0800
Links: << >>  << T >>  << A >>
Bob Perlman wrote:
> On Sun, 11 Jan 2004 15:35:14 -0800, Jim Lewis <Jim@SynthWorks.com>
> wrote:
> 
> 
>>Verilog is a less consise language.  If you don't follow
>>some adhoc methodology for coding styles, you will not
>>get it right.  This fact has been proven time and time
>>again by Verilog experts who have given numerous
>>conference papers how they overcame yet another Verilog
>>issue.  And by the way, according to my sources (Cliff C.)
>>this is not a feature that is being fixed in SystemVerilog.
> 
> 
> I'm hardly an expert in Verilog, yet I have no problems writing code
> that's easily and correctly synthesized.
> 
> There are perfectly good reasons for coding in VHDL, perhaps the most
> compelling of which to me is the ability to more easily include
> placement information, e.g., RLOCs  (I'm going by what people I
> respect tell me, not personal experience).  But writing synthesizeable
> Verilog is not an issue.
> 
> I think that Janick Bergeron, the verification guru, came up with the
> best answer to the which-is-better question.  When asked which of the
> two languages he prefers, he said it's whichever one he isn't
> currently using.
> 
> Bob Perlman
> Cambrian Design Works



Thanks Bob and everyone else who responded to my inquiry.

I'm not going to get into another round of second guessing about my 
choice to use Verilog.  Since I will be using it sporadically for things 
that are only a little too complicated to do with a schematic easily, I 
could even design at the gate instantiation level if I wanted to.

I doubt I will have too much trouble, and I intend to learn as much as I 
can about synthesizability in the process of learning the language.

Good day!


-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov




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