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Messages from 65450

Article: 65450
Subject: Re: Partial Reconfig Spartan 2 - Bus Macros, which one?
From: tau14@sussex.ac.uk (Ian)
Date: 29 Jan 2004 09:39:26 -0800
Links: << >>  << T >>  << A >>
Update!!

I have tried two approaches to solve this problem.

1) open the bm_4b.mnc macro with FPGA editor and modify to suit target
architectue (i.e. spartan2)

Result FPGA editor crashes with message:

FATAL_ERROR:SpeedData:getspeeds:c:181:1:12 - bad pm for reading speed
file
please refer to answers database

which obviously has no relevent help at all!!

2) produce my own bus macro design

Result FPGA Editor crashes whenever I try to relocate a component with
the message

FATAL_ERROR:GuiUtilities:WinApp.c:$Revision - This application has
discovered an exceptional condition from which it cannot recover.
Process will terminate....Please contact the answers database

once again the answers database is about as useful as a handbrake on a
canoe.

Article: 65451
Subject: Re: building macros for Virtex-II with FPGA editor...
From: bret.wade@xilinx.com (Bret Wade)
Date: 29 Jan 2004 10:01:34 -0800
Links: << >>  << T >>  << A >>
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<4018a051$1@news.starhub.net.sg>...
> Bret
> may I know the "documented hard macro flow"? Is it an application note or
> what?
> Does the RPMs allow going parameteric? I guess a Bus Macro with a variable
> bus width is better than the current 4-bit bus...
> 
> Otherwise I may merge a lot of bus macros to make 32-bit or 64-bit Bus
> Macros...
> It's really troublesome to instantiate many Bus Macros...
> 
> 
> Kelvin

Hi Kevin,

I was refering to XAPP290 where it mentions the use of Bus Macros. No,
the RPMs would not be parameteric. The advantages of using RPMs with
Directed Routing over hard macros in general is that they exist in the
logical design where timing constraints can be applied. Also, since
hard macros are not a mainstream flow, they are more likely to run
into a tool problem as the OP found.

http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf

Regards,
Bret

Article: 65452
Subject: Re: Altera Active Serial
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Thu, 29 Jan 2004 18:02:38 -0000
Links: << >>  << T >>  << A >>
> > Hi Khim,
> > As I understand things, the Altera flash memory devices are based upon
> > standard serial flash devices  (ST microelectronics ?). Hence you would
> > program these devices as you would any normal serial memory device. You
> > only have yo be careful that you do not overwrite your configuration
data.
>
> EPCS1 == M25P10
> EPCS4 == M25P40
>
> standard serial flash from www.st.com
> altera is only ordering them them with custom lables printed :)


Antti, any idea what the relative cost of the ST part is?

Altera say they've developed the AS devices for low cost
configuration, but low quantity prices for the EPCS4 in the
UK are £8 ish, not what I'd call cheap.


Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 65453
Subject: Re: Altera Active Serial
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Thu, 29 Jan 2004 18:11:24 -0000
Links: << >>  << T >>  << A >>

"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message
news:40194a7e$0$18492$fa0fcedb@lovejoy.zen.co.uk...
> > > Hi Khim,
> > > As I understand things, the Altera flash memory devices are based upon
> > > standard serial flash devices  (ST microelectronics ?). Hence you
would
> > > program these devices as you would any normal serial memory device.
You
> > > only have yo be careful that you do not overwrite your configuration
> data.
> >
> > EPCS1 == M25P10
> > EPCS4 == M25P40
> >
> > standard serial flash from www.st.com
> > altera is only ordering them them with custom lables printed :)
>
>
> Antti, any idea what the relative cost of the ST part is?
>
> Altera say they've developed the AS devices for low cost
> configuration, but low quantity prices for the EPCS4 in the
> UK are £8 ish, not what I'd call cheap.


OK, so I got off my own arse and looked up the prices.

DigikeyUK list them at £2.93 one off, down to £1.44 for 1000,
they're probably cheaper in the States.

Time to spend a bit of time perusing data sheets I think.

Writing Altera's logo on them must be expensive :-(


Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 65454
Subject: Re: pci-x core/ XC2VP/ pin capacitance
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Thu, 29 Jan 2004 10:33:24 -0800
Links: << >>  << T >>  << A >>

Hi,

As you point out, the pin capacitance is out of
specification.  Based on the designs I have seen,
you will not have any "serious problems".  In fact,
I don't think you'll have any problems at all.

That doesn't constitute a guarantee, however.
Eric

Matthias Müller wrote:
> 
> Hallo,
> I will implement a PCI-X core in a XC2VP7, the pin capacitance of which
> is 10 pF. The PCI-X specification requires a pin capacitance of 8 pF.
> Does anyone know if there will be serious problems for operation  with
> 133MHz?
> Thank you for answers,
> Matthias

Article: 65455
Subject: Re: Asking about FPGA-SPARTAN error in synthizer
From: Mike Treseler <tres@peoplepc.com>
Date: Thu, 29 Jan 2004 11:44:37 -0800
Links: << >>  << T >>  << A >>
H.Azmi wrote:


> ERROR: a gnd net is driven by primitive gate(s) --  NET: GND0

http://groups.google.com/groups?q=gnd+net+driven+primitive+gate+vhdl

   -- Mike Treseler

Article: 65456
Subject: VirtexII Pro MMU/Cache Setup for VxWorks
From: doug.edge@coemfg.com (douge)
Date: 29 Jan 2004 14:12:31 -0800
Links: << >>  << T >>  << A >>
Can someone help with information on setting up a VirtexII Pro FPGA
with MMU/Cache support for VxWorks? I have an Insight-Memec 2VP4/7
(XC2VP4) development board and P160 Communications Module. I've built
a test system on the board and can get VxWorks to boot OK until I add
MMU/Cache support in Tornado. As soon as I add those into the VxWorks
image the system hangs after the "Starting at 0x10000..." message is
displayed.

Article: 65457
Subject: Re: PowerPC and JTAG
From: alann@accom.com (Alan Nishioka)
Date: 29 Jan 2004 14:27:10 -0800
Links: << >>  << T >>  << A >>
"Steve Casselman" <sc_nospam@vcc.com> wrote in message news:<MEjRb.16624$un.13640@newssvr27.news.prodigy.com>...
> Yes. There is an internal JTag tap that can be "tapped into" If you want to
> use the PPC Jtag you have to use the internal tap symbol.

Is this really true?  I thought the only way you could drive the JTAG
pins was with external connections from other IO pins.  The only
reference I could find to JTAG tap is the way the PPC taps into the
JTAG instruction register so the length doesn't vary depending on
whether the PPC is used or not.

Could you cite a reference?

Alan Nishioka
alann@accom.com

Article: 65458
Subject: Where to get FPGA devices for testing?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Fri, 30 Jan 2004 07:35:10 +0800
Links: << >>  << T >>  << A >>
I have found that FPGA's and cables can be easily built for fun and hobby,
but that will break my wallet...
but I don't want to buy a demo board at US$45 and pay 50US$ for UPS...And I
don't want to spend
more US$50 at all...

JTAG cable can be built with a parallel cable...but where can I find the
FPGA devices and socket for them?

Kelvin




Article: 65459
Subject: Re: Where to get FPGA devices for testing?
From: "fabbl" <yttt@nukes.com>
Date: Thu, 29 Jan 2004 23:37:34 GMT
Links: << >>  << T >>  << A >>
>And I
> don't want to spend
> more US$50 at all...

Find another hobby...Bird watching is cheap.



Article: 65460
Subject: Re: FPGA basics
From: Jim Lewis <Jim@SynthWorks.com>
Date: Thu, 29 Jan 2004 15:47:19 -0800
Links: << >>  << T >>  << A >>
Paper due soon?

Go to www.xilinx.com or www.altera.com
lots of free papers describing the basics of their
architectures.

Good luck,
Jim

Arcadius A. wrote:

> Hello!
> Please, I'm looking for documents/URLs explaining the basics of FPGA, 
> and how FPGA work.
> I've done a google search, but I couldn't find any thing simple enough 
> for me to get the idea.
> 
> All I need is the base architecture, the logic components used, and how 
> the whole works.
> 
> Thanks.
> 
> Arcadius.

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Article: 65461
Subject: Re: FPGA basics
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Thu, 29 Jan 2004 23:54:25 GMT
Links: << >>  << T >>  << A >>
Try here too
http://www.fpga4fun.com/



Article: 65462
Subject: Re: Altera Active Serial
From: khimREMOVEbittle@cliftonREMOVEsystems.com (Khim Bittle)
Date: Thu, 29 Jan 2004 23:58:34 GMT
Links: << >>  << T >>  << A >>
On 28 Jan 2004 23:43:35 -0800, antti@case2000.com (Antti Lukats)
wrote:

>Ben Popoola <b.popoola@ntlworld.com> wrote in message news:<wBoQb.11$WQ3.10@newsfep1-gui.server.ntli.net>...
>> Khim Bittle wrote:
>> > hi folks ... when using the Cyclones with the EPCS4 flash
>> > configuration chip and active serial mode ... I'd like to use the
>> > extra memory space to store a memory image ... so all I need to do is
>> > read or write it in a big block .. so yes i have done this with Nios
>> > but this is too much overhead in a small cyclone device simply to copy
>> > an image from the flash to an external ram  .. anyone know how to read
>> > the flash without using nios ?  kb
>> > 
>> Hi Khim,
>> 	As I understand things, the Altera flash memory devices are based upon 
>> standard serial flash devices  (ST microelectronics ?). Hence you would 
>> program these devices as you would any normal serial memory device. You 
>> only have yo be careful that you do not overwrite your configuration data.
>
>EPCS1 == M25P10
>EPCS4 == M25P40
>
>standard serial flash from www.st.com
>altera is only ordering them them with custom lables printed :)
>
>the problem accessing the config memory from non-nios applications is that
>quartus doesnt allow assignments to pins DATA0 and DCLK so it is not 
>possible to access the config flash memory.
>

thanks for the response , you are correct , the problem is not how the
memory chips work but how to manipulate dclk/data0 without nios ... (
i don't think quartus will let me at them ?) ... i haven't given up
yet  ..  KB



Article: 65463
Subject: Re: Is FPGA fully static?
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Thu, 29 Jan 2004 18:03:33 -0600
Links: << >>  << T >>  << A >>


Raivo Nael wrote:

>If i wish for debuging purposes lower clock frequency that i supply
>for FPGA from external source can i always do it?
>
>For example if i have borad that is intended to run with 40MHz
>external clock source and for debuging purposes i will supply 40 Hz
>clock, does circuit behave exactly as on higher speed expect that all
>happens 1 000 000 x slower or is this situation more complicated?
>  
>
The older Xilinx FPGAs that didn't have clock multipliers and DLLs
are totally static.  You could clock them with a debounced pushbutton
if you wanted to.  I think even the current ones can be used like this, but
you have to avoid the PLL and DLL components, as they do have a
specified min and max frequency.

I have several products that run Xilinx FPGAs WAY below their maximum
clock frequency, because that is all the speed needed in the application.
I have a device I'm debugging right now using an older 5V Spartan chip
that has no continuous clock whatsoever.  There are a few clocks that
are really strobes from other devices, but the part is largely 
combinatorial.
It routes signals around unpopulated bus slots in a piece of gear, reports
which slots have what boards in them, if any, and such things.

Jon


Article: 65464
Subject: Re: Where to get FPGA devices for testing?
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Fri, 30 Jan 2004 00:07:15 GMT
Links: << >>  << T >>  << A >>
hum, without changing hobby, you can find some small to medium size FPGAs
without spending too much.
Look for the Xilinx Spartan-2 and the Altera ACEX - small but still usable
devices are in the $10 to $20 range.

Sockets are expensive though ($200-$1000), so that's not a good solution to
save money.
For boards, look at http://www.fpga-faq.com/FPGA_Boards.shtml
You can find complete boards for less than $50 (most of them CPLD based
though)
The cheapest FPGA board seems to be http://www.fpga4fun.com/board_pluto.html
(10K gates) and doesn't require a parallel cable.
Anybody has other recommendations?

Jean (fpga4fun)



Article: 65465
Subject: Re: PowerPC and JTAG
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 29 Jan 2004 16:15:53 -0800
Links: << >>  << T >>  << A >>
Alan,

Page 260 of the PowerPC Processor Reference Guide covers JTAG for the 
405PPC.

www.support.xilinx.com and go to the /documentation/users guides/Device 
Families/Virtex-II Pro/

Austin

Alan Nishioka wrote:
> "Steve Casselman" <sc_nospam@vcc.com> wrote in message news:<MEjRb.16624$un.13640@newssvr27.news.prodigy.com>...
> 
>>Yes. There is an internal JTag tap that can be "tapped into" If you want to
>>use the PPC Jtag you have to use the internal tap symbol.
> 
> 
> Is this really true?  I thought the only way you could drive the JTAG
> pins was with external connections from other IO pins.  The only
> reference I could find to JTAG tap is the way the PPC taps into the
> JTAG instruction register so the length doesn't vary depending on
> whether the PPC is used or not.
> 
> Could you cite a reference?
> 
> Alan Nishioka
> alann@accom.com


Article: 65466
Subject: Re: Is FPGA fully static?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 29 Jan 2004 20:38:20 -0500
Links: << >>  << T >>  << A >>
There is a caveat on the older devices:  The 4000 series had a limitation on
the amount of time the clock could be held high to CLB RAM due to power
dissipation concerns.  I can't remember now if that included the 4000E series
or not, I don't think it did but am not sure.  So while those particular
devices were static, you had to be careful not to park the clock high if you
had any CLBRAMs in your design.

Other than that, and the DLL/DCM restrictions others have mentioned, there is
no minimum clock.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 65467
Subject: Re: Where to get FPGA devices for testing?
From: "Matt" <bielstein2002@comcast.net>
Date: Fri, 30 Jan 2004 02:02:43 GMT
Links: << >>  << T >>  << A >>
Try ebay.
Here is one with a starting bid of $10 and no bids yet!
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=2592626600&category=50913

And no it is not my board!  ;-)




"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
news:bvc3td$7h7$1@reader01.singnet.com.sg...
> I have found that FPGA's and cables can be easily built for fun and hobby,
> but that will break my wallet...
> but I don't want to buy a demo board at US$45 and pay 50US$ for UPS...And
I
> don't want to spend
> more US$50 at all...
>
> JTAG cable can be built with a parallel cable...but where can I find the
> FPGA devices and socket for them?
>
> Kelvin
>
>
>



Article: 65468
Subject: Re: Where to get FPGA devices for testing?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 29 Jan 2004 21:12:56 -0500
Links: << >>  << T >>  << A >>
Jean, neat website.  In your post you should probably have said that the pluto
board is your board.  I added a link from my links page to your site.
The Burch board is also one of the lower cost ones, but is still beyond the $50
budget.  There is a fairly comprehensive list of boards at www.optimagic.com.
Jean, you may want to send them a note with details and a link to your board.

The Xilinx spartan2  and altera acex parts can be had for not much more than a
song ($10-20 USD), and these have enough gates to do some pretty cool things.
For example, I used an $18 spartanII chip to demo a shortwave radio implemented
entirely in an FPGA except for the A to D converter and antenna (there is a
block diagram on the front page of my website).  Unfortunately, it does cost a
bit of money to make a board that is going to be robust enough to work under
hobbyist conditions and provide all the hooks to make it useful.  The insight
spartan2 board I used ran a tad over $100 USD, which is more or less the low
end.  The Burch board, and Jean's Pluto boards are about all that you'll find
cheaper.




Jean Nicolle wrote:

> hum, without changing hobby, you can find some small to medium size FPGAs
> without spending too much.
> Look for the Xilinx Spartan-2 and the Altera ACEX - small but still usable
> devices are in the $10 to $20 range.
>
> Sockets are expensive though ($200-$1000), so that's not a good solution to
> save money.
> For boards, look at http://www.fpga-faq.com/FPGA_Boards.shtml
> You can find complete boards for less than $50 (most of them CPLD based
> though)
> The cheapest FPGA board seems to be http://www.fpga4fun.com/board_pluto.html
> (10K gates) and doesn't require a parallel cable.
> Anybody has other recommendations?
>
> Jean (fpga4fun)

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 65469
Subject: Verilog code to Physical layout?
From: kkrishnan@wisc.edu (KaRtiK)
Date: 29 Jan 2004 21:16:56 -0800
Links: << >>  << T >>  << A >>
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this.. 
Any one tried this before?

Article: 65470
Subject: One bit Virtex BRAM.
From: jaxlau@yahoo.com (Jacques athow)
Date: 29 Jan 2004 21:35:17 -0800
Links: << >>  << T >>  << A >>
Is it possible to infer in vhdl, some kind of logic that has the same
property as that of a virtex block ram, but being of size 1 bit (just
using CLB logic) ??

Thanks for any ideas
jac

Article: 65471
Subject: Re: Altera Active Serial
From: antti@case2000.com (Antti Lukats)
Date: 29 Jan 2004 21:54:31 -0800
Links: << >>  << T >>  << A >>
khimREMOVEbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote in message 
> >> Khim Bittle wrote:
> >> > hi folks ... when using the Cyclones with the EPCS4 flash
> >> > configuration chip and active serial mode ... I'd like to use the
> >> > extra memory space to store a memory image ... so all I need to do is
[snip]
> thanks for the response , you are correct , the problem is not how the
> memory chips work but how to manipulate dclk/data0 without nios ... (
> i don't think quartus will let me at them ?) ... i haven't given up
> yet  ..  KB

http://wiki.openchip.org/index.php/ASMI

instantiating ASMI Block from VHDL code :)
Antti
xilinx.openchip.org

Article: 65472
Subject: Re: Where to get FPGA devices for testing?
From: antti@case2000.com (Antti Lukats)
Date: 29 Jan 2004 22:03:57 -0800
Links: << >>  << T >>  << A >>
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<bvc3td$7h7$1@reader01.singnet.com.sg>...
> I have found that FPGA's and cables can be easily built for fun and hobby,
> but that will break my wallet...
> but I don't want to buy a demo board at US$45 and pay 50US$ for UPS...And I
> don't want to spend
> more US$50 at all...
> 
> JTAG cable can be built with a parallel cable...but where can I find the
> FPGA devices and socket for them?
> 
> Kelvin

be smart. be smarter.

at www.ebay.com you can find FPGA BGA pulls at price from 
$9 for 300,000 gates and $49 for 1M Gates FPGA

even if it looks undoable at the first look BGA chips
with ball distance of 1mm+ and not full grid are easily 
used in wire wrap proto boards.

just put it balls up onto some PCB board, connect GND and VCCxx
and JTAG and ready is your FPGA proto board in budget.

My proto worked at first attempt, power on and impact reported
device found in JTAG chain.

Antti
xilinx.openchip.org
P.S. if somebody doesnt believe I can post some photos of the
working proto board

PPS there is a catch - those cheap FPGA pulls, they are mostly
Virtex FPGA so can not be used with free WebPack :(

but I also obtained some Altera FGPAs they should be useable
in above mentioned manner and with free Quartus, I even have
some 'oveleft' chips if you want them

Article: 65473
Subject: Re: Where to get FPGA devices for testing?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 30 Jan 2004 08:26:44 +0000
Links: << >>  << T >>  << A >>
antti@case2000.com (Antti Lukats) writes:

<snip>
> even if it looks undoable at the first look BGA chips
> with ball distance of 1mm+ and not full grid are easily 
> used in wire wrap proto boards.
> 
> just put it balls up onto some PCB board, connect GND and VCCxx
> and JTAG and ready is your FPGA proto board in budget.
> 
> My proto worked at first attempt, power on and impact reported
> device found in JTAG chain.
> 
> Antti
> xilinx.openchip.org
> P.S. if somebody doesnt believe I can post some photos of the
> working proto board
> 

I believe you, but I'd still like to see the pictures!

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 65474
Subject: Re: Where to get FPGA devices for testing?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Fri, 30 Jan 2004 09:49:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
Antti Lukats <antti@case2000.com> wrote:
: "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<bvc3td$7h7$1@reader01.singnet.com.sg>...
: > I have found that FPGA's and cables can be easily built for fun and hobby,
: > but that will break my wallet...
: > but I don't want to buy a demo board at US$45 and pay 50US$ for UPS...And I
: > don't want to spend
: > more US$50 at all...
: > 
: > JTAG cable can be built with a parallel cable...but where can I find the
: > FPGA devices and socket for them?
: > 
: > Kelvin

: be smart. be smarter.

: at www.ebay.com you can find FPGA BGA pulls at price from 
                                        ^^^^^
What do you mean here?

: $9 for 300,000 gates and $49 for 1M Gates FPGA

: even if it looks undoable at the first look BGA chips
: with ball distance of 1mm+ and not full grid are easily 
: used in wire wrap proto boards.

Which FBGA FPGA is not full grid?

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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