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Messages from 94400

Article: 94400
Subject: Re: FPGA and video generation
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 14:14:24 +0100
Links: << >>  << T >>  << A >>
"Johan" <jvm.jr@pandora.be> schrieb im Newsbeitrag 
news:ei7xf.93683$ZL.6095929@phobos.telenet-ops.be...
> Dear hobbyists,
>
> I need some advice on FPGA's. One of my projects involves VGA video 
> generation (with AVR microcontroller). I want to use FPGA's instead of MCU 
> to produce higher resolutions. The FPGA should read data from sram and 
> send it to a D/A converter. Wich FPGA can I use for this? Altera, Xilinx? 
> I suppose I need to write the code in Verilog? Wich of the two has the 
> best free of least expensive software?
>
> Thanks in advance
>
> Johan
>
>
pretty much all vendors have free sw that is sufficent for your purposes
you can also use any FPGA, its all up to you what to choose

you can write in verilog VHDL or design in schematics whatever you
like the best, there are plenty of VGA/display examples available
so its the best to get some sample code and check it out and then
start modifiying to your needs or write your own

www.fpga4fun.com has very simple pong game, well it is not
using any memory at all, but its very simple and easy

there are many more complex projects, just search the net



-- 
Antti Lukats
http://www.xilant.com 



Article: 94401
Subject: Re: FPGA configuration time for PCI identification ?
From: "Gabor" <gabor@alacron.com>
Date: 11 Jan 2006 05:28:21 -0800
Links: << >>  << T >>  << A >>

Kolja Sulimma wrote:
> sjulhes schrieb:
> > Ok, I found it !
> >
> > But what about the PCI express ?
> > I don't have the spec so if someone can tell me if there is the same process
> > and what is the allowed time ?
> >
>
> PCIe is hot plug capable, so it probably does not matter.
> Just tell the system that your device is present when you finished
> configuration.
>
> Kolja Sulimma

As I read the PCIe specification, it seems that the hot plug capability
is optional on the system board, so this may not always work.  The
timing of PERST# is minimum 100ms after power stable and 100us
after REFCLK stable.


Article: 94402
Subject: SDRAM Clock Skew
From: "Pouria" <pouria@hotmail.com>
Date: Wed, 11 Jan 2006 07:42:47 -0600
Links: << >>  << T >>  << A >>
HI Everybody!

I'm having a timing problem interfacing with my SDRAM bank. I'm using
256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
So far I have only been working at 40 Mhz.

I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
for clocking the SDRAM. The design works if I DON'T use the external
feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
the feedback (Which according to Xilinx should be the correct way to
terminate clock Skew). 

The feedback to the other DLL is taken from clock output of it self, and I
have used IBUG/OBUF/BUFG so that is not the problem.

Hope some one can help me .
Best regards,
/P

 




Article: 94403
Subject: Samples
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Wed, 11 Jan 2006 07:42:57 -0600
Links: << >>  << T >>  << A >>
Can you get samples from Xilinx, Altera or Lattice? Or where is the
cheapest place to buy small quantities?

Thanks

Jon




Article: 94404
Subject: Re: SDRAM Clock Skew
From: "Gabor" <gabor@alacron.com>
Date: 11 Jan 2006 05:57:18 -0800
Links: << >>  << T >>  << A >>

Pouria wrote:
> HI Everybody!
>
> I'm having a timing problem interfacing with my SDRAM bank. I'm using
> 256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
> So far I have only been working at 40 Mhz.
>
> I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
> for clocking the SDRAM. The design works if I DON'T use the external
> feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
> the feedback (Which according to Xilinx should be the correct way to
> terminate clock Skew).
>
> The feedback to the other DLL is taken from clock output of it self, and I
> have used IBUG/OBUF/BUFG so that is not the problem.
>
> Hope some one can help me .
> Best regards,
> /P

This really sounds like you are getting hold time violations.  I think
for standard
single-data-rate SDRAM 100 MHz should be very easy to attain if you
register
everything in the IOB's, and your clocks at the SDRAM and Virtex are in
phase.
In my past designs with these parts I distributed the 100 MHz from a
central
clock resource to the SDRAM chips and the FPGA.  I was able to run
without
using DLL or DCM at 100 MHz, just using the clock from a global input
pin
through the associated BUFG.  Thus my internal clock was somewhat
delayed
from the SDRAM clock, but using the standard IOB input timing there
should
be no hold time violation.  It is important to use fast slew rate on
the output
buffers or you will definitely get setup time violations at the SDRAM.


Article: 94405
Subject: Re: Samples
From: "Gabor" <gabor@alacron.com>
Date: 11 Jan 2006 06:05:35 -0800
Links: << >>  << T >>  << A >>

maxascent wrote:
> Can you get samples from Xilinx, Altera or Lattice? Or where is the
> cheapest place to buy small quantities?
>
> Thanks
>
> Jon

You could probably get samples from any of these companies if you can
convince them that your ongoing business is sufficient.  You can pretty
much forget samples if your ongoing usage is small.  Also it's often
easier
to get samples (and freebies like software) from the "other" guys, i.e.
the
ones you don't currently do business with but are waiting in the wings
to
steal your sockets from your current supplier.

Small quantity purchases are usually at list price from the franchised
distributors and your best place will depend on your location.  I know
that
at least Xilinx has a policy of supporting the distributor that brings
in your
business, so although you can buy parts anywhere you will always get
the best price from your "registered" distributor.  If you're thinking
of
developing a new relation with Xilinx (and possibly others) you should
think carefully about your own distributor preferences before you
start.

Just my 2 cents,
Gabor


Article: 94406
Subject: Re: Samples
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 15:12:36 +0100
Links: << >>  << T >>  << A >>
"maxascent" <maxascent@yahoo.co.uk> schrieb im Newsbeitrag 
news:DfmdnUpOU__8lljeRVn-uA@giganews.com...
> Can you get samples from Xilinx, Altera or Lattice? Or where is the
> cheapest place to buy small quantities?
>
> Thanks
>
> Jon

it is possible to get samples from: Atmel (FPSLIC), Actel, Altera, Lattice 
and Xilinx however you are probably easier to just buy what you want, both 
xilinx and altera have FPGAs in their online shops, prices start from about 
10USD

optionally it may actually make more sense to buy some low low cost eval 
board

avnet S3e board is 69USD

http://www.oho-elektronik.de/
89EUR spartan3 module

http://www.hardware-design.de/produkte.html

there are lattice cheap boards 60EUR or so

at 99-149 USD price there are many more

you can of course do the board yourself
http://xilant.com/content/view/35/2/

sometimes ebay has FPGAs are low low price, so I made my first 2Million Gate 
FPGA board with 49USD pulled BGA what I got from ebay

its all up to you, if you have no FPGAs and no FPGA boards I suggest buying 
the first eval board, either TREX C1 or then wait for the Xilinx Spartan3E, 
of if your budget is below 100USD then choose from other offerings

-- 
Antti Lukats
http://www.xilant.com



Article: 94407
Subject: Re: SDRAM Clock Skew
From: Joseph Samson <user@example.net>
Date: Wed, 11 Jan 2006 14:13:25 GMT
Links: << >>  << T >>  << A >>
> Pouria wrote:
> 
>>HI Everybody!
>>
>>I'm having a timing problem interfacing with my SDRAM bank. I'm using
>>256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
>>So far I have only been working at 40 Mhz.
>>
>>I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
>>for clocking the SDRAM. The design works if I DON'T use the external
>>feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
>>the feedback (Which according to Xilinx should be the correct way to
>>terminate clock Skew).
>>
>>The feedback to the other DLL is taken from clock output of it self, and I
>>have used IBUG/OBUF/BUFG so that is not the problem.

As Gabor pointed out, register all signals in the IOBs and use fast slew 
rate drivers. I highly recommend using the DDR IOB flipflop to generate 
the SDRAM clock. That dramatically improved my SDRAM design, and now I 
generate all external clocks that way. You might have good luck sending 
an inverted clock to the SDRAMs. I don't use the clock feedback.

Once you get the design running, experiment with lowering the output 
drive. The default is 12mA, but my layout allows me to go as low as 4mA.

---
Joe Samson
Pixel Velocity

Article: 94408
Subject: Re: Stepping vs. ES
From: "Sophie Liu" <mailwz@263.net>
Date: Wed, 11 Jan 2006 23:25:30 +0800
Links: << >>  << T >>  << A >>
hi dears:
    OK, I see! Thank  you very much!

"Austin Lesea" <austin@xilinx.com> ??????:dpudf7$f6s7@xco-news.xilinx.com...
> Jude,
>
> ES marking implies that the:
> -test program is not final (parts are almost ready for production release)
> or
> -the verification and characterization is not complete (early silicon,
> not all errata are known, or there is still work to do to characterize
> the parts)
> or
> -the part is from a lot that has not finished process qualification
> (also early silicon, but all process qual tests may still be incomplete)
>
> Once we have the final test program coverage we require, and the
> verification and characterization os signed off, and the process
> qualification is complete, then we stop marking parts as "ES."
>
>
> Stepping relates to the features.  Stepping 1 may have more features
> than stepping 0 (and may also have fewer errata, or no errata at all).
>
> The stepping program makes it such that a newer stepping is backward
> (bitstream) compatible with an older stepping (the old bitstream
> provides the same performance).  To gain the new features, a new
> bitstream may be required.
>
> Austin 



Article: 94409
Subject: Verilog Code for echo on Serial Port
From: "Prateek Singhal" <singhal.prateek@gmail.com>
Date: 11 Jan 2006 07:29:12 -0800
Links: << >>  << T >>  << A >>
Hi,

I need a Verilog code for echoing back the bytes recieved on a serial
port. I am using Xilinx Spartan-3 FPGA. Could anyone give me some
simple code?

Thanks a lot in adavnce,

Prateek Singhal


Article: 94410
Subject: Re: Verilog Code for echo on Serial Port
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 16:36:30 +0100
Links: << >>  << T >>  << A >>
"Prateek Singhal" <singhal.prateek@gmail.com> schrieb im Newsbeitrag 
news:1136993352.093400.28470@g44g2000cwa.googlegroups.com...
> Hi,
>
> I need a Verilog code for echoing back the bytes recieved on a serial
> port. I am using Xilinx Spartan-3 FPGA. Could anyone give me some
> simple code?
>
> Thanks a lot in adavnce,
>
> Prateek Singhal
>

yes, here it is:

assign TXD = RXD;

that should do it, works for all baudrates!!

-- 
Antti Lukats
http://www.xilant.com 



Article: 94411
Subject: best evm for virtex-4 and linux
From: "Anonymous" <someone@microsoft.com>
Date: Wed, 11 Jan 2006 15:47:56 GMT
Links: << >>  << T >>  << A >>
Can anyone suggest the best evm board for virtex-4 and linux? How has
people's experience been with it? Are USB drivers included in the linux os
builds they provide?

Thanks,
Clark



Article: 94412
Subject: Re: FPGA and video generation
From: Mike Harrison <mike@whitewing.co.uk>
Date: Wed, 11 Jan 2006 15:54:04 GMT
Links: << >>  << T >>  << A >>
On Wed, 11 Jan 2006 14:14:24 +0100, "Antti Lukats" <antti@openchip.org> wrote:

>"Johan" <jvm.jr@pandora.be> schrieb im Newsbeitrag 
>news:ei7xf.93683$ZL.6095929@phobos.telenet-ops.be...
>> Dear hobbyists,
>>
>> I need some advice on FPGA's. One of my projects involves VGA video 
>> generation (with AVR microcontroller). I want to use FPGA's instead of MCU 
>> to produce higher resolutions. The FPGA should read data from sram and 
>> send it to a D/A converter. Wich FPGA can I use for this? Altera, Xilinx? 
>> I suppose I need to write the code in Verilog? Wich of the two has the 
>> best free of least expensive software?
>>
>> Thanks in advance
>>
>> Johan
>>
>>
>pretty much all vendors have free sw that is sufficent for your purposes
>you can also use any FPGA, its all up to you what to choose
>
>you can write in verilog VHDL or design in schematics whatever you
>like the best, there are plenty of VGA/display examples available
>so its the best to get some sample code and check it out and then
>start modifiying to your needs or write your own
>
>www.fpga4fun.com has very simple pong game, well it is not
>using any memory at all, but its very simple and easy
>
>there are many more complex projects, just search the net

You could probably also do it in a CPLD (e.g. Xilinx 95xx series) if cost is an issue and you have
the time to optimise it to fit, but an FPGA will give you plenty of room to play with - e.g. Xilinx
Spartan-3 series. 
Another advantage with FPGA is that you have some RAM to play with which may help buffering data to
and from the SRAM,a nd also allows room for things like fonts etc. 

Article: 94413
Subject: PLX PCI9656
From: "sjulhes" <t@aol.fr>
Date: Wed, 11 Jan 2006 16:56:12 +0100
Links: << >>  << T >>  << A >>
Hello everybody,

I would like to know if the PLX PCI9656 can support the following PCI modes
upon the slot it is plugged in :
3.3V 64 bits / 66 Mhz

3.3V 32 bits / 33 Mhz

5V 32 bits / 33 Mhz

Thank you for your fast answer.

Stéphane




Article: 94414
Subject: Re: FPGA and video generation
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 17:11:48 +0100
Links: << >>  << T >>  << A >>
"Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag 
news:lpaas1hmbai2h63a0ds04rmqhjatqt8u8b@4ax.com...
> On Wed, 11 Jan 2006 14:14:24 +0100, "Antti Lukats" <antti@openchip.org> 
> wrote:
>
>>"Johan" <jvm.jr@pandora.be> schrieb im Newsbeitrag
>>news:ei7xf.93683$ZL.6095929@phobos.telenet-ops.be...
>>> Dear hobbyists,
>>>
>>> I need some advice on FPGA's. One of my projects involves VGA video
>>> generation (with AVR microcontroller). I want to use FPGA's instead of 
>>> MCU
>>> to produce higher resolutions. The FPGA should read data from sram and
>>> send it to a D/A converter. Wich FPGA can I use for this? Altera, 
>>> Xilinx?
>>> I suppose I need to write the code in Verilog? Wich of the two has the
>>> best free of least expensive software?
>>>
>>> Thanks in advance
>>>
>>> Johan
>>>
>>>
>>pretty much all vendors have free sw that is sufficent for your purposes
>>you can also use any FPGA, its all up to you what to choose
>>
>>you can write in verilog VHDL or design in schematics whatever you
>>like the best, there are plenty of VGA/display examples available
>>so its the best to get some sample code and check it out and then
>>start modifiying to your needs or write your own
>>
>>www.fpga4fun.com has very simple pong game, well it is not
>>using any memory at all, but its very simple and easy
>>
>>there are many more complex projects, just search the net
>
> You could probably also do it in a CPLD (e.g. Xilinx 95xx series) if cost 
> is an issue and you have
> the time to optimise it to fit, but an FPGA will give you plenty of room 
> to play with - e.g. Xilinx
> Spartan-3 series.
> Another advantage with FPGA is that you have some RAM to play with which 
> may help buffering data to
> and from the SRAM,a nd also allows room for things like fonts etc.

now when you mentioned PLD, there is 8 bit VGA project using small PLD and 
SRAM chips
http://www.ulrichradig.de/index.html

seek PLD there is link to the design...


-- 
Antti Lukats
http://www.xilant.com



Article: 94415
Subject: Re: PLX PCI9656
From: amyler@eircom.net
Date: 11 Jan 2006 08:16:03 -0800
Links: << >>  << T >>  << A >>
sjulhes wrote:
> Hello everybody,
>
> I would like to know if the PLX PCI9656 can support the following PCI mod=
es
> upon the slot it is plugged in :
> 3.3V 64 bits / 66 Mhz
>
> 3.3V 32 bits / 33 Mhz
>
> 5V 32 bits / 33 Mhz
>
> Thank you for your fast answer.
>
> St=E9phane

Hi Stephane,

Have you looked at the datasheet for this information?

http://www1.plxtech.com/TEMP/57839/9656BA_DataBook_v1.1.pdf

The electrical spec' section describes how to use it in a 5V PCI
system.

So it looks like yes yes and yes are your answers.

Best regards,

Alan


Article: 94416
Subject: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 11 Jan 2006 17:23:45 +0100
Links: << >>  << T >>  << A >>
Antti.Lukats@xilant.com writes:

> http://wiki.openchip.org/index.php/Altera:JTAG
> 
> MAXII is similar to Cyclone, I have verified that in silicon

Thanks!

BTW, is there a way to make quartus_pgm play SVF files (or convert SVF
into some other format I can play)? I would like to play the following
file:

SIR 10 TDI (007);
SDR 32 TDI (FFFFFFFF); ! or some other pattern

I would then expect to observe the USERCODE value being shifted out of
the maxii_jtag module from my user logic.


Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 94417
Subject: UCF-File problem
From: foag@iti.uni-luebeck.de
Date: 11 Jan 2006 08:35:14 -0800
Links: << >>  << T >>  << A >>
While compliling my VHDL design with XILINX ISE, I received the
following error concerning a IO-constraint:

Annotating constraints to design from file "noc_top.ucf" ...
ERROR:NgdBuild:755 - Line 7 in 'noc_top.ucf': Could not find net(s)
'lclk' in
   the design.  To suppress this error specify the correct net name or
remove
   the constraint.  The 'Ignore I\O constraints on Invalid Object
Names'
   property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
"noc_top.ucf".

In the design top level file, lclk is an input port.

Entity of TOP-LEVEL-VHDL-File:
entity noc_top is
  port(
    lclk : in std_logic;
    boardout : out std_logic_vector(6 downto 0);
    anode : out std_logic);
end noc_top;

Corresponding UCF-File
##########################################################
NET "lclk"           LOC=3D"T9";
NET "boardout<6>"    LOC=3D"E13";
NET "boardout<5>"

If I change the port name simultaneously in the design file and in the
ucf, the error is still indicated.

Does is depend on the port direction (all output port are mapped
correctly) ?

Any ideas ???
J=FCrgen


Article: 94418
Subject: Re: Xilinx Spartan3E Sample Pack 3rd party programing support now available
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 17:40:58 +0100
Links: << >>  << T >>  << A >>
[snip]
> nahitafu is using MITOU JTAG tool for flash programming of the sample pack
> but as that tool is not free and has no eval so our Flash programming 
> utility for the Sample Pack is the first freely available and proven 
> working solution to reflash the strataflash on the Sample Pack board.
>
> the base functionality of the tool is FREE of charge, there is no 
> registration required, just download unzip and get start
>

I just received a bit angry email from Nahitafu about my nonpolite wording
about their products, so here is goes public appology to Nahitech, sorry !

additional info from Nahiteh: There will be no MITOUJTAG trial or
evaluation versions available over internet, but a free evaluation of
MITOUJTAG is offered for those who attend one of the upcoming
trade shows in Japan.
http://www.reedexpo.co.jp/inj/english/
there will be MITOUJTAG eval available, I wish I could go
my 3 days visit to Tokyo is one of my best memories of all my travels.

Sorry, Nahitafu - I did not mean to say bad about yours products
I just think they are getting too little exposure in non-japanese
speaking world.

http://www.nahitech.com/jtag/basicv.html

I dont find any english description any more, it used to be online
also a evaluation version was available, what I have tested and
it worked - the commercial version of MITOUJTAG is most
likely much better than the very old version what was available
as free version.

Antti



Article: 94419
Subject: Re: FPGA and video generation
From: "Johan" <jvm.jr@pandora.be>
Date: Wed, 11 Jan 2006 16:42:44 GMT
Links: << >>  << T >>  << A >>
Thank you very much for the quick reply's. This is exactly what I wanted to 
know. The CPLD graphics card is able to generate a pretty high resolution. I 
was thinking to use CPLD's but wasn't sure if it would work.

Thank you guy's!!



Article: 94420
Subject: Re: UCF-File problem
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 17:42:47 +0100
Links: << >>  << T >>  << A >>
><foag@iti.uni-luebeck.de> schrieb im Newsbeitrag 
>news:1136997314.865085.276220@g44g2000cwa.googlegroups.com...
>While compliling my VHDL design with XILINX ISE, I received the
>following error concerning a IO-constraint:
>
>Annotating constraints to design from file "noc_top.ucf" ...
>ERROR:NgdBuild:755 - Line 7 in 'noc_top.ucf': Could not find net(s)
>'lclk' in   the design.  To suppress this error specify the correct net 
>name or
>remove

[snip]

if your input port is optimized away then it comes non-existant and UCF 
mapper will fail


-- 
Antti Lukats
http://www.xilant.com 



Article: 94421
Subject: Re: UCF-File problem
From: foag@iti.uni-luebeck.de
Date: 11 Jan 2006 08:49:51 -0800
Links: << >>  << T >>  << A >>
Hi Antti,
if I have a look into the generated "View RTL Schematic" (*.ngr), I can
see the input port "lclk"


Article: 94422
Subject: Re: best evm for virtex-4 and linux
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 17:49:57 +0100
Links: << >>  << T >>  << A >>
"Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag 
news:MM9xf.5246$Kp.178@southeast.rr.com...
> Can anyone suggest the best evm board for virtex-4 and linux? How has
> people's experience been with it? Are USB drivers included in the linux os
> builds they provide?
>
> Thanks,
> Clark
>
I may be mistaken but I think there are no Virtex4 linux ready currently 
shipping with both device and host support drivers for USB

Virtex-4 based modules from
http://www.hydraxc.com/

eg LX15, LX25 and FX12 based units are currently all shipping, but the 
included ucLinux reference design does not include USB drivers, this will be 
supplied later on, currently only some standalone USB firmware samples are 
included.

There are possible other boards or modules with partial USB support, but 
with device and host (OTG) support already included I doubt that you find 
anything at the moment, you can possible find something with host support 
only

Antti



Article: 94423
Subject: Re: UCF-File problem
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 11 Jan 2006 17:52:17 +0100
Links: << >>  << T >>  << A >>
<foag@iti.uni-luebeck.de> schrieb im Newsbeitrag 
news:1136998191.769635.302560@g43g2000cwa.googlegroups.com...
> Hi Antti,
> if I have a look into the generated "View RTL Schematic" (*.ngr), I can
> see the input port "lclk"
>
well if the lclk is retained after that then it isnt the problem, but RTL 
view doesnt mean that the lclk do not get optimiued away later so check if 
it is really used and not optimized, for testing uncomment the ucf and check 
if lclk is mapped to some pin or not, if it is then the UCF should work as 
well

-- 
Antti Lukats
http://www.xilant.com 



Article: 94424
Subject: Back to Power?
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 11 Jan 2006 08:55:06 -0800
Links: << >>  << T >>  << A >>
Brian,

DCI parallel power is fact.  Multiply the number of DCI by the power, 
and you get an answer.

So what?  Our static power is demostratably less than other 90nm 
"solutions", and our dynamic power is similar.  It amounts to 1 to 5 
watts.  Could you program the DCI in parallel termination mode and eat 
up the advantage?  Sure!  But then, I would not need hundreds of 
resistors, either.  Did the job, with the same power, but with less 
resistors.  You choose how to burn the power, you choose how to spend 
the power advantage. Power advantage allows use of

Same design, less power.  Different design, different power.

The advantages are clear.  There is no apology required.

Austin




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