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Messages from 6050

Article: 6050
Subject: Re: Chip Temperature (was:Re: Sole source)
From: Martin d'Anjou <mdanjou@nortel.ca>
Date: Tue, 08 Apr 1997 09:34:04 -0400
Links: << >>  << T >>  << A >>
Martin d'Anjou wrote:
>(that's also how you can get
> boiling water below 100 C - just add salt).
> 
hummmm.... I not so sure after all. Let me check my thermodynamic
textbooks.

Martin.

-- 
| Martin d'Anjou                  | tel: (613) 765-3058               |
| Nortel                          | fax: (613) 763-9535               |
| P.O. Box 3511, Station C        | email: mdanjou@nortel.ca          |
| Ottawa, Ontario, CANADA  K1Y 4H7| My opinions, not Nortel's         |
| http://www.nortel.com/          | Mes opinions, pas celles de Nortel|
Article: 6051
Subject: temperature (was Re: Sole source)
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Tue, 8 Apr 1997 15:00:03 GMT
Links: << >>  << T >>  << A >>
In article <peter-0404970844470001@appsmac-1.xilinx.com>,
Peter Alfke <peter@xilinx.com> wrote:
>The threshold of pain in your fingertip is above 60 degrees C. If you can
>hold youe fingertip on the device surface for several seconds, then the
>temperature is below 65 degrees Celsius ( or centigrade for non-Europeans).

It's Celsius here too; only USAnians think it's Centigrade. :-)

>That used to be an old rule for electrical machinery: put your hand on it,
>if it's not painful, there is no danger to the insulation...

Actually, there's a more modern rule of thumb for electronics:  if you
can't keep your finger on the chip, you should rethink the design.  (Not
that it can always be avoided, but it *is* a sign of trouble.)
-- 
Committees do harm merely by existing.             |       Henry Spencer
                           -- Freeman Dyson        |   henry@zoo.toronto.edu
Article: 6052
Subject: Re: Chip Temperature (was:Re: Sole source)
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Tue, 8 Apr 1997 15:03:18 GMT
Links: << >>  << T >>  << A >>
In article <33493EFD.5E6D@nortel.ca>,
Martin d'Anjou  <mdanjou@nortel.ca> wrote:
>> Saliva is mostly water and therefore boils ans sizzles at 100 degrees C. (
>
>Saliva contains some minerals too (NaCl), which lower the temperature
>at which the water boils by a few degrees (that's also how you can get
>boiling water below 100 C - just add salt).

Right idea, wrong direction -- adding salt *raises* the boiling point. 
See any decent chemistry text.  In the kitchen, when you add salt to a
pot that's boiling over, it stops boiling.

Not that it matters much in this case. :-)
-- 
Committees do harm merely by existing.             |       Henry Spencer
                           -- Freeman Dyson        |   henry@zoo.toronto.edu
Article: 6053
Subject: Re: Reconfig computing and multimedia?
From: jmarnold@potomac.znet.com (Jeffrey M. Arnold)
Date: 8 Apr 1997 08:03:35 -0700
Links: << >>  << T >>  << A >>
In article <334AAE54.E74@ludd.luth.se>,
Joachim Strömbergson  <watchman@ludd.luth.se> wrote:
>Hi!
>
>I have been offered the opportunity to investigage reconfig computing as
>a master thesis project. The area suggested would be multimedia aspects
>of reconfig computing. I have not been given any real instructions and
>are therefor searching for information concerning:
>
>* Current research.
>* Multimedia problems that would be especially suitable to solve with
>reconfig computing.
>* Any reference and pointers to existing resources, commercial
>applications using reconfig computing.

I suggest starting with the on-line bibliography maintained by Brigham
Young University: http://splish.ee.byu.edu:80/rllhome.html.  In
addition, there are several annual conferences which focus at least in
part on reconfigurable computing:

	IEEE FCCM (in Napa, CA next week!), proceedings published by
IEEE Computer Society Press (see http://www.fccm.org)

	FPL (in London, 1-3 Sept), proceedings published by
Springer-Verlag in the LNCS series

	ACM FPGA (in Monterey, CA in Feb), proceedings published by
the Association for Computing Machinery

	SPIE Photonics East, proceedings published by The
International Society for Optical Engineering (SPIE)
	

-jeff (co-chair, FCCM'97)
-- 
Jeffrey M. Arnold		jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace		Tel: 619-547-9257
San Diego, CA 92131		Fax: 619-547-9010
USA
Article: 6054
Subject: Re: Chip Temperature (was:Re: Sole source)
From: Jason.Wright@ebu.ericsson.com (Jason T. Wright)
Date: Tue, 08 Apr 1997 15:20:16 GMT
Links: << >>  << T >>  << A >>
On Mon, 07 Apr 1997 14:37:49 -0400, Martin d'Anjou <mdanjou@nortel.ca>
wrote:

>Peter Alfke wrote:
>
>> Saliva is mostly water and therefore boils ans sizzles at 100 degrees C. (
>
>Saliva contains some minerals too (NaCl), which lower the temperature
>at which the water boils by a few degrees (that's also how you can get
>boiling water below 100 C - just add salt).

It's been a while since I took chemistry, but if my memory serves me
correctly, adding salt (and other things) raises the boiling
temperature ...

I did a search on yahoo that came up with the same answer:
      http://www.hcrhs.hunterdon.k12.nj.us/science/salt.html

>
>My $0.02 CAN
>Martin.
>-- 
>| Martin d'Anjou                  | tel: (613) 765-3058               |
>| Nortel                          | fax: (613) 763-9535               |
>| P.O. Box 3511, Station C        | email: mdanjou@nortel.ca          |
>| Ottawa, Ontario, CANADA  K1Y 4H7| My opinions, not Nortel's         |
>| http://www.nortel.com/          | Mes opinions, pas celles de Nortel|

Article: 6055
Subject: Re: Reconfig computing and multimedia?
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 8 Apr 1997 15:23:36 GMT
Links: << >>  << T >>  << A >>
There are numerous links to reconfigurable computing (even some for
multimedia) on the Programmable Logic Jump Station.  Check out the research
section at:

'http://www.netcom.com/~optmagic/research.html'
-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Joachim Strömbergson <watchman@ludd.luth.se> wrote in article
<334AAE54.E74@ludd.luth.se>...
| Hi!
| 
| I have been offered the opportunity to investigage reconfig computing as
| a master thesis project. The area suggested would be multimedia aspects
| of reconfig computing. I have not been given any real instructions and
| are therefor searching for information concerning:
| 
| * Current research.
| * Multimedia problems that would be especially suitable to solve with
| reconfig computing.
| * Any reference and pointers to existing resources, commercial
| applications using reconfig computing.
| 
| No, I'm not asking anyone to do my homework, I'm trying to find a field
| to do my work in. I will greatly appreciate any suggestions I can get.
| 
| -- 
| Cheers!
| Joachim - Alltid i harmonisk svängning
| --------------------------------------------------------
| Joachim Strömbergson  MSc Student, nice to CUTE animals.
| Porsögården 24:6    PC    e-mail : watchman@ludd.luth.se
| 977 54 Luleå       C64       phone: +46(0)920 - 22 16 42
| Sweden         -FairLight-   alt:   +46(0)10 - 22 10 543
| --------------------------------------------------------
| 
Article: 6056
Subject: fpga technologies and Iddq testing
From: "Rich K." <rich.katz@gsfc.nasa.gov>
Date: 8 Apr 1997 17:19:28 GMT
Links: << >>  << T >>  << A >>
Hi,

Iddq testing has been shown to be a good technique for detecting faults in
many types of circuits, including FPGAs.  The technique relies on the fact
that in CMOS circuits, voltages switch from rail to rail and there is no DC
current through any gates.  However, in routing of signals in FPGAs signals
often go through n-channel pass transistors, i understand, and there would
be a drop in voltage across this structure.  is this correct?  if so, does
this result in a small positive bias of the p-channel fets and increased
leakage current when logical '1' signals are propagated?

I am interested in how this applies to many different types of FPGAs and
would appreciate comments from readers of this newgroup.

Thanks a bunch,

rk 
Article: 6057
Subject: Re: Reconfig computing and multimedia?
From: Rhondalee Rohleder <104126.311@CompuServe.COM>
Date: 8 Apr 1997 20:36:19 GMT
Links: << >>  << T >>  << A >>
Joachim,

For advice on which multimedia applications would be most 
appropriate for a reconfigurable computing approach, try 
contacting:
Gerry Kaufhold, sr. analyst for multimedia, In-Stat
email address:  73700.3056@compuserve.com

He's very good in this area and may help you out.

Rhondalee Rohleder
Pace Technologies (Scottsdale, AZ)
ASIC market research

-- 
R. Rohleder
Pace_Research@compuserve.com
Article: 6058
Subject: Reconfig computing and multimedia?
From: Joachim Strömbergson <watchman@ludd.luth.se>
Date: Tue, 08 Apr 1997 13:45:08 -0700
Links: << >>  << T >>  << A >>
Hi!

I have been offered the opportunity to investigage reconfig computing as
a master thesis project. The area suggested would be multimedia aspects
of reconfig computing. I have not been given any real instructions and
are therefor searching for information concerning:

* Current research.
* Multimedia problems that would be especially suitable to solve with
reconfig computing.
* Any reference and pointers to existing resources, commercial
applications using reconfig computing.

No, I'm not asking anyone to do my homework, I'm trying to find a field
to do my work in. I will greatly appreciate any suggestions I can get.

-- 
Cheers!
Joachim - Alltid i harmonisk svängning
--------------------------------------------------------
Joachim Strömbergson  MSc Student, nice to CUTE animals.
Porsögården 24:6    PC    e-mail : watchman@ludd.luth.se
977 54 Luleå       C64       phone: +46(0)920 - 22 16 42
Sweden         -FairLight-   alt:   +46(0)10 - 22 10 543
--------------------------------------------------------
Article: 6059
Subject: Re: Vendors (Xilinx, Cypress) leaving antifuse market
From: Rhondalee Rohleder <104126.311@CompuServe.COM>
Date: 8 Apr 1997 20:55:27 GMT
Links: << >>  << T >>  << A >>
Peter,

you wrote:
>watch the competition continue, and may the best man win. No 
>arguing, no mudslinging, just read the dataquest statistics.

OK, let the numbers speak for themselves.  Your company is No.1 in 
the market, no doubt about it.  But growth rate means something, 
too.  By the way, these are Pace Technologies statistics.

(US$ millions)	'96 FPGA/CPLD	'95 FPGA/CPLD	% change

Xilinx Inc.	$566.1 		$520.3 		 8.8%
Altera Corp.	$467.4 		$368.9 		26.7%
Actel Corp.	$148.8 		$108.4 		37.3%
Vantis/AMD	$109.4 		$94.5 		15.8%
Lattice Semi	$99.3 		$59.4 		67.2%
Lucent Tech	$87.2 		$77.8 		12.1%
QuickLogic	$26.1 		$17.1 		52.6%

Rhondalee Rohleder
Pace Technologies (Scottsdale, AZ)

-- 
R. Rohleder
Pace_Research@compuserve.com
Article: 6060
Subject: bidirectional buses in xilinx 3000 fpgas
From: u9200386@bournemouth.ac.uk
Date: Tue, 08 Apr 1997 15:12:40 -0600
Links: << >>  << T >>  << A >>
i'm trying to implement a bi-directional bus in an xc3020 device which is
attached to the pc data bus. i have successfully written data out on to
the bus using obuf devices, however, how do i model ibufs in my
top-level??

during xnfprep i'am getting serial buffer errors?? can anyone help??? this
is for my final year disseration so it is very important to me..

any help or advice would be much appreicated.. thanks :)

jon worthington
bournemouth university
microelectronics and computing hons.
u9200386@bournemouth.ac.uk

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6061
Subject: About the usage of Altera maxplus2
From: Lee Jae-Hyuck <starry@kumi2.lge.co.kr>
Date: Wed, 09 Apr 1997 08:12:59 +0900
Links: << >>  << T >>  << A >>
Hello! I am using maxplus2 for EPM9560rc304 altera fpga chip. I'd like
to make all non-used pins into
high impedence state, but I cannot find any options in maxplus2. My
maxplus2 version is 7.0.
plesase tell me. thanks in advance.
Article: 6062
Subject: test
From: Mike Romine <mromine@inetworld.net>
Date: Tue, 08 Apr 1997 16:42:16 -0700
Links: << >>  << T >>  << A >>
test
Article: 6063
Subject: About the usage of maxplus2
From: Lee Jae-Hyuck <starry@kumi2.lge.co.kr>
Date: Wed, 09 Apr 1997 08:51:08 +0900
Links: << >>  << T >>  << A >>
Hello! I am using maxplus2 version 7.0 for EPM9560RC304 altera chip.
I'd like to make all non-used pins into high-impedance state, but
I can't find the option for it in maxplus2. Please tell me about it,
thanks in advance.
Article: 6064
Subject: PCI and DRAM control - Xilinx 4000 -Verilog
From: tech100@mindspring.com (TM)
Date: Wed, 09 Apr 1997 00:35:31 GMT
Links: << >>  << T >>  << A >>
Hello folks,
We are looking for a way to quickly implement a DRAM controller
(32-128MB) and a PCI interface in a Xilinx 4000 part.  Anyone know of
some Verilog code or guidlines for implementing these?

Thanks !

Tom McElroy
tech100@mindspring.com
fax 770 664 5135
Article: 6065
Subject: Re: bidirectional buses in xilinx 3000 fpgas
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 9 Apr 1997 02:34:56 GMT
Links: << >>  << T >>  << A >>

Start with an IPAD, the outside world.

Connect to it the output of an OBUFT or OFDT, your way out of the chip.
Connect to the IPAD the input of an IBUF, or the D of an IFD, or both
  (both is for demuxing addr and data of a muxed external bus)

If you need an internal bidirectional bus, connect the output of the IBUF
or IFD to the input of a BUFT. The output of the BUFT is your internal
bidirectional bus. Connect this bus to the input of the OBUF or OFDT to take
the data from the internal buss and put it on the external pins.

If inputing to the FPGA, the OBUFT or OFDT must not be enabled. You will need
to enable the BUFT that takes the external data and places it on the 
internal bus.

If outputting from an internal bus to the ouside world, enable the BUFT 
that puts the data from its source onto the internal bus (NOT the above 
mentioned BUFT that is used to bring data in), and enable the OBUFT or OFDT.

Enjoy.
Philip Freidin.



In article <860529930.11035@dejanews.com> u9200386@bournemouth.ac.uk writes:
>i'm trying to implement a bi-directional bus in an xc3020 device which is
>attached to the pc data bus. i have successfully written data out on to
>the bus using obuf devices, however, how do i model ibufs in my
>top-level??
>
>during xnfprep i'am getting serial buffer errors?? can anyone help??? this
>is for my final year disseration so it is very important to me..
>
>any help or advice would be much appreicated.. thanks :)
>
>jon worthington
>bournemouth university
>microelectronics and computing hons.
>u9200386@bournemouth.ac.uk
>
>-------------------==== Posted via Deja News ====-----------------------
>      http://www.dejanews.com/     Search, Read, Post to Usenet


Article: 6066
Subject: Re: Chip Temperature (was:Re: Sole source)
From: Gareth Baron <gareth@trsys.demon.co.uk>
Date: Wed, 9 Apr 1997 12:24:13 +0100
Links: << >>  << T >>  << A >>
In article <334a60dc.63614042@cnn.exu>, "Jason T. Wright" <Jason.Wright@
ebu.ericsson.com> writes
>On Mon, 07 Apr 1997 14:37:49 -0400, Martin d'Anjou <mdanjou@nortel.ca>
>wrote:
>
>>Peter Alfke wrote:
>>
>>> Saliva is mostly water and therefore boils ans sizzles at 100 degrees C. (
>>
>>Saliva contains some minerals too (NaCl), which lower the temperature
>>at which the water boils by a few degrees (that's also how you can get
>>boiling water below 100 C - just add salt).
>
>It's been a while since I took chemistry, but if my memory serves me
>correctly, adding salt (and other things) raises the boiling
>temperature ...

Correct.

                Melting point         Boiling point

Sea Water               -9 C            ~104 C
H2O                     0  C             100 C

I guess that when someone told me Saliva had a boiling point of 80 C, I
trusted them.  I guess that Saliva is in between the two figures above.
BTW they are from the SI databook.

So now we have some real figures!

Regards,

Gareth Baron

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%                                               %
%       Morphesys Ltd.  Tel: +44 (0)802 754 512 %
%                                               %
%       EMail:    Gareth@trsys.demon.co.uk      %
%                                               %
%       http://www.trsys.demon.co/              %
%                                               %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Article: 6067
Subject: Re: Pentium Pro Worth it for Altera Max Plus?
From: Dave Grace <dgwing@xilinx.com>
Date: Wed, 09 Apr 1997 07:52:00 -0400
Links: << >>  << T >>  << A >>
That is good data!

What about device performance?

It is one thing to place & route a design quickly that only needs to run
at 10 MHz. What about 40 or 50 MHz? Are you putting any timing
constraints on the design. Marketing from both Altera and anybody else
will tell you that the P&R tools are fast, but how "really" how fast are
they when they are constrained with timing!

I am sure that all of us are curious!

DG
-- 

/ 7\7 Dave Grace     Sr. Field Applications Engineer
\ \   Xilinx Inc.       email: dave.grace@xilinx.com
/ /   6010-C Six Forks Road       Tel: (919)846-3922
\_\/\ Raleigh, NC  27609          FAX: (919)846-8316
Article: 6068
Subject: Re: PCI and DRAM control - Xilinx 4000 -Verilog
From: "Austin Franklin" <#darkroom@ix.netcom.com#>
Date: 9 Apr 1997 13:49:50 GMT
Links: << >>  << T >>  << A >>
Tom,

> We are looking for a way to quickly implement a DRAM controller
> (32-128MB) and a PCI interface in a Xilinx 4000 part.  Anyone know of
> some Verilog code or guidlines for implementing these?

The four words quickly PCI Xilinx and Verilog don't go well in the same
paragraph.

PCI runs at 33MHz (max spec.) and in an FPGA that takes a lot of placement
and logic mapping.  I would be surprised if any of the available Verilog
compilers would be able to make the timing.  And if you're going to have to
screw around with the tools to get it to work right, you may as well take a
known path and use schematic to do this job, at least I can guarantee you
it can be done...

Austin Franklin
..darkroom@ix.netcom.com.

Article: 6069
Subject: comp.arch.fpga archiv dead?
From: Markus.Wannemacher@FernUni-Hagen.De (Markus Wannemacher)
Date: 9 Apr 1997 16:23:00 GMT
Links: << >>  << T >>  << A >>
It seams, that the comp.arch.fpga archiv at
  
  http://www.super.org:8000/FPGA/

has stopped recording new articles in August 1996.

Does anyone know if there are any plans to
bring the archiv back to live?

Are there any other archives of this newsgroup?

Markus Wannemacher

Article: 6070
Subject: Re: Chip Temperature (was:Re: Sole source)
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 9 Apr 1997 16:34:41 GMT
Links: << >>  << T >>  << A >>
Any impurity added to water increases the boiling point and decreases the
freezing point.  This is one of the reasons that you add anti-freeze to
your car's radiator.
-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Jason T. Wright <Jason.Wright@ebu.ericsson.com> wrote in article
<334a60dc.63614042@cnn.exu>...
| On Mon, 07 Apr 1997 14:37:49 -0400, Martin d'Anjou <mdanjou@nortel.ca>
| wrote:
| 
| >Peter Alfke wrote:
| >
| >> Saliva is mostly water and therefore boils ans sizzles at 100 degrees
C. (
| >
| >Saliva contains some minerals too (NaCl), which lower the temperature
| >at which the water boils by a few degrees (that's also how you can get
| >boiling water below 100 C - just add salt).
| 
| It's been a while since I took chemistry, but if my memory serves me
| correctly, adding salt (and other things) raises the boiling
| temperature ...
| 
| I did a search on yahoo that came up with the same answer:
|       http://www.hcrhs.hunterdon.k12.nj.us/science/salt.html
| 
| >
| >My $0.02 CAN
| >Martin.
| >-- 
| >| Martin d'Anjou                  | tel: (613) 765-3058               |
| >| Nortel                          | fax: (613) 763-9535               |
| >| P.O. Box 3511, Station C        | email: mdanjou@nortel.ca          |
| >| Ottawa, Ontario, CANADA  K1Y 4H7| My opinions, not Nortel's         |
| >| http://www.nortel.com/          | Mes opinions, pas celles de Nortel|
| 
| 
Article: 6071
Subject: Cisco's SIBU is looking for ASIC and Systems Engineers
From: lshevock@diablo.cisco.com (CISCO SYSTEMS)
Date: 9 Apr 1997 17:15:05 GMT
Links: << >>  << T >>  << A >>
I am with Human Resources for the Small Internetworks Business Unit
(formerly Grand Junction) at Cisco Systems.  We develop switches, routers,
and hubs that focus on small and medium-sized companies.  Revenue-wise we
are the fastest growing Business Unit at Cisco Systems with 30+% growth
over the last five quarters.  

We are currently looking for senior and intermediate ASIC Engineers
(digital) as well as senior and intermediate Systems Engineers (embedded
CPU, FPGA) to join our team.  We are located in San Jose, California.

If you, or anyone you know is interested, please contact me or send me
your resume.  I will be happy to talk with you further about the
positions.

To send your resume:
fax:  408-527-3831 or
email:  lshevock@cisco.com
No agencies please

-- 
To send your resume:
fax:  527-0180 or
email:  lshevock@cisco.com
No agencies please
Article: 6072
Subject: Re: About the usage of maxplus2
From: Woody Johnson <woodyj@maroon.tc.umn.edu>
Date: Wed, 09 Apr 1997 16:32:38 -0500
Links: << >>  << T >>  << A >>
Lee Jae-Hyuck wrote:

> Hello! I am using maxplus2 version 7.0 for EPM9560RC304 altera chip.
>
> I'd like to make all non-used pins into high-impedance state, but
> I can't find the option for it in maxplus2. Please tell me about it,
>
> thanks in advance.

  The unused _I/O_ pins will be, by defualt, made into outputs so that
you
won't need to tie them to a valid logic level externally.  I'm guessing
that
that is what you actually wanted.

If you truly do want to place them in high impedance, it can be done in
two different ways.  1)  Reserve the pin(s) as unused inputs.  2) Make
the pins outputs and "drive" them with a TRI that has the enable pin
tied low.
Either way you should tie those pins externally to a valid logic level.

You could "automatically" do this to all pins this way (assuming you
want
to go with method 1), above, though the same process could be used for
2)).  Assume after compiling, you have 80 unused I/O's (or I/O's and
dedicated inputs, whatever your need).  Create a new input called
UNUSED[79..0], that'll do it.

WoodyJ

Article: 6073
Subject: Re: prep benchmarks for FPGAs
From: peter@xilinx.com (Peter Alfke)
Date: Wed, 09 Apr 1997 18:20:21 -0700
Links: << >>  << T >>  << A >>
In article <MPG.db43e57e1c4f2b5989810@nntp.aracnet.com>, eteam@aracnet.com
(bob elkind) wrote:

> I'm doing some comparison shopping/measuring for various
> FPGA products vs. synthesis tools.  I'm looking for
> information along the lines of:
> 
> Xilinx XC9885     28 instances of Prep#1 with Synario v9.99
> Altera Flex 2940  39 instances of Prep#1 with Synario v9.99
> Lucent Orca 4c99  32 instances of Prep#1 with Synario v9.99


Please, Bob, let the old PREP lie where they belong, 6 feet underground.
These tiny benchmarks ( because they had to fit into tiny CPLDs ) with
their unrealistic concatenation tell you nothing that you could not figure
out on the back of an envelope. Who cares how many 16-bit counters, each
only connected to its neighbor you can put into an XC4036EX. (The answer
is 162, since each takes 8 CLBs, and there are 1296 CLBs available. And 36
of them are slower, because they have to be broken up.) Who would put 162
counters into an FPGA? 
But, really, who cares? Those benchmarks ar contrived and unrealistic and
completely ignore the routing issues.
Try more meaningful designs with real routing, and always beware of the
Marketing Spin. No marketing department will accept anything but the top
position. So everybody claimed to be the winner. The dirty tricks used in
the original PREP benchmarks could make a grown man cry, ( or throw up ). 

They definitely destroyed any respect I might still have had for the
technical integrity of Marketing on Orchard Parkway.

Peter Alfke, speaking for himself.

.
Article: 6074
Subject: Re: fpga technologies and Iddq testing
From: peter@xilinx.com (Peter Alfke)
Date: Wed, 09 Apr 1997 18:30:46 -0700
Links: << >>  << T >>  << A >>
In article <01bc4441$0a89d760$6e0db780@Rich>, "Rich K."
<rich.katz@gsfc.nasa.gov> wrote:

> Hi,
> 
> Iddq testing has been shown to be a good technique for detecting faults in
> many types of circuits, including FPGAs.

 If I undersstand you right, you want to measure the difference in
cross-current ( I would not call it leakage current ) between
a) an inverter that is driven with a "full High signal, =Vcc, versus 
b) an inverter where the input signal goes through a pass transistor. 

Without gate pumping, the output of the pass transistor is unavoidably
lower than Vcc, but I think the difference in current through the inverter
or gate will be too tiny to be measurable outside the physics lab. And
with tens of thousands of gates on the same chip, what are you really
measuring ?
Just curious.

Peter Alfke, Xilinx Applications


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