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Messages from 7075

Article: 7075
Subject: Re: Design Protection in FPGAs
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Tue, 29 Jul 1997 15:02:38 GMT
Links: << >>  << T >>  << A >>
In article <33DCD75C.29D3@uqtr.uquebec.ca>,
Sam Falaki  <Falaki@uqtr.uquebec.ca> wrote:
>I have been mostly doing work in "academia".  Now however, I need to
>make a commercial prototype and I'm worried that my design could be
>copied.  Anyone have any suggestions? ...

The first and most important thing you should do is to decide whether it's
worth investing serious effort in protecting your design.  What's in it?
Is there actually a significant innovation in it -- something that would
be patentable, and worth patenting if the patent system wasn't so useless?

Unless you're working in some unusual situation (e.g., the game industry),
a design that requires time and effort but contains nothing new and weird
is simply not going to be worth stealing.  Time spent on major anti-copy
precautions for such a design is wasted, and should be spent on something
productive instead.
-- 
Committees do harm merely by existing.             |       Henry Spencer
                           -- Freeman Dyson        |   henry@zoo.toronto.edu
Article: 7076
Subject: ASIC NRE costs, how are they calculated, which values are typical
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Tue, 29 Jul 1997 17:37:52 +0200
Links: << >>  << T >>  << A >>
Does somebody know, how ASIC-vendors calculate NRE costs?

Which values are typical today for 0.35um/0.25um?

Thank you.


Best regards
Martin


martin.vorbach@scrap.de
Fon +49 721 97243 35
Fax +49 721 97243 28




Article: 7077
Subject: Re: FPGA die photograph
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Tue, 29 Jul 1997 17:40:13 +0200
Links: << >>  << T >>  << A >>


> -----Original Message-----
> From:	sidhu@halcyon.usc.edu (Reetinder P. S. Sidhu)
> [SMTP:sidhu@halcyon.usc.edu]
> Posted At:	Saturday, July 26, 1997 1:01 PM
> Posted To:	fpga
> Conversation:	FPGA die photograph
> Subject:	FPGA die photograph
> 
> Would anyone know where I could get the photo of an FPGA silicon chip?
> I need it for a presentation. Thanks in advance.
> 
> 							Reetinder Sidhu
> 
	[M.Vorbach]  
	Try "Scientific American" issue 6/97 or 7/97, there is an
article about reconfig. computing and a photo of an FPGA die. I believe
itīs a XILINX.


Article: 7078
Subject: Re: Problem simulating 3-state output with M1 and Synopsys
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Tue, 29 Jul 1997 18:51:55 +0200
Links: << >>  << T >>  << A >>
> Dear fellows,
> 
> I'm doing a functional simulation of a 4028EX design that has several
> three-state output lines with vss and the new M1 simprim library.
> The vhdl entity that I'm simulating has been generated by ngd2vhdl
> after design translation. This is the only kind of functional
> simulation that I can do with this design, as it contains several
> RPM macros from .xnf files.
> My impression is that the three-state output buffer is not simulated
> well, as the output lines are always defined as X"????" in vss.
> I also checked that the GTS net was low giving the "assign '0' gts"
> command before running the simulation but this didn't help.
> 
> Has anyone had this problem before ?
> 
> thanks in advance
> 
	[M.Vorbach]  
	I had a similar problem a couple of months before, using VERILOG
and the very buggy FinTronic simulator (distributed by VERIBEST). My
problem was a simulator bug:
	If I designed a bus containing 16 wires and tried to simulate it
I always got XXXX. After I extended the bus to 17 wires , but my stimuli
and port interface used only 16 wires, the simulation result was OK. Not
very satisfying, just a workaround.




Article: 7079
Subject: Quick prototyping? Best solution?
From: davewang@wam.umd.edu.delete.after.edu@Glue.umd.edu (David T. Wang)
Date: 29 Jul 1997 16:57:58 GMT
Links: << >>  << T >>  << A >>
Hi all.  

I am working on a project using Actel 1280 FPGA's.  However, This FPGA 
would eventually be used to control another piece of ASIC, whose 
performance characteristic is not entirely clear to us. (Custom ASIC,
no manufacturer to provide fancy manual, we figure it out)  So We'd 
like to do some prototyping.  Which involve the following set of tasks.

1. provide an init sequence/string to the ASIC.

2. provide a regular alternating set of signals to the ASIC.

3. upon triggering, te ASIC would provide a trigger, the FPGA would 
   stop the alternating set of signals, and go into the third sequence
   of signals to digitize some analog signals, and then serially clock
   out the data. The serial data then has to be converted to paralle,
   and decoded (it's in gray code)

I had though about going ahead and use the Actel to do this, except that
since the exact performance characterisitic of the custom ASIC isn't 
known, we'd like to fiddle with the sequence, and timing of the signals.
And as we all know, the Actel isn't too amiable to being reprogrammed :)
I also thought about using something like GAL's, since I know I can get
basically free tools to program them, and the language isn't too 
terribly difficult to pick up.  However, GAL's are too small for my purpose
in this case.  What FPGA/PLD's would be best for my purpose of generating 
about 14 control signals, probably requiring about 50 to 100 FF's for latching
in various signals, and generate the control state machine.  It should be 
easily reprogrammable, and the programming language should be simple to pick 
up. (I do know VHDL). The programming software should be inexpensive.
(prefer free), and I need to develope this piece of hardware in a giffy.
Experience with Altera? 

BTW, the target speed of the system is 4 to 8 MHz, but we'd like to push to 
16 MHz, and see what the performance is like.

Your input is greatly appreciated.


Article: 7080
Subject: Re: PCI burst transfers
From: nin@wam.umd.edu (Hydrochloric Asad)
Date: 29 Jul 1997 15:04:56 -0400
Links: << >>  << T >>  << A >>
In article <33dd49ff.55145054@news.netcomuk.co.uk>,
Peter <z80@dserve.com> wrote:
>
>>  Either way all FPGAs suck tremendously in performance and per unit cost
>>  compared to gate array or standard cell ASIC implementation.  I redid a
>>  8000 gate FPGA built in a 0.6 um process with a 10,000 gate gate array (I
>>  added a few extra functions) in a nearly obsolete two metal 1.0 um process.
>>  The FPGA only ran at about 2/3 of the maximum target clock frequency, the
>>  gate array twice as fast as needed.  The gate array was about 25% the cost
>>  (for a relatively low volume video capture and processing VME card) of the
>>  FPGA and the gate array NRE plus my time was paid for after selling less
>>  than a 100 units.  (This didn't even include the cost of maintaining the
>>  FPGA fuse files and programming parts on the production floor).
>>
>>  A good compromise is if you can design system ASIC(s) to be drop in compatible
>>  with an existing FPGA.  The system can be brought up earlier with the FPGA and
>>  lab testing and evaluation can provide valuable input to the final ASIC design
>>  (and even reduced capability early beta units to customers).  Sometimes some FPGA
>>  samples might run fast enough under benign or conditions to run a few systems at
>>  full speed prior to sampling the ASIC.

OK where did you go to fab the parts?  What were the exact mask costs?  

hmm.  i'm interested.

-bobby mozumder.

>
>Well put. No suprise here :)
>
>
>Peter.
>
>Return address is invalid to help stop junk mail.
>E-mail replies to z80@digiserve.com.


Article: 7081
Subject: Re: Quick prototyping? Best solution?
From: Tom Burgess <tburgess@drao.nrc.ca>
Date: Tue, 29 Jul 1997 13:45:54 -0700
Links: << >>  << T >>  << A >>
David T. Wang wrote:
> 
> Hi all.
> 
> I am working on a project using Actel 1280 FPGA's.  However, This FPGA
> would eventually be used to control another piece of ASIC, whose
> performance characteristic is not entirely clear to us. (Custom ASIC,
> no manufacturer to provide fancy manual, we figure it out)  So We'd
> like to do some prototyping.  Which involve the following set of
> tasks.
> 
> 1. provide an init sequence/string to the ASIC.
> 
> 2. provide a regular alternating set of signals to the ASIC.
> 
> 3. upon triggering, te ASIC would provide a trigger, the FPGA would
>    stop the alternating set of signals, and go into the third sequence
>    of signals to digitize some analog signals, and then serially clock
>    out the data. The serial data then has to be converted to paralle,
>    and decoded (it's in gray code)
> 

An approach I have seen used for flexible CCD imager control is to
keep the control logic relatively simple and to use a downloadable
RAM as a high speed arbitrary pattern generator. That way you can
just edit the pattern to change the timing and don't need to recompile
a bunch of logic every time. Don't recall the reference, but could look
it up if you want.

	regards, tom (tburgess@drao.nrc.ca)
Article: 7082
Subject: Re: Design Protection in FPGAs
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Wed, 30 Jul 1997 01:32:41 GMT
Links: << >>  << T >>  << A >>
Sam Falaki <Falaki@uqtr.uquebec.ca> wrote:

>Hi all,

>I have been mostly doing work in "academia".  Now however, I need to
>make a commercial prototype and I'm worried that my design could be
>copied.  Anyone have any suggestions?  For example do one-time
>programmable FPGAs offer more security?  I don't have the money to
>pay expensive lawyers (patent protection, etc).  I would like a quick
>and easy solution if possible however all suggestions are welcome.

In short, FPGA security is pretty good, at least at the design level.
However, at the binary level there is a wide difference.

It's quite hard to read the code out of a one-time programmable
device.  It's much easier to read the bit stream in an SRAM type
device (e.g. Xilinx / Orca).

I think FPGA security is just like any other security...the more time
and energy you put into it, the better it is.  I do a fair about of
reverse engineering for patent infringement investigation, and given
enough time and money, there is no FPGA (or other IC for that matter)
that can't be reverse engineered.

I think the first thing to decide is whether or not you're protecting
the product design or the binary source files.  Sure, knowing the
binary stream in a XILINX FPGA will allow you to reproduce it, but
without knowing the design you would never be able to support the
product.

Another concern is manufacturing.  A lot of companies will blow their
security fuses, but that will leave them without any way of reading a
part for failure analysis.  They end up protecting their product, but
at the expense of poor product quality.


-----------------------------------------------------
Wade D. Peterson         | TEL: 612.722.3815
Consultant to Industry   | FAX: 612.722.5841
3525 E. 27th St. No. 301 |---------- EMAIL ----------
Minneapolis, MN  55406   | peter299@maroon.tc.umn.edu
---------------- Committed to Quality ---------------

Article: 7083
Subject: Re: information on RIPP10
From: "Stephen Smith" <sjsmith@pacbell.net>
Date: 30 Jul 1997 04:57:16 GMT
Links: << >>  << T >>  << A >>
> Mauro Olivieri <olly@dibe.unige.it> wrote in article 
> does anyone have information on the RIPP10 board from Altera?

you can get some information about the RIPP10 board, and our new board the
ARC-PCI, at our web site "http://www.altera.com/html/programs/phd.html" or
call me on 408-544-7666, or e-mail me at sjsmith@altera.com for more
information.

Regards,
Stephen

Article: 7084
Subject: Re: Should Xiling have more local clock nets?
From: z80@dserve.com (Peter)
Date: Wed, 30 Jul 1997 06:33:46 GMT
Links: << >>  << T >>  << A >>

>Either that or make FFs capable of clocking on both edges of a
>clock so that some can run at double speed.

Now THAT is an excellent idea.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 7085
Subject: Re: Should Xiling have more local clock nets?
From: z80@dserve.com (Peter)
Date: Wed, 30 Jul 1997 06:33:48 GMT
Links: << >>  << T >>  << A >>

>>With the older Xilinx devices, one could attach a L attribute to a
>>local clock net (forces it onto a long line), add a SC=1 (skew below
>>1ns) attribute, and that would do it. This was with the old (1991) APR
>>program. With the new devices (and using PPR) this doesn't work.
>
>How deeply disappointing. Will M1 fix this?

I didn't think it was a s/w problem. I think it is a property of the
newer (faster) devices. It looks like the clock-Q delay is now so much
shorter than the mux propagation delays, that using the normal FPGA
interconnect methods for clock distribution is almost impossible, if
driving any closely-coupled structure like a shift reg or a counter.

But you got me thinking. It is *possible* that XACT6/PPR (which is the
"best" I have, and all I can afford) does have a bug which causes it
to sometimes not notice a situation where multiple D-types are clocked
from the same (non-global) clock net, and maybe it routes the clock to
just one of them halfway around the die. And maybe APR didn't have
this problem. 

When I was doing an ASIC recently, I had a fair number of gated clocks
in the design, and I found that with APR everything worked perfectly -
through perhaps a hundred compilations. (This was a BIG design).

Then, the gate count went up (due to new "customer input") and APR
could no longer pack it into the 3090 for which my prototype PCB was
designed. So I got XACT6/PPR, and sure enough that packed the gates in
more easily, but about 1 compilation in 3 I found that some specific
features (e.g. a 40-bit counter which I used to implement a simple
RTC) didn't work. Specifically, parts of it clocked OK, but the carry
didn't propagate correctly to the rest of the stages. This is
indicative of an excessive delay in the clock input to one of the
D-types. If there was a *general* problem with mux delays, then I
would have expected that counter to almost never work at all. APR
never did this.

I was never able to go back to APR, partly because it never occured to
me then that this might be an APR/PPR issue, and partly because APR
would not have routed the enlarged design.

I now also note that when I do a new build (using the newest devices,
e.g. a fast 3064A) of a product originally done with APR (and
originally using the slowest/cheapest 3064 available) and never
re-routed, I *never* have problems. I have a number of such products,
done mainly in 1992/93, all making use of the fact that a 3064A is a
bitstream-superset of the 3064.

I have always tried to avoid hand layout, having seen it in Xilinx
seminars, done by sales people who do the same "it's easy -see" demo
all day long. I don't do FPGA design full-time, and even a few-months'
gap is enough to forget the subtleties of the various tools. Schematic
entry is much faster to get in/out of, especially if one has another
schematic as a guide.



Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 7086
Subject: Where is Actel's www?
From: sol@elvis.ru (Alexandr Solovkin)
Date: 30 Jul 1997 09:39:06 GMT
Links: << >>  << T >>  << A >>

Hi, FPGA - mans.
I confused I can't to reach Actel www site with
URL: http://www.actel.com.
Who knows Is it problems of my ISP or Actel
changes www site?

Alex.
ELVIS + Ltd.


Article: 7087
Subject: Re: PCI burst transfers
From: "Austin Franklin" <dark4room@ix.netcom.com>
Date: 30 Jul 1997 12:04:30 GMT
Links: << >>  << T >>  << A >>
>   I redid a 8000 gate FPGA built in a 0.6 um process with a 10,000 gate
gate array (I
>   added a few extra functions) in a nearly obsolete two metal 1.0 um
process.
>   The gate array was about 25% the cost...
>   ... and the gate array NRE plus my time was paid for after selling less
>   than a 100 units.

A Xilinx 4010 cost is about $70, and your ASIC was %25 or $17.50 (which is
about the right price, may be even a little high, for a 10k ASIC in 1um). 
Therefore savings were $5250 with these numbers.  At $75/hour for
engineering time, that is 70 hours.  Say it took you 20 hours for your time
(which would be quite a low estimate), leaving $3750 for NRE.  Also, most
ASIC houses won't make an ASIC without a minimum number P.O., say a few
thousand...

My experience has shows your NRE to be quite low for a 10k ASIC, unless you
made up the low NRE by ordering a larger quantity of chips, therefore
including part of the NRE in the chip price, instead of up front.

If you could post your actual numbers (actual NRE, minimum number of chips
you had to order, and at what price, how many hours it took for you to do
this 'conversion') this would make your numbers more 'compelling'.

Thanks,

Austin Franklin
darkroom@ix.netcom.com



Article: 7088
Subject: Re: Where is Actel's www?
From: "Adam J. Elbirt" <aelbirt@viewlogic.com>
Date: Wed, 30 Jul 1997 09:01:22 -0400
Links: << >>  << T >>  << A >>
Alexandr Solovkin wrote:
> 
> Hi, FPGA - mans.
> I confused I can't to reach Actel www site with
> URL: http://www.actel.com
> Who knows Is it problems of my ISP or Actel
> changes www site?
> 
> Alex.
> ELVIS + Ltd.

I tried it today and it works.

Adam
Article: 7089
Subject: Re: Quick prototyping? Best solution?
From: John Chambers <johnc@ihr.mrc.ac.uk>
Date: Wed, 30 Jul 1997 16:18:42 +0100
Links: << >>  << T >>  << A >>
Try the Lattice range.  They do a free starter kit that will program the
1016 and 2032 parts via the printer port.  They can be reprogrammed
10000 times.  The only snag is that you'll have to make your own
download cable (free circuit diagram on the CD ROM consisting of 1 CMOS
buffer).  The complexity of the 1016 is 2000 PLD gates and has 32 IO
pins.  Also the entry is either ABEL or Schematic capture.  The CD ROM
contains the manuals for the Lattice parts and the Synario system.

John
Article: 7090
Subject: Re: VHDL Synthesis in Xilinx Foundation Series
From: "A.C.Rochat" <arjan.rochat@pi.net>
Date: Wed, 30 Jul 1997 19:34:41 +0200
Links: << >>  << T >>  << A >>
Richard Schwarz wrote:
> 
> George Noten wrote:
> 
> > A.C.Rochat (arjan.rochat@pi.net) wrote:
> > : If you are planning to use version 2.2 or earlier, forget it.
> >
> > : The Foundation package contains software by Xilinx and Aldec.
> >
> > : The Aldec part (VHDL, Schematic capture, simulation) has a very
> > fancy
> > : GUI and fancy functionality, but it simply does not work.
> >
> > : The Aldec software performed so bad that we decided to halt the
> > project
> > : altogether.
> >
> > : Now, a jear later i am planning to take the project up again, if
> > there
> > : is goed software
> > : available and Xilinx is willing to give it to mee free. (Yes _FREE_!
> >
> > : Xilinx owes me one!)
> >
> > : Positive notes:
> > : The software written by Xilinx themselves is OK.
> > : The support from the Xilinx distributor here in Holland is realy
> > : exelent!!
> >
> > This reminds me very much of my own experience with Viewlogic
> > PROseries.
> > The only good part of it was the beta-test version of Speedwave
> > simulator.
> > The synthesis just did not work.  Now I know that PRO-/View- synthesis
> >
> > tools are not to be trusted.  You are telling me that neither is
> > Aldec.
> > Can anybody recommend something that is good enough and does not cost
> > you your life savings?  What about the new VHDL synthesis tool from
> > MINC?
> >
> >         George.
> 
> I have used the Foundation Tools from XILINX and they indeed do work.

Realy?
What about the Aldec project manager that changes your project name into
something you don't want? - Unable to change it back?
Or what about moving a symbol in Aldec schematic capture, so the entire
net is messed up 
and all net nodes are are placed at the same point, so the only thing
you can do is delete the net and redraw it?
Or wat about using the Aldec simulator that doesn't simulate the circuit
as designed, so 
you spend half a day to find bugs that aren't there?
Or what about writing some stuff in VHDL - syntax O.K. but the compiler
doesn't swallow it?
Article: 7091
Subject: Re: Design Protection in FPGAs
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Wed, 30 Jul 1997 21:21:44 GMT
Links: << >>  << T >>  << A >>
fliptron@netcom.com (Philip Freidin) wrote:

>   The same also applies to trying to reverse
>   engineer an SRAM FPGA bitstream. To my knowledge, this has only been
>   done successfully once, by a very motivated company, and the intent was
>   not to ripoff an end user's design, but rather to create competitive
>   CAE software.

I've never tried it, but I would think it would be fairly easy to
break SRAM code.  XILINX and guys like that claim that it's
impossible, but if you think about it, it should be that hard.

For example, if you took some design tools for a XC400X device, and
(a) programmed only one interconnect at a time and (b) looked at the
resulting bitstream, I think you should be able to break their code.
This could be repeated until a total picture of the bitstream results.
Furthermore, there's probably pattern to the bit patterns.  I would
think you should be able to find the pattern in a few days of work.


>4) The highest security is with SRAM FPGAs that have a power-down/battery
>   backed up mode of operation (such as the XC3000L products). With these
>   devices, the bitstream is loaded into the device during manufacturing,
>   and a battery maintains the configuration data in the device, even when
>   the system is turned off. Unless you want to have a big battery, you
>   need an FPGA that can maintain its data in a power down mode with very
>   little power. The XC3000L parts can do this as low as 5uA, which is
>   down at the battery's own leakage current, and with appropriate
>   batteries, could give an operation life of 5 to 10 years.

I don't really care for this from a manufacturing standpoint.  Any
glitch (caused by a fat probe, etc.) on the power rail would render
the product useless, as the FPGA would forget it's program and
couldn't be reset in the field.


-----------------------------------------------------
Wade D. Peterson         | TEL: 612.722.3815
Consultant to Industry   | FAX: 612.722.5841
3525 E. 27th St. No. 301 |---------- EMAIL ----------
Minneapolis, MN  55406   | peter299@maroon.tc.umn.edu
---------------- Committed to Quality ---------------

Article: 7092
Subject: Contact Lenses for Internet users
From: Contact Lenses <lyuks@easyway.net>
Date: Wed, 30 Jul 1997 19:39:56 -0400
Links: << >>  << T >>  << A >>
Contact Lenses for Internet users
http://www.lyuks.com/lenses.html
Thanks

Article: 7093
Subject: digitizer design, high speed
From: "Richard B. Katz" <stellere@erols.com>
Date: 31 Jul 1997 02:37:30 GMT
Links: << >>  << T >>  << A >>
hi,

as part of a space flight instrument, a high speed digitizer is required. 
here's a brief specification.

	1. sample rate >= 1 gigasample/second, 8-bit resolution; > 1.6
Gigasample/second desired.
	2. input bandwith >= 250 MHz
	3. memory depth >= 32,000 samples; > 64,000 samples desired.
	4. 100 MHz clock input, PLL to increase speed as needed
	5. 80 Hz rate.
	6. power <= 25 watts.
	7. prefer mcm packaging
	8. design life >= 8 years, 5 years on-orbit.

we welcome any ideas that you may have.  also, if you have experience in
this area, like a good challenge, and would like to be considered for this
assignment, please contact me (info at the bottom).

one concept we're exploring is to use, for example, the 1 GSample/second
SPT ADC and RAMBUS DRAMS.  This can give us a huge memory (and cheap
redundancy) and is a bonus for the system design.  for this, obviously, we
would like a high-speed asic to provide the connection between the ADC (500
MHz w/ the 1:2 on-chip demux) and the RDRAMs for acquisition and system
logic for readout (which is relatively slow).  spt adc and RDRAMS have
already passed preliminary radiation tests and are currently undergoing
construction analysis.

other concepts are being explored and feel free to come with a clean sheet
of paper.

you may contact me at:

	Rich Katz
	NASA/GSFC
	Code 738
	Greenbelt, MD 20771

	Tel: 	(301) 286-9705
	Fax:	(301) 286-0220
	email: 	rich.katz@gsfc.nasa.gov
Article: 7094
Subject: Re: Simulating large VHDL design (FPGA backannotated)
From: berndt@eas.iis.fhg.de (Thomas Berndt)
Date: 31 Jul 1997 04:35:56 GMT
Links: << >>  << T >>  << A >>
Georg Diebel <g_diebel@lis.e-technik.tu-muenchen.de> writes:

> Hi everybody,
Hi too,

> Now the Problem:
> 
> I have a VHDL design targeted for a Altera FLEX FPGA (10K50).
So far so good.

> When I try to simulate these designs (Synopsys VSS), first everything 
> looks good, but when I try to set a trace (view a waveform), the
> simulator gets to work (on what I don't know) and won't stop and
> won't react to anything (at least for the 4 hours I had the patience
> to wait).
What do think about Hardware/Software-Cosimulation. The partitioning
your design to components for simulation at all and components for
emulation at a prototyping board coupled to a HDL-Simulator is up to you.
The sight to the emulator partition is as a HDL entity.
But now, you can achive a significant speed up depend on the design.

> OK, then I figured that this VHDL design simply was too large for
> the *interpreted* VHDL-simulator from Synopsys and hence tried to
> analyze the VHDL for the "compiled" mode. This took about 3 hours
> (yes, only analyze & compile) before the job ran out of memory and
> aborted. Oh, I was running it on a UltraSparc with 600 MB physical
> memory and about 1.2 Gig of swap space ... wouldn't know where to
> find a bigger machine here at the institute.
Our HW/SW-Cosimulation environment supports also the VSS from Synopsys.

> Now, what to do?
Have a look at http://www.eas.iis.fhg.de/sim/projects/dfg/welcome_de.html
 
> Looking forward to any ideas!
Hope this helps.

Yours,

Thomas

 ______________________________________________________________________________
|                                                                    	       |
| Dipl.-Ing. Thomas Berndt   	Tel: 0351 / 4640-731           		       |
|                             email: berndt@eas.iis.fhg.de		       |
|				URL: http://www.eas.iis.fhg.de/sim/staff/berndt|
|        			FAX: 0351 / 4640-703        	               |
|                                                                              |
| Fraunhofer-Institut fuer Integrierte Schaltungen (IIS)                       |
| EAS Dresden                                                                  |
| Zeunerstr. 38                                                                |
| 01069 Dresden                                                                |
|______________________________________________________________________________|



Article: 7095
Subject: Re: Problem simulating 3-state output with M1 and Synopsys
From: berndt@eas.iis.fhg.de (Thomas Berndt)
Date: 31 Jul 1997 04:48:58 GMT
Links: << >>  << T >>  << A >>
Arrigo Benedetti <arrigo@vision.caltech.edu> writes:
> Dear fellows,
> 
> I'm doing a functional simulation of a 4028EX design that has several
> three-state output lines with vss and the new M1 simprim library.
> The vhdl entity that I'm simulating has been generated by ngd2vhdl
> after design translation. This is the only kind of functional
> simulation that I can do with this design, as it contains several
> RPM macros from .xnf files.
> My impression is that the three-state output buffer is not simulated
> well, as the output lines are always defined as X"????" in vss.
> I also checked that the GTS net was low giving the "assign '0' gts"
> command before running the simulation but this didn't help.
> 
> Has anyone had this problem before ?
Yes, I do. At the first gate the input std_logic value 'Z' moves to 'X'. So
you can drive the pin with static 'L' or 'H'.
In this way, 'Z' moves to 'L' or 'H', but '0' or '1' don't changes.

> thanks in advance
Hope this helps.

Thomas

 ______________________________________________________________________________
|                                                                    	       |
| Dipl.-Ing. Thomas Berndt   	Tel: 0351 / 4640-731           		       |
|                             email: berndt@eas.iis.fhg.de		       |
|				URL: http://www.eas.iis.fhg.de/sim/staff/berndt|
|        			FAX: 0351 / 4640-703        	               |
|                                                                              |
| Fraunhofer-Institut fuer Integrierte Schaltungen (IIS)                       |
| EAS Dresden                                                                  |
| Zeunerstr. 38                                                                |
| 01069 Dresden                                                                |
|______________________________________________________________________________|


Article: 7096
Subject: Make extra cash..it works.
From: Dan <danthompson@hotmail.com>
Date: Wed, 30 Jul 1997 22:08:13 -0700
Links: << >>  << T >>  << A >>
MAKE A FORTUNE - AND THIS IS THE ABSOLUTE TRUTH!

IF YOU HAVE READ THIS FAR YOU HAVE ALREADY PROVED IT WORKS!!

TAKE JUST 5 MINUTES TO READ THIS AND SEE.


This is the newest updated version.
As I was surfing the net, I read all these postings on how you can
make over $50,000, even $800,000.  Well I believe that if all goes
well, and you follow the rules EXACTLY, it will work. Just follow the
instructions given in this letter, and you to can make over $800,000,
perfectly legally according to USA Post Office Laws (read on for
specifics).
Don't look at this as a  scam, but rather a true-to-life
example to test the above statement. It will only cost you $6 dollars
plus 6 stamps, and a few hours of your time. Thus, there is some
effort involved, because nothing in life is absolutely free. Are you
ready and willing to accept that you deserve to receive a fair amount
of ? If so, please continue reading. But if you think this is
just another scam, I suggest that you don't try it.

PLEASE NOTE: THIS IS A 6-PERSON LIST, NOT THE USUAL 5.
PLEASE DO NOT TRY TO CHEAT THIS PROGRAM. JUST ADD ONE NAME AND
REPOST THE ARTICLE.  IF YOU DO NOT IT WILL NOT WORK, AND YOU WILL BE
REMOVED
FROM THE LIST! FOLLOW THESE DIRECTIONS AND JOIN US IN A GREAT
OPPORTUNITY!

The program has been revised and you will notice six names instead of
five.
The reason for this is the flood of five name programs and the sixth
name will add $50000 to $100000. This is proven mathematically and in
my bank account. I never really thought that this program would work,
but IT DOES and it will for you too. Just be patient and follow the
directions exactly.

Print this article now, so you have all the information for your
 version.
Remember to keep the names right. Let's go!

STEP 1

Invest your $6 by writing your name and address on six separate pieces
of paper along with the words:

"PLEASE ADD ME TO YOUR MAILING LIST".

(In this way, you are not just sending a dollar to someone; you are
paying for a legitimate service.)
People have asked me if this is really legal.  It is! You are using
the Internet to advertise your business.  What is that business?  You
are assembling a mailing list of people who are interested in home
based computer and on-line businesses and methods of generating income
at home.
Remember - people send you a small fee to be added to your list. It is
legal. What will you do with your list of thousands of names?  That's
up to you, but this is how it becomes legal. To be legal you must
actually sell a product or service if you expect to receive a dollar.
Anyone sending a dollar back to you must receive something in return.
You have already received this letter due to the participation of each
of the 6 persons listed below. This letter and the plan given within
this letter are a "product" that you have received. Thus, you will be
sending $1.00 to each of the 6 persons given below in exchange for
receiving this letter and for asking them to provide the "service" of
adding you to their mailing list.
THIS IS A SERVICE AND IS A 100% LEGAL BUSINESS OPPORTUNITY WHICH I
COVERED IN TITLE 18, SECTION 1302 AND 1342 OF THE POSTAL AND LOTTERY
LAWS.
Now, please follow the given steps exactly to receive your desired
amount of :
Immediately send $1 US cash (a one dollar bill, no checks, no
orders) to each of the 6 people on the list below. Wrap this dollar in
a note with the words: "Please put me on your mailing list." (In this
way, you're not just sending a dollar to someone, you're paying for a
legitimate service.)

Also, to discourage those who prey on cash in the mail, be sure the
bill is completely hidden by the note. A woven envelope is
recommended.  Include your address. You do not need to include your
name. This is the key to the program!  Also, let each person know what
number they are in your letter so he/she knows which cycle he is
receiving the $1.00 from. Make sure that you
retain EVERY name and address sent to you, either on computer or hard
copy, but do not discard the names and notes that people send to you.
This is PROOF that you are truly providing a service, and should the
IRS or some other government agency question you, you can provide them
with this proof
Therefore, you will start a list of all the people who send you a
dollar requesting to be added to a mailing list.  Actually, you will
want to safeguard this list because it can generate even better
responses and much more  later!
Fold a $1 bill inside each paper, and mail them by standard mail to
the following six addresses:

1)    Lindsey W.
      736 Shivel Ln.
      Huntington, WV 25705
      USA

2)    Rudolfs Osins
      Aspazijas 37-4
      Jelgava, LV 3001
      Latvia

3)    J. DiMauro
      89 East Squire Dr.  Apt. 1
      Rochester, NY 14623
      USA

4)    D.Brottlund
      1588 Nokomis Dr.
      Colo Spgs, CO 80915-2605
      USA

5)    S. Bhattacharjee
      11008 Hard Rock Road
      Austin, TX 78750-1552
      USA

6)    Daniel Thompson
      492 W. 600 N.
      Spanish Fork, Ut 84660
      USA

STEP 2
Now remove the top name from the list, and move the other names up.
This way #6 becomes #5 and so on. Put your name in as the #6 on the
list (Remember to take #1 off and change the numbers so #2 becomes #1,
#3 becomes #2, #4 becomes #3, #5 becomes #4 and #6 becomes #5 and you
become #6.)


STEP 3
LET ME TELL YOU HOW MUCH  YOU CAN MAKE.
How do the numbers work for potential income earnings?  Assume for the
sake of example that you get a 7.5% return rate.  This is very
conservative; my first attempt was about 9.5%, and my second was over
 11%.

1. You send out 200 letters, and 15 people (7.5% x 200) will send you
$1 each. $15.00

2. Those 15 send out 200 letters each, and 225 people send you $1
each. $225.00

3. Those 225 send out 200 letters each, and 3,375 people send you
$1 each. $3,375.00.

4. Those 3,375 send out 200 letters each, and 50,625.00
people send you $1 each. $50,625.00

5. Those 50,625 send out 200 letters each, and 758,375 people send you

$1 each. $759,375.00

TOTAL $813,615.00!!  If those figures sound incredibly high, figure
that even with half the return rate, or even a quarter, the total is
still spectacular.  It works every time, but how well will depend on
how many letters you send. In the above example you mailed out 200
letters.
This sounds like "pie in the sky," but the numbers add up, and with
over 40 million people on the NET, it works!  TIP:  For an even
greater return, post to MORE than 250 newsgroups initially; try for
300-350.  When your name drops off a list, simply access another
message from a newsgroup and start the process over again.
Post the new article to at least 250 newsgroups. remember, the more
you post, the more people see, and the more you get. There are at
least 25,000 newsgroups at any one time.
This is a $7.92 investment. It takes about a week or so to start
seeing a return- so be patient. The  should flow for about 3
months. At that point, simply add your name to the list and start
over.
I've done this three times and now I can quit my job and start
investing in real estate full time. I assure you this can work.
If you mailed out 500 letters, you could have received even more!
Check the math yourself, but I guarantee it's correct.  With this kind
of return, you have got to give it a try!  Try it once, and you'll do
it again. Just make sure you send a dollar to each of the addresses on
the list above with a note asking to be added to their mailing list.
Together we will all prosper and we will be able to share our wealth
with those less fortunate than ourselves.

GOOD LUCK!!
GENERAL STEPS ON AUTOMATING THE PROCESS
--------------------------------------------------------------------------

If you have Netscape 3.0 do EXACTLY the following:

1)  Click on any newsgroup like normal, THEN click on 'TO NEWS', which
is on the far left when you're in the newsgroups page.  This will
bring up a box to type a message in.
2)  Leave the newsgroup box like it is, CHANGE the subject box to
something flashy, like,..
3)  Tab once and you should be ready to type.  Now, retype (only once)
THIS whole article WORD FOR WORD, except insert your name at #6,  and
remove #1 off the list, plus any other small changes you think you
need to make.
Keep almost all of it the SAME!
4)  When you're done typing the WHOLE article, click on FILE in THIS
BOX, RIGHT ABOVE SEND, NOT WHERE IT SAYS NETSCAPE NEWS ON THE FIRST
 BOX.
Click on SAVE AS when you're under FILE.  Save your article as a text

file to your C: or A: drive.  DO NOT SEND OR POST YOUR ARTICLE UNTIL
YOU DO THIS.  Once saved, move on to number 5 below.
NOTE:  If you don't want to type in the whole article by hand, AND you
know how to use a plain text editor (like Notepad), you can edit the
file ahead of time, then attach it as shown in step 6.
5)  If you still have all of your text, send or post to this newsgroup
now by just clicking send, which is right below FILE, and right above
Cc:
6)  Here's where you're going to post all 200.  OK, click on any
newsgroup then click on 'TO NEWS', again in the top left corner.
Leave the NEWSGROUPS BOX alone again, put a flashy subject title in
the SUBJECT BOX, hit TAB once you're in the body of the message.
Click on ATTACHMENTS, which is below the SUBJECT BOX.  You will get
another box to come up.  Click on ATTACH FILE, then find YOUR file
that if you did this right, you should see your file name in the
attachments box, and it will be shaded green.
NOTE:  If you don't want to type in the whole article and you know how
to use a plain text editor (Notepad), you can edit the file ahead of
time, then attach it.
IF YOU USE I.E. EXPLORER IT'S JUST AS EASY...HOLDING DOWN THE LEFT
MOUSE BUTTON, highlight this article.  Then press the "ctrl" key and
the "c" key at the same time to copy this article.  Then print this
article for your records, to have the names of those you will be
sending $1 bills to.
2)  Go to the news groups and press "post an article".   A window will
open.  Type in your headline in the subject area and then click in the
large window below.  Press "ctrl" and then "v" and the article will be
placed in the window.

If you want to edit the article, do so and then highlight and copy it
again.  Now every time you post the article in a new newsgroup all you
have to repeat is "ctrl" and "v" and press post.
3)  That's it.  Each time you do this, all you have to do is type in a
different newsgroup, so that way it posts to 200 DIFFERENT newsgroups,
or more.

You see?  Now you just have 249 to go!! (Don't worry, each one takes
about 30 seconds, once you get used to it.
REMEMBER 250 IS THE MINIMUM.  But the more you post the more  you
will receive.
AND THAT'S IT!!  THEY ARE ONLY STEPS!!!
--------------------------------------------------------------
(this is a later addition for extra ease of posting)
EXTRA TIPS:-

(ONLY) IF YOU ARE CONFIDENT WITH YOUR COMPUTER YOU CAN AUTOMATE YOUR
POSTINGS (and prevent spamming) AS FOLLOWS: (THIS Replaces the
previous section only i.e. 'GENERAL STEPS ON AUTOMATING THE PROCESS')
(using Netscape):

As you are reading this message click on "file" - "save message as",
enter a filename in the 'save as' dialog box, press "enter".
Now open "Notepad" (usually from "start" - "programs" - "accessories")
and open the message ( "file" - "open" ) you just saved. (You will
find it in the same folder you saved it and you may also find it
has a '.html' file extension). Then edit the letter EXACTLY as you
have been directed above. Just make sure you delete the
'system-message'
that appears at the top so that it makes sense when you read it!
Click on "edit" - "select all" (all the
text should now be highlighted) then again "edit" - "copy".
Leave Notepad alone for now and return to the Netscape News program:
Click on "options" - "show all newsgroups".
Now select (subscribe to) whichever groups you think are suitable by
moving down the entire listing and clicking in the appropriate empty
boxes. Once you have finished click "options" - "show subscribed
newsgroups".
Now simply click on the first group you want to post to, to highlight

it. Then choose the group about 10 further on and WHILE HOLDING DOWN
THE SHIFT KEY click on it. Next click on "file" - "new news message".

A message box will appear and after entering the "flashy" subject
line,
position the cursor in the main message area.
Click on "edit" -"paste"; the message will appear.
NOW CHECK IT!!
When you are satisfied everything is correct click "send" and it will
 be
sent to all 10 groups. Now repeat as many times as you need- very
simple!

PLEASE NEVER post to many more than 10 with any one message since
the resulting long lines of newsgroup listings at the top of EVERY
message will annoy many AND will vastly reduce the effectiveness of
your posting.
JUST ONE OTHER THING:
Let's remember that there are many people far less fortunate than
ourselves who will never be able to afford a computer and hence
will be unable to join in our enterprise. Therefore please consider
donating a (significant) portion of your earnings from the venture
to charity.
NOTE - "edit" - "copy" is exactly the same as pressing "ctrl" with "c"
       "edit" - "paste" is exactly the same as pressing "ctrl" with
 "v"




Article: 7097
Subject: Download FLEX10K over the LPT port
From: berndt@eas.iis.fhg.de (Thomas Berndt)
Date: 31 Jul 1997 05:15:42 GMT
Links: << >>  << T >>  << A >>

Hi,

does anybody knows how I can download designs which are compiled with MAXPLUS2
over the LPT port?

Thanks in forward.

Thomas
 ______________________________________________________________________________
|                                                                    	       |
| Dipl.-Ing. Thomas Berndt   	Tel: 0351 / 4640-731           		       |
|                             email: berndt@eas.iis.fhg.de		       |
|				URL: http://www.eas.iis.fhg.de/sim/staff/berndt|
|        			FAX: 0351 / 4640-703        	               |
|                                                                              |
| Fraunhofer-Institut fuer Integrierte Schaltungen (IIS)                       |
| EAS Dresden                                                                  |
| Zeunerstr. 38                                                                |
| 01069 Dresden                                                                |
|______________________________________________________________________________|


Article: 7098
Subject: Re: Quick prototyping? Best solution?
From: "J. Mejia" <jms56y@aol.com>
Date: 31 Jul 1997 12:27:51 GMT
Links: << >>  << T >>  << A >>

How about GateField. These are reprogramable devices based
in Flash ROM technology. They work just as an FPGA but you
can reprogram them over and over. 

David T. Wang <davewang@wam.umd.edu.delete.after.edu@Glue.umd.edu> wrote in
article <5rl7em$nf7$1@hecate.umd.edu>...


Article: 7099
Subject: Re: VHDL Synthesis in Xilinx Foundation Series
From: Richard Schwarz <aaps@erols.com>
Date: Thu, 31 Jul 1997 09:19:54 -0400
Links: << >>  << T >>  << A >>
A.C.Rochat wrote:

> Richard Schwarz wrote:
> >
> > George Noten wrote:
> >
> > > A.C.Rochat (arjan.rochat@pi.net) wrote:
> > > : If you are planning to use version 2.2 or earlier, forget it.
> > >
> > > : The Foundation package contains software by Xilinx and Aldec.
> > >
> > > : The Aldec part (VHDL, Schematic capture, simulation) has a very
> > > fancy
> > > : GUI and fancy functionality, but it simply does not work.
> > >
> > > : The Aldec software performed so bad that we decided to halt the
> > > project
> > > : altogether.
> > >
> > > : Now, a jear later i am planning to take the project up again, if
>
> > > there
> > > : is goed software
> > > : available and Xilinx is willing to give it to mee free. (Yes
> _FREE_!
> > >
> > > : Xilinx owes me one!)
> > >
> > > : Positive notes:
> > > : The software written by Xilinx themselves is OK.
> > > : The support from the Xilinx distributor here in Holland is realy
>
> > > : exelent!!
> > >
> > > This reminds me very much of my own experience with Viewlogic
> > > PROseries.
> > > The only good part of it was the beta-test version of Speedwave
> > > simulator.
> > > The synthesis just did not work.  Now I know that PRO-/View-
> synthesis
> > >
> > > tools are not to be trusted.  You are telling me that neither is
> > > Aldec.
> > > Can anybody recommend something that is good enough and does not
> cost
> > > you your life savings?  What about the new VHDL synthesis tool
> from
> > > MINC?
> > >
> > >         George.
> >
> > I have used the Foundation Tools from XILINX and they indeed do
> work.
>
> Realy?
> What about the Aldec project manager that changes your project name
> into
> something you don't want? - Unable to change it back?
> Or what about moving a symbol in Aldec schematic capture, so the
> entire
> net is messed up
> and all net nodes are are placed at the same point, so the only thing
> you can do is delete the net and redraw it?
> Or wat about using the Aldec simulator that doesn't simulate the
> circuit
> as designed, so
> you spend half a day to find bugs that aren't there?
> Or what about writing some stuff in VHDL - syntax O.K. but the
> compiler
> doesn't swallow it?

I have not seen any of the problems you described above. I have done
dozens of projects and never had the software change the project name on
me. I typically make more use of the VHDL compiler and have never had
the problems you describe between the syntax checker (which most
compilers don't even have as a separate feature) and compiler. I am
sorry that you have had some difficulties, but there are thousands
(including me) who are using this software successfully. I have used
Exemplar, Synplicity and several other more expensive VHDL compilers and
have not found the XILINX /ALDEC software to be any more or less buggy
or problematic than the other more expensive compilers. Please feel free
in contacting me or XILINX or ALDEC if you run into any future problems.
I wish you  success in your future endeavors.
  --
----------------------------------------------------------------
Richard Schwarz,     President
Associated Professional Systems (APS)
EDA and Communications Tools
http://www.associatedpro.com
richard@associatedpro.com
410.569.5897  fx:410.661.2760




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