Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 6225

Article: 6225
Subject: Interface between WVo731 VHDL and ORCA
From: Ilan Ron <iron@radnet.co.il>
Date: Wed, 30 Apr 1997 06:53:38 +0300
Links: << >>  << T >>  << A >>
I'm experiencing some problems concerning the interface between
Viewlogic's WVO731 VHDL synthesizer and the ORCA foundry software.

To be more precise:
I'm using WVO's EDIF netlist writer in order to convert WIR files into
EDIF format. The motivation for this process derives from the need to
add to level I/O pads automatically. This switch can only be operated in
the ORCA S/W if the input format is in EDIF.

The main problem is that is the Mapping stage the ORCA S/W encounters an
unknown element, named "PW" and skips all the FF's in the design.

A more serious inquiry discovered that this "PW" is some sort of Pulse
width attribute from the VWO BUILTIN library.

It turns out that the EDIF netlist writer translated this object into an
unfamiliar name for the ORCA S/W.

I tried to specify the EDIF writer the level of descending into the
deign elements to be ORCA, thus not reaching any 'PW" elements.
The result was surprising indeed - because the ORCA mapper somehow tried
to add I/o pads to internal nets, and off course, failed.

If any of you have any relevant information about this puzzle please
forward it to me, any tips are gladly welcomed.


Best regards,
               Iron.
Article: 6226
Subject: Re: Low power PLD?
From: murray@pa.dec.com (Hal Murray)
Date: 30 Apr 1997 07:50:12 GMT
Links: << >>  << T >>  << A >>
In article <5k4md7$jgq$1@wnnews.sci.kun.nl>, sloman@sci.kun.nl (Bill Sloman) writes:

> I've got to fit 8 clock extractors/resynchronisers into one or two SMD
...
> But my bigest constraint is that I've only got 50mA for the PLD/PLDs.
...

Anybody seen any metastability data on low power PLDs?

I could easily imagine that whatever the circuit people do
to reduce power also reduces the gain/bandwidth that helps
the settling time.
Article: 6227
Subject: Laptop
From: Ole_Christian_Midtbust@norcontrol.com (Ole Christian Midtbust)
Date: Wed, 30 Apr 97 12:00:55 GMT
Links: << >>  << T >>  << A >>
I'm looking for a laptop with the following spec.: 1024x786 with 256 colour palette (need 1 MB video RAM). The graphic processor 
most be TSENG ET 4000 or ET6000,  the graphic controller bios have to be compatibel with VESA VGA standard 1.2 or higher.
Help....
Article: 6228
Subject: test
From: Mike Romine <mromine@inetworld.net>
Date: Wed, 30 Apr 1997 09:37:30 -0700
Links: << >>  << T >>  << A >>
tst
Article: 6229
Subject: XC6200 plentifully available
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 30 Apr 1997 11:42:17 -0700
Links: << >>  << T >>  << A >>
There was a recent question about XC6216 availability, and it should not
be left unanswered.
Thousands of XC6216 devices in HQ240 and PQ299 packages, and also some
in TQ144 and BG255 are available, ready to ship. Sorry, no PLCCs.
Contact your Xilinx sales rep or distributor.

For an even better deal, look at the development kits from Annapolis
Microsystems ( wfinfo@annapmicro.com )and from Virtual Computer
Corporation (sc@vcc.com). They give you a running start, and they are
not expensive.
Please excuse this crass commercialism. I'll be more technical next
time.

Peter Alfke
Article: 6230
Subject: Anyone done an IEEE488 talker/listener in AHDL for Altera ?
From: Steve@s-dewey.demon.co.uk (Steve Dewey)
Date: Wed, 30 Apr 97 18:50:58 GMT
Links: << >>  << T >>  << A >>
Hi

Has anyone done a basic IEEE488 bus interface in Altera AHDL ?
It can be pretty simple as my application is not very complicated.
I am only interested in Talker/Listener functionality, not a
controller.

P.S. What bus driver chips should I use ?

Cheers

-- 
Steve Dewey
Steve@s-dewey.demon.co.uk
Too boring to have an interesting or witty .sig file.


Article: 6231
Subject: Re: XC52xx and Hardware Debugger
From: stuart.summerville@practel.com.au (Stuart Summerville)
Date: Wed, 30 Apr 1997 19:03:47 GMT
Links: << >>  << T >>  << A >>

>We have never claimed that you can read back combinatorial outputs.
True, with the exception of p4.187 of the XC5200 datasheet (v4.01)
which says that one can "observe internal logic levels...".  This, to
me, is misleading. 

WRT performing readback on anything but CLB's,  the Hardware Debugger
Reference/User Guide claims on page 1-2 that 5200 IOB and CLB outputs
can be probed. This is also incorrect.

This is due to be rectified, according to Xilinx support.

Stu.
---------------------------------------------
Stuart Summerville      
Project Engineer         
Practel International
442 Torrens Road, Kilkenny, SA 5009
Tel: (61.8) 8268 2196  Fax: (61.8) 8268 2882
Email: stuart.summerville@practel.com.au  
---------------------------------------------
Article: 6232
Subject: FPGA chip on Khepera robot
From: ass@daimi.aau.dk (Asger Sporring)
Date: 30 Apr 1997 17:48:13 -0400
Links: << >>  << T >>  << A >>
I'm doing my master thesis on EvolHard, and am going to use the
Khepera robot for some practical testing.

But I need to place a FPGA chip (right now I'm looking into using the
Xilinx chips(like Splash 2), but this is not fixed) on the robot, for
it to be of any use.

Does anybody have any experience with this (using, I assume, the
general IO turret).

--
Asger Sporring            * "I love the smell of napalm in the morning,       *
Spobjergvej 145 l.7+8     *  mhhh it smells like.. victory!", Apocalypse Now! *
8220 Brabrand, DK         & University of Aarhus, office B2.17,   (+45)89423357
ass@daimi.aau.dk, www.daimi.aau.dk/~ass, tlf(/fax when I'm home): (+45)89449501

--
*****   Crossposted with comp.robotics.research (moderated)  *****
  Summary: Academic, government & industry research in robotics.
      Archives and information: http://www.robot.ireq.ca/CRR
         Charter: ftp://ftp.robot.ireq.ca/pub/crr/Charter
      Meta-discussions/information: crr-request@robot.ireq.ca
Article: 6233
Subject: Re: Laptop
From: Satyan Namdhari <satyan@raleigh.ibm.com>
Date: Wed, 30 Apr 1997 21:11:39 -0400
Links: << >>  << T >>  << A >>
Ole Christian Midtbust wrote:
> 
> I'm looking for a laptop with the following spec.: 1024x786 with 256 colour palette (need 1 MB video RAM). The graphic processor
> most be TSENG ET 4000 or ET6000,  the graphic controller bios have to be compatibel with VESA VGA standard 1.2 or higher.
> Help....

Hi Ole,
   IBM has a very good range of Laptop PCs. I suggest you take a look at
http://www.sg.pc.ibm.com.

-- 
Satyan Namdhari                  
Contractor at IBM - Mwave          Phone : (919) 543 - 2057 (Work)
e-mail : namdhari@hotmail.com              (919) 572 - 0919 (Home)
       : satyan@raleigh.ibm.com      FAX : (919) 254 - 6963
       : satyan@usa.net
Article: 6234
Subject: Re: ISP CPLD from AMD or Cypress???
From: Joe Schmo <Joe.Schmo@framenbacher.com>
Date: Wed, 30 Apr 1997 22:23:40 -0400
Links: << >>  << T >>  << A >>
Ed Barrett wrote:
> 
> Look into LAttice ISP devices. They have been shipping ISP for 5 years.
> You can get a free CD for tools. This free tool does not iinclude VHDL
> but you could use ABEL that is supported. You didn't mention your design
> requirements, but Lattice has the most ISP devices, the fastest devices,
> and great support for In System Programming from a PC. Check it out at
> WWW.LATTICESEMI.COM
> 
> Ed

True, Lattice WAS the first company to really "champion" the concept of
ISP.  However, as you probably know, this was a Lattice-proprietary ISP
implementation that remains in their devices today.  However, as ISP has
become more prevalent, the rest of the industry has adopted the use of
the
JTAG Boundary Scan chain to implement ISP functionality.  The main
benefit
of this is the ability to "piggy-back" on the physical JTAG interface
(becoming more and more popular for board testing in designs using
higher-density packaging).

And as far as who has the most ISP devices, I would have to take issue
with declaring Lattice the leader (see the following):

Vantis (AMD)
ISP-only:
MACH111SP	MACH131SP	MACH211SP	MACH221SP	MACH231SP
JTAG and ISP:
MACH355/M4-96	MACH446/M4-128*	MACH466/M4-256*	M5-128*		M5-192*
M5-256*		M5-320*		M5-384*		M5-512*

14 distinct devices, 9 with JTAG testability

*Shipping both 3.3v and 5v devices

Lattice
Proprietary ISP-only:
ispLSI1016	ispLSI1024	ispLSI1032	ispLSI1048	ispLSI2032
ispLSI2064	ispLSI2096	ispLSI2128
JTAG and ISP:
ispLSI3192*	ispLSI3256*	ispLSI3320*	ispLSI6192*

12 distinct devices, 4 with JTAG testability

Clearly the number of ISP devices from Vantis outnumbers that from
Lattice, and
Vantis, too, provides excellent (and free) programming software and
applications
support via their Web-site at www.vantis.com.  

On the issue of speed, Vantis offers the MACH111SP and MACH131SP in -5
speed
grades (tPD = 5.5nsec).  And, as on all MACH 1, 2, 3, and 4 devices,
this speed
is predictable, fixed, and guaranteed - regardless of routing or logic
usage.
No other PLD vendor offers this guarantee.  So speed leadership clearly
belongs
to Vantis as well.

Steve Cooper
Vantis FAE
Article: 6235
Subject: Viewlogic- PUSH VHDL
From: "Anthony" <aelogic@iafrica.com>
Date: 1 May 1997 06:49:42 GMT
Links: << >>  << T >>  << A >>
I have just upgraded to Workview 7.31. I have run their tutorials for
creating symbols
from VHDL and placed those symbols in a schematic. When selecting the
symbols and invoking the pop-up menu the "push-vhdl" etc. options are not
available. I understood from the literature that one could push into the
symbol and bring up the source code for editing. Is this so?. What
attributes are missing so that the PUSH options are unavailable.

Thanks Tony.
Article: 6236
Subject: TEST
From: Darius Braziunas <dariusdb@kaunas.aiva.lt>
Date: Thu, 01 May 1997 01:57:43 -0700
Links: << >>  << T >>  << A >>
Helo all.
Article: 6237
Subject: Re: ISP CPLD from AMD or Cypress???
From: harper@convex.hp.com (David Harper)
Date: 1 May 1997 07:05:52 -0500
Links: << >>  << T >>  << A >>
In article <3367FEAC.6A81@framenbacher.com>,
Joe Schmo  <Joe.Schmo@framenbacher.com> wrote:
>Ed Barrett wrote:
>> 
>> Look into LAttice ISP devices. They have been shipping ISP for 5 years.
      [...]
>> Ed
>
>True, Lattice WAS the first company to really "champion" the concept of
>ISP.  However, as you probably know, this was a Lattice-proprietary ISP
>implementation that remains in their devices today.  However, as ISP has
>become more prevalent, the rest of the industry has adopted the use of
>the
>JTAG Boundary Scan chain to implement ISP functionality.  The main
>benefit
>of this is the ability to "piggy-back" on the physical JTAG interface
>(becoming more and more popular for board testing in designs using
>higher-density packaging).


I hardly think you can blame Lattice for not implementing JTAG in their
early devices at a time when it was unclear that JTAG would ever be little
more than a dream.  As JTAG has grown in popularity Lattice has started to
incorporate it in their new devices.  True, the old devices still use the
original proprietary ISP programming method, but I see nothing wrong in
continuing to support early customers who still manufacture designs based
on that method.

 
>And as far as who has the most ISP devices, I would have to take issue
>with declaring Lattice the leader (see the following):
>
>Vantis (AMD)
>ISP-only:
>MACH111SP	MACH131SP	MACH211SP	MACH221SP	MACH231SP
>JTAG and ISP:
>MACH355/M4-96	MACH446/M4-128*	MACH466/M4-256*	M5-128*		M5-192*
>M5-256*		M5-320*		M5-384*		M5-512*
>
>14 distinct devices, 9 with JTAG testability
>
>*Shipping both 3.3v and 5v devices
>
>Lattice
>Proprietary ISP-only:
>ispLSI1016	ispLSI1024	ispLSI1032	ispLSI1048	ispLSI2032
>ispLSI2064	ispLSI2096	ispLSI2128
>JTAG and ISP:
>ispLSI3192*	ispLSI3256*	ispLSI3320*	ispLSI6192*
>
>12 distinct devices, 4 with JTAG testability
>

And I would have to take issue with your "facts".  The above list doesn't
even mention the ispLSI3160 or the ispLSI3256E, both of which I have used
in designs.  These are also fully JTAG and, as for whether the ispLSI3256E
is a "distinct" device, I would have to say that a device that doubles the
number of I/O pins over the original ispLSI3256 qualifies.  There are also
variations within each device (ie: ispLSI1016E, ispLSI1048C, ispLSI6192FF,
ispLSI6192SM, ispLSI6192DM, etc.).  The product line is also starting to
include members based on 3.3V as well.

>Clearly the number of ISP devices from Vantis outnumbers that from
>Lattice, and
>Vantis, too, provides excellent (and free) programming software and
>applications
>support via their Web-site at www.vantis.com.  
>
>On the issue of speed, Vantis offers the MACH111SP and MACH131SP in -5
>speed
>grades (tPD = 5.5nsec).  And, as on all MACH 1, 2, 3, and 4 devices,
>this speed
>is predictable, fixed, and guaranteed - regardless of routing or logic
>usage.
>No other PLD vendor offers this guarantee.  So speed leadership clearly
>belongs
>to Vantis as well.

The ispLSI2032 is available in a 5.0 ns Tpd speed grade.

>
>Steve Cooper
>Vantis FAE

I certainly see nothing wrong with an employee being proud of his company
or advocating products from that company.  Certainly, the MACH family has
been around for many years and offers a broad product line.  However, to
slam the compition in a public forum, particularly with inaccurate or
misleading facts, does not reflect well on either the individual or the
company they represent. 

regards,
Dave Harper
Sr. Hardware Design Engineer



-- 
Dave Harper           HP - Convex Division             E-mail address:
3000 Waterview Pky.,  Richardson, TX 75080             harper@rsn.hp.com

Article: 6238
Subject: Re: Announcing new division & an fpga implementation
From: Vitit Kantabutra <vkantabu@howland.isu.edu>
Date: Thu, 01 May 1997 14:15:58 -0600
Links: << >>  << T >>  << A >>
Don Husby wrote:
> 
> About two weeks ago, Vitit Kantabutra wrote:
> > I would like to announce a new algorithm for division that retires 2-3 bits
> > [...]
> > Don Husby of the Fermi National Accelerator Lab has implemented a
> > 16/8 bit version of it in ORCA, which can be found in pdf format at the
> > following Web site:
> > http://www-ese.fnal.gov/eseproj/trigger/div16p.pdf
> >
> > Any commercial use of the algorithm is subject to negotiation with Idaho
> > State University and me.
> 
> Although I implemented this algorithm for FPGAs, I don't endorse it as
> optimal for most applications.

Likewise, I don't know whether Don Husby's implementation was an optimal
one.
But I am thankful that an implementation exists. I never meant to imply
that Don Husby endorses the algorithm.  However, I still think that our
algorithm might be faster than the traditional bit-by-bit ones, at least
for larger word lengths. (Read on.)

> It is possible to build a 16/8 divider in
> an Orca FPGA using 16 PFU and producing a result in ~80ns.  This uses the
> simple-minded long division step:
> 
> if (X > D) { X= (X-D)<<1;  Q= (Q<<1)+1; }
>       else { X= X<<1;      Q= Q<<1;     }
> 
> A single step requires an 8-bit subtractor and an 8-bit 2-1 mux.  This
> can be implemented using two Orca PFU.  I beleive it can also be
> implemented using four Xilinx 4000E CLB, since the CLB carry path is
> completely separate from the data path.
> 
> The complete divider is (in psuedo RTL notation):
> 
>   AX[15:8] = SubMux(   X[15:8]    , D[7:0], Q7= Carry, Select= Q7 )
>   BX[14:7] = SubMux( {AX[14:8],X7}, D[7:0], Q6= Carry, Select= Q6 )
>   CX[13:6] = SubMux( {BX[13:7],X6}, D[7:0], Q5= Carry, Select= Q5 )
>   DX[12:5] = SubMux( {CX[12:6],X5}, D[7:0], Q4= Carry, Select= Q4 )
>   EX[11:4] = SubMux( {DX[11:5],X4}, D[7:0], Q3= Carry, Select= Q3 )
>   FX[10:3] = SubMux( {EX[10:4],X3}, D[7:0], Q2= Carry, Select= Q2 )
>   GX[ 9:2] = SubMux( {FX[ 9:3],X2}, D[7:0], Q1= Carry, Select= Q1 )
>   HX[ 8:1] = SubMux( {GX[ 8:2],X1}, D[7:0], Q0= Carry, Select= Q0 )
> 
> Where a SubMux(A,B) is a subtraction of A-B followed by a selection
> of (A-B) or A
> 
> As mentioned above, this takes 16 Orca PFU or possibly 32 Xilinx CLB.
> I can't verify the xilinx design since I don't have my xilinx software
> installed.  An 8/8 divide could possibly be done using only 20 Xilinx CLB.
> 
> Note that the divisor (D[7:0]) must be normalized so that D>128.  This
> will require some extra front end circuitry to do a barrel shift.
> 
> This has many advantages over the algorithm proposed by Vitit Kantabutra:
> 
> 1) It doesn't generate a variable number of bits per iteration.
> 2) It's easy to unroll the loop
> 3) It's at least as fast whether unrolled or pipelined since it doesn't
>    require multi-way multiplexers and shifters.

It is very important to note that our algorithm only requires ONE
full-length
subtraction to retire 2-3 operand bits, plus a 2-bit comparison and a
little
more simple logic.  Admittedly, my experience in only in full-custom
design, not 
FPGA's.  (And in fact, I didn't think of FPGA's at all when I wrote that
paper.
I didn't think about FPGA's until Don Husby and a lot of other FPGA
people wrote me
email in response to my earliest Usenet News posting a few weeks ago.)

However, it does appear, intuitively speaking, that at least for a large
enough
word length (maybe more than 8 bits?), a circuit using our algorithm
could be faster than one that needs 2 full-length subtractions to retire
2 bits.  I've designed very fast carry circuits, so I know that carries
over a large word lengths can be made very fast.  But that comes
at a hardware cost that rises quickly with the word length.  So it
appears that an traditional
adder that needs two full-length subtractions would be larger or slower
than one
using our algorithm if the word length is large.  Now how large it must
be, I don't
know.  But it seems like a very interesting question to explore,
particularly if
you are into FPGA's and must deal with word sizes greater than 8 (?). 
I'd love to
know the answer.  (If I can find time to learn about FPGA's this summer,
I will.  But I have
to teach a summer course to survive.)

> 4) It's not subject to being patented.

I must reassure you that we aren't into a get-rich-quick scheme here.  I
have
suggested to the university to charge a reasonable rate that would be
good for everyone.
If our algorithm is as good as I suspect it is, then the most important
thing for me
is to see that it gets used widely.  I love free things too, but
sometimes it is worth
paying a reasonable amount for something that is worth paying for.

Anyway, I'd love to hear all the pros and cons about our division
algorithm, for whatever sort of design style you might be interested
in.  I don't check Usenet News all the time, so if you post news, you
might want to send it to me also by email.  Thanks.


Vitit Kantabutra
vkantabu@howland.isu.edu
Article: 6239
Subject: Re: Viewlogic- PUSH VHDL
From: david holmes <highgate@best.com>
Date: 1 May 1997 21:48:47 GMT
Links: << >>  << T >>  << A >>
> I have just upgraded to Workview 7.31. I have run their tutorials for
> creating symbols
> from VHDL and placed those symbols in a schematic. When selecting the
> symbols and invoking the pop-up menu the "push-vhdl" etc. options are not
> available. I understood from the literature that one could push into the
> symbol and bring up the source code for editing. Is this so?. What
> attributes are missing so that the PUSH options are unavailable.
> 
> Thanks Tony.
Make sure your sysyem associates an editor with the .VHD extention

David Holmes

HighGate Design
Article: 6240
Subject: Special Session on AI and Logic Synthesis: CFP
From: Henry Selvaraj <Henry.Selvaraj@fcit.monash.edu.au>
Date: Fri, 02 May 1997 16:21:09 +1100
Links: << >>  << T >>  << A >>

ICCIMA'98
         International Conference on Computational Intelligence and
               Multimedia Applications  9-11 February 1998
     
         Monash University, Gippsland Campus, Churchill, Australia
 
 
                 S E C O N D     C A L L      F O R     P A P E R S
 
 Special Session:

      Artificial Intelligence and Logic Synthesis: intelligent
algorithms
 for logic synthesis; functional decomposition in machine learning,
 pattern recognition, knowledge discovery and logic synthesis;
 evolutionary and reconfigurable computing with FPGAs. Chair: Lech
 Jozwiak, Eindhoven University, Netherlands.
  
 Conference Topics Include (but not limited to):
   Artificial Intelligence 
   Artificial Neural Networks 
   Artificial Intelligence and Logic Synthesis
   Functional decomposition
   Pattern Recognition
   Fuzzy Systems 
   Genetic Algorithms
   Intelligent Control 
   Intelligent Databases
   Knowledge-based Engineering 
   Learning Algorithms 
   Memory, Storage and Retrieval 
   Multimedia Systems
   Formal Models for Multimedia
   Interactive Multimedia
   Multimedia and Virtual Reality
   Multimedia and Telecommunications
   Multimedia Information Retrieval

 
 Special Poster Session:
 
 ICCIMA'98 will include a special poster session devoted to recent work
 and work-in-progress. Abstracts are solicited for this session (2 page
 limit) in camera ready form, and may be submitted up to 30 days before
 the conference date. They will not be refereed and will not be
 included in the proceedings, but will be distributed to attendees upon
 arrival. Students are especially encouraged to submit abstracts for
 this session. 
 
 
 Invited Sessions
 
 Keynote speakers (key industrialists, chief research 
 scientists and leading academics) will be addressing 
 the main issues of the conference.
 
 Important Dates:
 
 Submission of papers received latest on:  7 July  97
 
 Notification of acceptance:  19 September 97
 
 Camera ready papers  & registration received by:  24 October  97
 
 
 Submission of Papers
 
 Papers in English reporting original and unpublished research results
 and experience are solicited. Electronic submission of papers via
 e-mail in postscript or Microsoft Word for Windows format directly to
 the General Chair are acceptable and encouraged for the refereeing
 process. If not submitting an electronic version, please submit three
 hard copy originals to the General Chair. Papers for refereeing
 purposes must be received at the ICCIMA 98 secretariat latest by 7
 July 1997. Notification of acceptance will be mailed by 19 September
 1997.
 
 Page Limits
 
 Papers for refereeing should be double-spaced and must include an
 abstract of 100-150 words with up to six keywords.
 
 The accepted papers will need to be received at the ICCIMA 98
 secretariat by 24 October 1997 in camera ready format.  A final 
 preparation format for the camera-ready papers will be provided upon 
 notification of acceptance. Camera ready papers exceeding 6 pages 
 (including abstract, all text, figures, tables and references etc.)
will be 
 charged an extra fee per page in excess to the normal registration.
 
 Evaluation Process
 
 All submissions will be refereed based on the following criteria by
 two reviewers with appropriate background.
 
     originality 
     significance 
     contribution to the area of research 
     technical quality 
     relevance to ICCIMA 98 topics 
     clarity of presentation 
 
 Referees  report will be provided to all authors.
 
 Check List
 
 Prospective authors should check that the following items are attached
 and guidelines followed while submitting the papers for refereeing
 purpose.
 
     * The paper and its title page should not contain the name(s) of 
       the author(s), or their affiliation
     * The paper should have attached a covering page containing 
       the following information 
 
         -title of the paper 
         -author name(s), Affiliation, mail and e-mail addresses, phone
          and fax numbers
         -Conference topic area 
         -up to six keywords 
 
     * The name, e-mail, phone, fax and postal address of the contact
       person should be attached to the submission 
 
 
 Visits and Social Events
 
 Industrial and sight seeing visits will be arranged for 
 the delegates and guests. A separate program will be 
 arranged for companions during the conference.
 
 
 General Chair: 
 
 Henry Selvaraj               
 Gippsland School of Computing 
 & Information Technology
 Monash University,        
 Churchill, VIC, Australia 3842
 Henry.Selvaraj@fcit.monash.edu.au
 Phone: +61 3 9902 6665 
 Fax: +61 3 9902 6842
 
 
 
 International Programme Committee:
 
 Abdul Sattar, Griffith University, Australia 
 Andre de Carvalho, University of Sao Paulo, Brazil 
 Bob Bignall, Monash University, Australia
 Brijesh Verma, Griffith University, Australia (Programme Chair)
 Dinesh Patel, Surrey University, UK
 Henry Selvaraj, Monash University, Australia
 Hyunsoo Lee, University of Yonsei, Korea 
 Jan Mulawka, Warsaw University of Technology, Poland
 Jong-Hwan Kim, Korea Advanced Institute of Science & 
 Technology, Korea
 Lech Jozwiak, Eindhoven Univ. of Tech, Netherlands
 Margaret Marek-Sadowska, University of California, USA
 Marek Perkowski, Portland State University, USA
 Michael Bove, MIT Media Laboratory, USA 
 Mikio Takagi, University of Tokyo, Japan 
 Nagarajan Ramesh,Tencor Instruments, USA 
 Ramana Reddy, West Virginia University, USA 
 Regu Subramanian, Nanyang Tech University, Singapore 
 Sargur Srihari, State University of New York, USA
 Shyam Kapur, James Cook University, Australia 
 Sourav Kundu, Kanazawa University, Japan
 S. Srinivasan, IIT, Madras, India
 Subhash Wadhwa, IIT, Delhi, India 
 Tadeusz Luba, Warsaw University of Technology, Poland
 Vishy Karri, University of Tasmania, Australia 
 Xin Yao, University of New South Wales, Australia
  
 
 International Liaison
 Asian Liaison: 
 Regu Subramanian, Network Technology Research 
 Centre, Nanyang Technological University, Singapore
 
 U.S. Liaison: 
 Marek Perkowski, Portland State University, USA 
 
 European Liaison:
 Tadeusz Luba, Warsaw University of Technology, 
 Poland
 
 
 Organising Committee:
 
 Bob Bignall,  Monash University, Australia
 Baikunth Nath, Monash University, Australia
 Vishy Karri, University of  Tasmania, Australia
 Syed M. Rahman, Monash University, Australia
 Bala Srinivasan, Monash University,Australia
 Cheryl Brickell, Monash University, Australia
 Andy Flitman, Monash University, Australia
 Lindsay Smith, Monash University, Australia
 
   Further Information:
 
   Conference Email :        
                 iccima98@fcit.monash.edu.au
   Conference WWW Page:
                 http://www-gscit.fcit.monash.edu.au/~iccima98
Article: 6241
Subject: Implementing three state output MUXes with Synopsys
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 01 May 1997 23:00:21 -0700
Links: << >>  << T >>  << A >>
I have some problems implementing a design with a MUX having a three
state output with Synopsys FPGA Compiler 3.5a targeted to a Xilinx
4010E part. The MUX is implemented by the following fragment of VHDL
code:

  ybus0 <= ("000000" & yy) when (s(0) = '1') else "ZZZZZZZZZZZZZZZZ";
  ybus0 <= ("000000" & ff) when (s(1) = '1') else "ZZZZZZZZZZZZZZZZ";
  ybus0 <= ("0000000000000000") when (s(2) = '1') else "ZZZZZZZZZZZZZZZZ";
  ybus0 <= ("00000000000000" & cmd) when (s(3) = '1') else "ZZZZZZZZZZZZZZZZ";

Xmake aborts with this error:

XMAKE: ERROR: Failed to find user defined subhierarchy '__tsgen__' in
       'vmc.xnf'.
  >>>  '__tsgen__' must be user defined, since it is not a primitive, a
       Xilinx macro or an XBLOX symbol. Correct the error before running
       XMAKE again.

According to the ``HDL Synthesys for FPGAs Design Guide'' this code
should infer a MUX with BUFT's, pag. 3-52.
I contacted Xilinx support, but I haven't got any answer from them
so far.
Does anyone have a clue?

Thanks in advance

-Arrigo
-- 
Arrigo Benedetti		    e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93				phone: (818) 395-3695
Pasadena, CA 91125				fax:   (818) 795-8649
Article: 6242
Subject: @@ it's very easy to find chipmaker websites (currently 395 valid sites listed here) @@
From: Gray Creager <gcreager@no.spam.scruznet.com>
Date: Fri, 02 May 1997 01:19:15 -0700
Links: << >>  << T >>  << A >>
Just a reminder to everyone.

I have been compiling a semiconductor manufacturer website listing (and
making it available to other engineers on the web) for about 2 years
now.
I used to post it to sci.electronics every so often in the
past, but it got way too big for that. There are 395 companies on
the list currently. These are chipmakers, so if you can't find the data
sheet that you need because you don't know the manufacturer's website,
try my listing. Bookmark it and tell your co-workers.

I try to keep it the most up-to-date and useful listing anywhere on the
web (by constantly searching for new URLs before most others find them)
and it is now widely used by a lot of people. The following categories
exist among my "engineering" subpages.

- Semiconductor URLs (Brief listing)
- Semiconductor URLs (Verbose listing; includes product categories)
- New Semiconductor URLs
- Missing Semiconductor URLs
- Motivations
- 25 Best Semiconductor Websites
- 25 Worst Semiconductor Websites
- Engineering Humor

try it out, I think you'll find it to be quite useful. Let me know what
you think. The URL is:

http://www.scruznet.com/~gcreager

The website is best viewed in a frames environment, but there are "back
doors" for getting to these pages if your browser doesn't support
frames.


-- 
+---------------------------------------------+
| Gray Creager                                |
| http://www.scruznet.com/~gcreager           |
+---------------------------------------------+
| "If you're not part of the solution, you're |
|  part of the precipitate." - Steven Wright  |
+---------------------------------------------+
| to reply to me by e-mail, you'll need to    |
| remove "no.spam." from my e-mail address.   |
+---------------------------------------------+
Article: 6243
Subject: Re: New Lattice (is)pLSI Resynthesis Server now online
From: Tim Forcer <tmf@ecs.soton.ac.uk.nospam>
Date: Fri, 02 May 1997 13:32:09 +0100
Links: << >>  << T >>  << A >>
Frank Dresig wrote:
>For those of you designing with Lattice (is)pLSI devices
>it might be interesting to check out our newly announced
>Lattice Resynthesis server. 
>..cut.. it accepts a (is)pLSI design and resynthesiszes it to
>improve speed, resource usage and fittability.
>..cut.. The service is free, so at least it might
>be worth a try.
>..cut..

Queries out of interest rather than genuine need to know, although I
have used ispLSI:

What is the position on Intellectual Property?  Specifically, would
ISDATA hold any rights in the resynthesised design?

What security is there for designs submitted for resynthesis?

Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University, Southampton, SO17 1BJ     UK

The University is not responsible for my opinions.
Article: 6244
Subject: Schmitt trigger inputs?
From: RODNEYM@rodneym.ibm.net (Rodney Myrvaagnes)
Date: 2 May 97 12:47:13 GMT
Links: << >>  << T >>  << A >>
Are there any FPGAs or CPLDs with Schmitt-trigger inputs that could be driven by a slowly varying voltage (i.e. 10s of Hz)?


-- 
Rodney Myrvaagnes    Associate Editor, Electronic Products
rodneym@ibm.net        516-227-1434        Fax 516-227-1444
When possible, sailing J36 Gjo/a

Article: 6245
Subject: Job-Upstate NY; Senior Engineer; FPGA; Altera
From: richard_steinman@cmagroup.com
Date: 2 May 1997 13:07:04 GMT
Links: << >>  << T >>  << A >>

Job-Upstate NY; Senior Engineer; FPGA; Altera;High Speed Digital. 5+ Years 
Exp. Must have: signal processing, algorithms, high speed digital design 
(40-50 MegaHertz), FPGAs, and exposure to imaging &/or sensor systems 
applications. Client using ViewLogic and Spice CAE/CAD tools. 60-70% design/
detailed design; 30-40% systems level work. TO $43-68K

Please refer to JO# 582RJS in your response.



Richard Steinman
Team Leader
rjs@cmagroup.com
IT & Software Solutions Team
Career Marketing Associates
http://www.cmagroup.com/IT.html
Article: 6246
Subject: Tutorial on Reconfigurable Computing at DAC, June 13th, Anaheim
From: hauck@ece.nwu.edu (Scott A. Hauck)
Date: Fri, 02 May 1997 10:18:27 -0500
Links: << >>  << T >>  << A >>
Reconfigurable Systems:  Logic Emulation, Custom Computing, and Beyond

A Design Automation Conference Full-day Tutorial, June 13th, 1997, Anaheim, CA
(For registration information, please see the DAC website at http://www.dac.com)

Organizer:  Scott Hauck - Northwestern University, Evanston, IL

Presenters:
Michael Butts - Quickturn Design Systems, Inc., Portland, OR
James Gateley - Sun Microsystems, Inc., Mountain View, CA
Scott Hauck - Northwestern University, Evanston, IL
Brad Hutchings - Brigham Young University, Provo, UT
Mark Shand - Digital Equipment Corp., Palo Alto, CA

Audience:  This tutorial is intended for CAD and hardware researchers,
digital logic designers, and others interested in the new opportunities
presented by FPGAs.  Only a basic knowledge of CAD tools and digital logic
design is required.

Description:  Field-Programmable Gate Arrays (FPGAs) are chips that can be
electrically programmed and reprogrammed to implement complex, multi-level
logic.  While commonly thought of as an implementation medium for
glue-logic on circuit boards, they offer great potential for many roles. 
As a logic emulation system, they offer orders of magnitude speedup for
the simulation and verification of integrated circuits.  As a
custom-computing device, they provide world-class performance for numerous
applications.  In this tutorial we will discuss these new opportunities
enabled by FPGA technology, focusing both on what is now possible with
current technology, as well as presenting critical areas for further
innovation.

Scott Hauck will begin the presentation by reviewing FPGA technology,
highlighting their unique features.  He will also explain how these chips
enable new applications, including multi-mode, logic emulation,
custom-computing, and run-time reconfiguration systems.

Michael Butts will then focus on how FPGAs have revolutionized logic
validation.  By considering current and future logic emulation and
rapid-prototyping hardware he will explain how these systems provide huge
speedups for functional simulation.

Brad Hutchings will cover the use of FPGAs for custom computing machines,
systems which provide extremely fast implementations for many different
applications.  He will also discuss run-time reconfiguration, a promising
new technology for multi-tasking digital hardware which may be key to
future high-performance computing.

Although much of FPGA-based system work has been driven by chip
technology, software support for these systems is just as critical as
efficient hardware.  Scott Hauck will present both the successes and
remaining challenges of current CAD tools for multi-FPGA systems.

We will conclude the presentation by focusing on user experiences with
FPGA-based systems.  James Gateley of Sun Microsystems will explain how
logic emulation systems have helped validate several of Sunžs advanced
microprocessors.  Then Mark Shand, part of Digital Equipment Corporationžs
seminal DecPeRLe project, will discuss how FPGA technology has enabled his
group to produce world-class performance, at a relatively low cost, for a
huge set of applications.

We will also feature demonstrations of current commercial and research
reconfigurable systems.  This will provide attendees a chance to explore
this powerful new computing paradigm.


Presenter Biographies

Michael Butts has been Emulation Architect with Quickturn Design Systems
in Portland for the last four years.  He is the co-inventor of logic
emulation, and has written several key patents and papers on
reconfigurable hardware systems.

James Gateley joined Sun Microsystems in 1992 to establish their emulation
program, and is currently Design Verification Manager for the UltraSPARC
III microprocessor.  Starting with the MicroSPARC II, each announced Sun
microprocessor has been successfully emulated, including SuperSPARC II,
UltraSPARC I and UltraSPARC II.

Scott Hauck is an Assistant Professor in ECE at Northwestern University,
specializing in reconfigurable systems.  He has published articles on many
aspects of FPGA architectures, multi-FPGA systems, and CAD algorithms for
FPGA-based systems.  He is the author of upcoming surveys on
reconfigurable hardware and software systems.

Brad L. Hutchings is an associate professor in ECE at Brigham Young
University. In 1993 he established the Laboratory for Reconfigurable Logic
at BYU and currently serves as its director.  He has published many
articles on novel applications of FPGAs, especially run-time
reconfigurability.

Mark Shand has worked on reconfigurable systems since 1988 when he joined
the Digital Paris Research Laboratory.  As a member of the PAM project
(and since) he has worked on all aspects of reconfigurable systems,
including applications, runtime support, CAD algorithms, and board design
and implementation.
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of ECE                        Voice: (847) 467-1849                |
|  Northwestern University             FAX: (847) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@ece.nwu.edu             |
|  Evanston, IL  60208                 WWW: http://www.ece.nwu.edu/~hauck   |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 6247
Subject: Re: ISP CPLD from AMD or Cypress???
From: Ed Barrett <ed.barrett@worldnet.att.net>
Date: Fri, 02 May 1997 12:20:21 -0700
Links: << >>  << T >>  << A >>
Actually, your mis-informed. Lattice has JTAG devices, Boundary scan and
the software to program them. Lattices original family still does use
their proprietary interface, which is very similar to JTAG. The truth is
that the idea of a JTAG standard is a mis-nomer. All it means is that
the manufacturers have agreed to using the JTAG pins for the interface.
How the devices program is still dependent on the manufacturers and no
two are compatible!

Lattice offers 5 families of CPLD devices - 1000E, 2000, 2000V, 3000 and
6000. Each family offers multiple density ranges, and the 2000V family
is a complete 3.3V family that includes programming the device at 3
volts. This results in over 20 parts not including speed grades and
package options that range from 44 & 48 pin TQFPup to a 304 pin package.

As for speed, the 2032 offers a true 5.0 nsec tpd and 180 Mhz operation.
Also, for CPLD architectures tpd is fixed. The Lattice 5.0 nsec is a
fixed guaranteed worst case delay.
Article: 6248
Subject: Re: FPGA chip on Khepera robot
From: adrianth@cogs.susx.ac.uk (Adrian Thompson)
Date: 02 May 1997 18:47:17 -0400
Links: << >>  << T >>  << A >>
ass@daimi.aau.dk (Asger Sporring) writes:
> I'm doing my master thesis on EvolHard, and am going to use the
> Khepera robot for some practical testing.
> 
> But I need to place a FPGA chip (right now I'm looking into using the
> Xilinx chips(like Splash 2), but this is not fixed) on the robot, for
> it to be of any use.
> 
> Does anybody have any experience with this (using, I assume, the
> general IO turret).


I've put a Xilinx XC6216 chip on top of a Khepera, and evolved control
circuits using the real robot+FPGA combination. This was mainly just
as a demo (the behaviour was just the "usual" wall avoider, so it
wasn't a great breakthrough in evolutionary robotics), so I haven't
written it up in a paper. However, I mention it in passing and give a
photograph in my paper "Artificial Evolution in the Physical World"
presented at ER97 last month, and available on my web site (with all
my other papers) at: http://www.cogs.susx.ac.uk/users/adrianth/

I didn't use the general IO turret, but using some info from K-Team I
designed my own interface turret which works along similar lines. I
can give schematics to people who email me. But be warned: I don't
think Xilinx are selling the chip in the package that I have (it was
an engineering sample). I think it's surface-mount only at the moment,
which is bad news for experimenters.

Feel free to contact me, and I'd be very interested to hear about your
thesis,

	Adrian.
____________________
Adrian Thompson,
Evolutionary & Adaptive Systems Group,
University of Sussex,
UK.


--
*****   Crossposted with comp.robotics.research (moderated)  *****
  Summary: Academic, government & industry research in robotics.
      Archives and information: http://www.robot.ireq.ca/CRR
         Charter: ftp://ftp.robot.ireq.ca/pub/crr/Charter
      Meta-discussions/information: crr-request@robot.ireq.ca
Article: 6249
Subject: Re: ISP CPLD from AMD or Cypress???
From: scott.thomas@vantis.com (Scott Thomas)
Date: Fri, 02 May 1997 23:50:52 GMT
Links: << >>  << T >>  << A >>
On Fri, 02 May 1997 12:20:21 -0700, Ed Barrett
<ed.barrett@worldnet.att.net> wrote:

>
>As for speed, the 2032 offers a true 5.0 nsec tpd and 180 Mhz operation.
>Also, for CPLD architectures tpd is fixed. The Lattice 5.0 nsec is a
>fixed guaranteed worst case delay.

Isn't this 5.0 nsec speed only for dedicated inputs (two on the 2032)
and no more than 4 product terms? Doesn't the timing change if I/O
pins are used as inputs, more prouct terms are used, if routing pools
are used? These may be fixed, guaranteed worst case delays, but don't
these cause the tPD to exceed 5.0 nsec?

The point Steve was making is the equivalent Vantis device
(MACH111SP-5) doens't exceed 5.0 nsec.--i.e., Vantis' worst case is
Lattice's best case.

Scott Thomas
Vantis


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search