Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 6100

Article: 6100
Subject: Re: Cadence dfII Layout Plotter: which type are the best solution ?
From: sdb@pctools.com (stevedb)
Date: Fri, 11 Apr 1997 22:34:08 GMT
Links: << >>  << T >>  << A >>
Andreas Wassatsch <wa11@e-technik.uni-rostock.de> wrote:

>for the preparation of a decision, which type of plotter we need, i'm
>looking for comments and experiences of the use of plotters together
>with the Cadence dfII Framework ! Which configuration of the
>plotter is advisable ?

>also an special question to the HP DesignJet 755CM: is the internal 68MB
>RAM of the plotter large enough to plot on A0 a medium chip layout with
>postscript? if not, who about the HP/GL plot ?

>-- =

>#  Andreas Wassatsch                           Tel: +49 (0)381 498 3533
>#  University Rostock                          Fax: +49 (0)381 498 1126
>#  Department of Electrical Engineering
>#  Institute of Applied Microelectronics and Computer Science
>#  Richard-Wagner-Str. 31
>#  18119 Rostock-Warnem=FCnde        email: wa11@e-technik.uni-rostock.de=

>#  Germany            WWW: http://www-md.e-technik.uni-rostock.de/~wass

If your plot pages are typically 36 x 60 inches or less I would highly
recommend the HP 750C --however HPGL/2 and Postscript are not the way
to get good IC plots.

You want to get a GDSII plotting program that will RIP the GDSII data
directly and send compressed bitmap data (RTL) to the plotter. This is
most likely going to be much much faster than creating a huge
Postscript or HPGL/2 file and then letting the plotter RIP it. Even
with 68 Mbytes of RAM the plotter may literally take hours to RIP a
single plot - it depends on the amount and complexity of the vector
data.

HPGL/2 via Pinebush is an extremely expensive approach and doesn't
make sense - if you're going to by a RIP why output HPGL/2 and then
RIP it.

There are relatively low cost software RIPs running on NT and major
UNIX workstations that cost less than US $2000 and are fast. You will
save about $5000 by getting a minimum memory 750C instead of a 68Mbyte
one with the PS option.

You should take a look at a program called GDSPLOT from Artwork
Conversion - I think their web site is www.artwork.com.


I've seen it in use at about 10 different sites in the silicon Valley
driving 650 and 750 plotters.


Steve DiBartolomeo
IC and PCB Design Utilities
Santa Cruz, CA



Article: 6101
Subject: Re: prep benchmarks for FPGAs
From: peter@xilinx.com (Peter Alfke)
Date: Fri, 11 Apr 1997 17:16:10 -0700
Links: << >>  << T >>  << A >>
In article <334E7143.4CC3@eet.cmp.com>, rwilson@eet.cmp.com wrote:


> 
> I'm afraid the vested interest here runs deeper than you might imagine.

Yes it does, and there is a reason why I got so vitriolic, and it is
totally different from what Ron assumes:

I was one of the originators of PREP, and I thought it was an excellent
idea. We struggled with meaningful definitions, and we did a resonable job
with defining these circuits, even though they ended up to the small size,
and they don't stress the interconnect.
Then we implemented them and haggled over the rules of hands-on vs
hands-off, and it still seemed almost meaningful.

Then we looked at each other's results, and I found that our friends at
Altera had achieved a density in excess of 100%. I found that strange, but
we got the explanation that the Altera tool had eliminated redundancies in
the step-and-repeat implementation that is at the core of PREP.

They had found - what then became obvious- that two versions of the
step-and repeat circuits had been defined such that some of the logic
stayed constant between instances. Altera had implemented that part of the
circuitry only once, resulting in what I even today call artificially
inflated density, or a lie.

I argued for staying with the original intent of PREP to show how much
circuitry can really be crammed into a chip, but Altera was adamant in
modifying the implementation in order to take advantage of the oversight
in the definition of two of the PREP designs.

 We had vehement arguments about this point, and that had nothing to do
with Xilinx versus Altera, but rather with my trying to defend the
original intent of PREP. Altera vetoed any suggestion to go back to full
implementation.
 
I thus lost the argument, any interest in PREP, and, as I said, the
respect for the technical integrity of certain PREP members. PREP had
turned into a sham.

If you promised to measure, you measure honestly and don't use any magic
tricks with disappearing logic.

Peter Alfke, speaking for himself
Article: 6102
Subject: Re: Seeking PALASM/ABEL/CUPL/?
From: rauletta@erebor.cudenver.edu (Richard J. Auletta)
Date: 12 Apr 1997 04:46:19 GMT
Links: << >>  << T >>  << A >>
s@cotts.cluon.com wrote:

: I'm working on a simple project, and I am using some GAL22V10s or
: similar for all my combinatorial logic.  However, right now, I have to
: send PALASM source to a friend with a PC who compiles it and emails me
: back the JEDEC files.  

: In days past, it was easy to get vendors to give you programming
: software for many platforms, but now it seems that nobody is
: supporting anything but Windows!  Help!

: I can eat the following binary formats: (in order of preference)

: Far Prefered:
: 	SPARC Binary under SunOS 4.1.x

: Acceptable:
: 	VAX/VMS under VMS 5.2 or VMS 4.6

I would go with Warp2 from Cypress Semiconductor (http://www.cypress.com)
and for $99.00 get their PLD synthesis tools that will handle a 22V10 from
VHDL. Runs on Solaris/SunOS/Windows/HP-UX. All 4 come on the one disk.

Or you could purchase Kevin Skahill's text book "VHDL for programmable logic"
for under $50.00 and get the textbook and software.

Well...you get the textbook and software for $99.00 from Cypress too, plus
it will be a newer version (Warp2 4.1 is better than the 4.0 version and worth
the extra bucks.)

-Rich Auletta

Article: 6103
Subject: The Programmable Logic Jump Station has moved ...
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 12 Apr 1997 09:28:18 +0200
Links: << >>  << T >>  << A >>
The PROGRAMMABLE LOGIC JUMP STATION is now at its new 
domain.  Point your browser to 'http://www.optimagic.com'.

Please also update your bookmarks and links to reflect 
this change.

Our apologies for the inconvenience.
-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.optimagic.com

Article: 6104
Subject: Re: Cadence dfII Layout Plotter: which type are the best solution ?
From: manding@ibm.net (Martin Anding)
Date: 12 Apr 97 13:47:12 GMT
Links: << >>  << T >>  << A >>
I second the recomendation for Artwork Conversion's GDSPLOT.
Plotting HP/GL lets you buy the minimum RAM in the plotter.
And GDSPLOT is about $2,000. This will get you plotting for
under $10K. Plot data size is limited only by the size of spooling space.

We wrote a pearl/TCL shell that allows piks from several
standard plot configurations, select a scale, plot just a layer or two, and start
the plot job. All this is done with a few button clicks.


In <334CBF30.3683@e-technik.uni-rostock.de>, Andreas Wassatsch <wa11@e-technik.uni-rostock.de> writes:
>for the preparation of a decision, which type of plotter we need, i'm
>looking for comments and experiences of the use of plotters together
>with the Cadence dfII Framework ! Which configuration of the
>plotter is advisable ?
>
>also an special question to the HP DesignJet 755CM: is the internal 68MB
>RAM of the plotter large enough to plot on A0 a medium chip layout with
>postscript? if not, who about the HP/GL plot ?
>
>-- =
>
>#  Andreas Wassatsch                           Tel: +49 (0)381 498 3533
>#  University Rostock                          Fax: +49 (0)381 498 1126
>#  Department of Electrical Engineering
>#  Institute of Applied Microelectronics and Computer Science
>#  Richard-Wagner-Str. 31
>#  18119 Rostock-Warnem=FCnde        email: wa11@e-technik.uni-rostock.de=
>
>#  Germany            WWW: http://www-md.e-technik.uni-rostock.de/~wass

Article: 6105
Subject: FAQ
From: ccorrea@unix.horizontes.com.br (Carlos Correa Goncalves)
Date: Sat, 12 Apr 1997 15:39:07 GMT
Links: << >>  << T >>  << A >>
Is there a FPGA FAQ available?


Carlos Correa Goncalves
Computer Scientist
Federal University of Minas Gerais - Brazil
ccorrea@lbd.dcc.ufmg.br
Article: 6106
Subject: Re: prep benchmarks for FPGAs
From: waynet@goodnet.com (Wayne Turner)
Date: Sat, 12 Apr 97 16:00:45 GMT
Links: << >>  << T >>  << A >>
In article <peter-1104971716100001@appsmac-1.xilinx.com>, peter@xilinx.com (Peter Alfke) wrote:
[...]
>If you promised to measure, you measure honestly and don't use any magic
>tricks with disappearing logic.
>
>Peter Alfke, speaking for himself

Then do you also disagree with how your company seems to report macrocell 
usage in your 9500 family, where even if all products terms for a macrocell 
are borrowed the report shows the macrocell as not used, though there are no 
products term left in it?  I found that to be an interesting measurement 
itself.   Correct me if I'm wrong, but if I'm not then what is your opinion on 
that?

Wayne
Article: 6107
Subject: Re: In search of free/low cost PAL/PEEL design sw
From: timolmst@cyberramp.net
Date: Sat, 12 Apr 1997 17:02:01 GMT
Links: << >>  << T >>  << A >>
"Otto Baumann" <obaumann@computerland.dk> wrote:

>Are there any free or low cost PAL/PEEL design/asm. software available ?

>TIA Otto


Chekc out http://www.amd.com. They have PALASM 4, v1.5 on their web
siter downloadable for free. It will cover most standard PALs, and, I
believe, some of the MACH devices too. No support though. They
released ot as FREEWARE, but it is quite good.

Article: 6108
Subject: Re: Seeking PALASM/ABEL/CUPL/?
From: timolmst@cyberramp.net
Date: Sat, 12 Apr 1997 17:05:15 GMT
Links: << >>  << T >>  << A >>
rauletta@erebor.cudenver.edu (Richard J. Auletta) wrote:

>s@cotts.cluon.com wrote:

>: I'm working on a simple project, and I am using some GAL22V10s or
>: similar for all my combinatorial logic.  However, right now, I have to
>: send PALASM source to a friend with a PC who compiles it and emails me
>: back the JEDEC files.  

>: In days past, it was easy to get vendors to give you programming
>: software for many platforms, but now it seems that nobody is
>: supporting anything but Windows!  Help!

>: I can eat the following binary formats: (in order of preference)

>: Far Prefered:
>: 	SPARC Binary under SunOS 4.1.x

>: Acceptable:
>: 	VAX/VMS under VMS 5.2 or VMS 4.6

I assume that you are in a Unix environment??? If yoy have access to a
DOS based system, why don;t you go to the AMD web site and just
download a free copy of PALASM? Go to http://www.amd.com. They have
released PALASM as FREEWARE.

Article: 6109
Subject: Re: Seeking PALASM/ABEL/CUPL/?
From: Pascal Dornier <pdornier@best.com>
Date: Sat, 12 Apr 1997 10:45:43 -0700
Links: << >>  << T >>  << A >>
Richard J. Auletta wrote:
> 
> s@cotts.cluon.com wrote:
> 
> : I'm working on a simple project, and I am using some GAL22V10s or
> : similar for all my combinatorial logic.  However, right now, I have to
> : send PALASM source to a friend with a PC who compiles it and emails me
> : back the JEDEC files.
> 
> : In days past, it was easy to get vendors to give you programming
> : software for many platforms, but now it seems that nobody is
> : supporting anything but Windows!  Help!
> 
> : I can eat the following binary formats: (in order of preference)
> 
> : Far Prefered:
> :       SPARC Binary under SunOS 4.1.x
> 
> : Acceptable:
> :       VAX/VMS under VMS 5.2 or VMS 4.6
> 
> I would go with Warp2 from Cypress Semiconductor (http://www.cypress.com)
> and for $99.00 get their PLD synthesis tools that will handle a 22V10 from
> VHDL. Runs on Solaris/SunOS/Windows/HP-UX. All 4 come on the one disk.
> 
> Or you could purchase Kevin Skahill's text book "VHDL for programmable logic"
> for under $50.00 and get the textbook and software.
> 
> Well...you get the textbook and software for $99.00 from Cypress too, plus
> it will be a newer version (Warp2 4.1 is better than the 4.0 version and worth
> the extra bucks.)

You could also take a look at the CUPL starter kit at
 
  http://www.logicaldevices.com

--------------------------------------------------------------------
Pascal Dornier   pdornier@pcengines.com     http://www.pcengines.com
Your Spec      + PC Engines            = Custom Embedded PC Hardware
--------------------------------------------------------------------
Article: 6110
Subject: XC5204PQ160 Configuration
From: "Yau Man Wai , Roger" <95486158j@polyu.edu.hk>
Date: Sun, 13 Apr 1997 01:58:03 +0800
Links: << >>  << T >>  << A >>
I got a Xilinx XC5204PQ160 FPGA. I can config it using Salve Serial Mode
Successfully.
When I using Master Parallel ( UP ), /INIT go high and configuration
error occur. I am
using the same output file from makebit. ( MCS formet ).
Is the device damaged ?
Is there any suggestions about to config the FPGA through the PC's LPT
ports?

-- 
Yau Man Wai , Roger
Department of Electronic Engineering
The Hong Kong Polytechnic University
http://www.acad.polyu.edu.hk/~95486158j ,
http://www.acad.polyu.edu.hk:8080
mailto:95486158j@polyu.edu.hk , ICQ UIN 703065
Article: 6111
Subject: XILINX FOUNDATION STUFF!!
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 12 Apr 1997 19:22:28 -0400
Links: << >>  << T >>  << A >>

APS has just put up an extensive XILINX FOUNDATION Support page
with links to *selected*  XILINX and ALDEC technotes, utilities, app
notes  and Tutorials.

Sometimes too much information can be almost as bad as none at all.
Filtering
the information down and making select applicable information avaliable
should
save time. This support page should prove helpful to those with XILINX
and particularly the XILINX FOUNDATION software. Check out the following
links:

APS XILINX FOUNDATION Customer support page:
http://www.erols.com/aaps/tech.html

APS Utility Links Page (lots of liinks)
http://www.erols.com/aaps/links.html

EDA Newsletter  (subscribe its free!!!)
http://www.erols.com/aaps/NL_APR97.html

APS X84 Kit Prices (still some VHDL kits  left at VERY low prices)
http://www.erols.com/aaps/x84price.htm

APS Home page
http://www.erols.com/aaps

--
______________________________________________
Richard D. Schwarz, President
Associated Professional Systems (APS)
FPGA Solutions/Test Boards/ EDA Software
SIGTEK Spread Spectrum & Comm. Equipment
3003 Latrobe Court, Abingdon, Maryland 21009
Phone: 410-569-5897   Fax: 410-661-2760
Email: aaps@erols.com
Web site: http://www.erols.com/aaps
_______________________________________________

Article: 6112
Subject: ISPD-97 Registration FULL
From: ispd97@cs.virginia.edu (1997 International Symposium on Physical Design)
Date: Sun, 13 Apr 1997 00:29:20 GMT
Links: << >>  << T >>  << A >>

----------------------------------------------------------------------------
                        IMPORTANT ANNOUNCEMENT

                 ISPD-97 Symposium Registration is Full

         * * *  NO ON-SITE REGISTRATIONS WILL BE ACCEPTED   * * * 

The 1997 International Symposium on Physical Design (ISPD-97) currently 
has well over 200 registrants attending this year's inaugural Symposium. 

This large number of pre-paid registrants means that space for the daily
meeting sessions is completely full, and additional (on-site) registrants
WILL BE TURNED AWAY at the door due to fire-marshal type restrictions.

Thank you for your overwhelming support of ISPD-97!
----------------------------------------------------------------------------


Article: 6113
Subject: ISPD-97 Registration FULL
From: ispd97@eecs.wsu.edu (ACM/PDW Treasurer)
Date: Sun, 13 Apr 1997 00:38:17 GMT
Links: << >>  << T >>  << A >>
----------------------------------------------------------------------------
                        IMPORTANT ANNOUNCEMENT

                 ISPD-97 Symposium Registration is Full

         * * *  NO ON-SITE REGISTRATIONS WILL BE ACCEPTED   * * * 

The 1997 International Symposium on Physical Design (ISPD-97) currently 
has well over 200 registrants attending this year's inaugural Symposium. 

This large number of pre-paid registrants means that space for the daily
meeting sessions is completely full, and additional (on-site) registrants
WILL BE TURNED AWAY at the door due to fire-marshal type restrictions.

Thank you for your overwhelming support of ISPD-97!
----------------------------------------------------------------------------



Article: 6114
Subject: Re: About the usage of Altera maxplus2
From: dbl@hydra1.tyrvos.caltech.edu (Daniel Lang)
Date: 12 Apr 1997 22:27 PST
Links: << >>  << T >>  << A >>
In article <5ilm82$85l$1@uabs64.uab.ericsson.se>, Rolf.Blom@uab.ericsson.se writes...
>In article <5ikojt$r9$2@news.pacifier.com>, yqrkcszwoo@pacifier.com (St.Peter) writes:
>>Lee Jae-Hyuck (starry@kumi2.lge.co.kr) wrote:
>>: Hello! I am using maxplus2 for EPM9560rc304 altera fpga chip. I'd like
>>: to make all non-used pins into
>>: high impedence state, but I cannot find any options in maxplus2. My
>>: maxplus2 version is 7.0.
>>: plesase tell me. thanks in advance.
>>
>>Why would you want to make them so?   Why don't just make them NC
>>in your circuit?
>>
> 
>Possibly because having them NC seem to make the pins outputs.
>Not sure if it's a feature of maxplus2 or the cpld itself.
> 
>It has happened on a couple of designs with this chip.
>Now we just connect unused pins to wide-input OR-gates
>to make them inputs, and the chip gets much cooler.
> 
>/Rolf
> 

If unused pins are being driven by other logic, they should be made inputs.
If they are *not* being driven by other logic, they should be made outputs
so they do not float.  I can't see making the pins outputs increasing the
power consumption unless the pins are already being driven by another source.
It is not a good idea to let input pins float as this can cause noise pickup
and increased power dissipation.

The proper way to make unused pins inputs is to declare them inputs in the
source code (but not referenced elsewhere) and in Assign Pin/Location/Chip,
assign the input signal to a pin number.  This will reserve the pin as an
input.

Daniel Lang  dbl@hydra0.caltech.edu

Article: 6115
Subject: Re: PCI Bus Problems
From: graeme@wallaby.digideas.com.au (Graeme Gill)
Date: 13 Apr 1997 18:41:17 +1000
Links: << >>  << T >>  << A >>

Austin Franklin (#darkroom@ix.netcom.com#) wrote:
: Isn't that two chips?  If you did the PCI interface in the FPGA, then that
: would be one chip?

Except that you can't use an 8k or 10K for this. The PCI interface has
to be non-volatile, or it won't meet the PCI specs.  (There has
to be enough of a PCI inteface there immediatly after powe-on/reset, to
respond to config space cycles with a retry.)

	Graeme Gill.
Article: 6116
Subject: Re: PCI Bus Problems
From: graeme@wallaby.digideas.com.au (Graeme Gill)
Date: 13 Apr 1997 18:43:34 +1000
Links: << >>  << T >>  << A >>

Alfred Fuchs (alfred.fuchs@siemens.at) wrote:
: TNX a lot, I was just looking for this possibility.
: There SEEMS to be another way: Connect the JTAG pins of a FLEX 10k
: device to the PCI-connector and figure out how to pump configuration
: data into these lines on the motherboard side. 
: Anyone got an idea?

In practice, JTAG support from the PCI bus seems to have been dropped.
(You might be hard pressed finding _any_ PCI motherboards that support it.)

	Graeme Gill.

Article: 6117
Subject: Re: PCI Bus Problems
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 13 Apr 1997 14:54:40 GMT
Links: << >>  << T >>  << A >>
The power-on and reset are two separate issues.  From the limited number of
systems that I've looked at, the power-on time is more than sufficiently
long for an FPGA to boot.  The XC4000E family also has a faster boot time
when you enable the proper option in MakeBits.  At power-on, the FPGA is
configuring at the same time that the processor and peripheral chips are
coming awake.

On a system reset (without power cycling), the FPGA is already configured
and can respond immediately.

-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Graeme Gill <graeme@wallaby.digideas.com.au> wrote in article
<5iq681$aht@wallaby.digideas.com.au>...
| 
| Austin Franklin (#darkroom@ix.netcom.com#) wrote:
| : Isn't that two chips?  If you did the PCI interface in the FPGA, then
that
| : would be one chip?
| 
| Except that you can't use an 8k or 10K for this. The PCI interface has
| to be non-volatile, or it won't meet the PCI specs.  (There has
| to be enough of a PCI inteface there immediatly after powe-on/reset, to
| respond to config space cycles with a retry.)
| 
| 	Graeme Gill.
| 
Article: 6118
Subject: Re: XILINX FOUNDATION STUFF!!
From: waynet@goodnet.com (Wayne Turner)
Date: Sun, 13 Apr 97 16:32:04 GMT
Links: << >>  << T >>  << A >>

Now that you have this web site, will it stop you from following-up every 
tools-related post with an advertisement for your company?  

Just curious.

Wayne

In article <33501934.CCC0F77C@erols.com>, aaps@erols.com wrote:
>
>APS has just put up an extensive XILINX FOUNDATION Support page
>with links to *selected*  XILINX and ALDEC technotes, utilities, app
>notes  and Tutorials.
>
>Sometimes too much information can be almost as bad as none at all.
>Filtering
>the information down and making select applicable information avaliable
>should
>save time. This support page should prove helpful to those with XILINX
>and particularly the XILINX FOUNDATION software. Check out the following
>links:
>
>APS XILINX FOUNDATION Customer support page:
>http://www.erols.com/aaps/tech.html
>
>APS Utility Links Page (lots of liinks)
>http://www.erols.com/aaps/links.html
>
>EDA Newsletter  (subscribe its free!!!)
>http://www.erols.com/aaps/NL_APR97.html
>
>APS X84 Kit Prices (still some VHDL kits  left at VERY low prices)
>http://www.erols.com/aaps/x84price.htm
>
>APS Home page
>http://www.erols.com/aaps
>
Article: 6119
Subject: TMS380SRA in an FPGA?
From: waynet@goodnet.com (Wayne Turner)
Date: Sun, 13 Apr 97 16:37:22 GMT
Links: << >>  << T >>  << A >>
Hello all,

This may be rather specific, but is anyone out there using a TMS380SRA 
source-routing-accelerator chip from TI?  It is going obsolete and I was 
wondering if anyone has tried to suck this into an programmable device.  It 
doesn't look overly complex, but there is not a lot of detailed info on the 
device because it interfaces directly to (and ONLY to) a TMS380Cx6 network 
processor.

Any info appreciated.

Wayne
Article: 6120
Subject: Announcing new division & an fpga implementation
From: Vitit Kantabutra <cad@inventor.isu.edu>
Date: Sun, 13 Apr 1997 12:18:39 -0600
Links: << >>  << T >>  << A >>
I would like to announce a new algorithm for division that retires 2-3
bits
per iteration,yet is much simpler than Radix-4 SRT because it uses no
lookup
table. It only needs 2-bit comparisons plus a little simple logic.  The
article is in the proceedings of ICCD '96.

The fastest implementation would be self-time dynamic, but our
algorithm is also suitable for FPGA implementation.  Don Husby of the
Fermi National Accelerator Lab has implemented a 16/8 bit version of it
in ORCA, which can be found in pdf format at the following Web site:

http://www-ese.fnal.gov/eseproj/trigger/div16p.pdf

Any commercial use of the algorithm is subject to negotiation with Idaho
State University and me.

Vitit Kantabutra
vkantabu@howland.isu.edu
(208) 236-3405
Idaho State University
Article: 6121
Subject: Re: PCI Bus Problems
From: wen-king@myri.com (Wen-King Su)
Date: 13 Apr 1997 11:50:06 -0700
Links: << >>  << T >>  << A >>
In a previous article "Steven K. Knapp" <optmagic@ix.netcom.com> writes:
:
;The power-on and reset are two separate issues.  From the limited number of
:systems that I've looked at, the power-on time is more than sufficiently
;long for an FPGA to boot.  The XC4000E family also has a faster boot time
:when you enable the proper option in MakeBits.  At power-on, the FPGA is
;configuring at the same time that the processor and peripheral chips are
:coming awake.
;
:On a system reset (without power cycling), the FPGA is already configured
;and can respond immediately.

We have customers with systems that start to access the PCI bus less than
200ms from power on.  That was too soon for some of the FPGAs.
Article: 6122
Subject: Re: XILINX FOUNDATION STUFF!!
From: Richard Schwarz <aaps@erols.com>
Date: Sun, 13 Apr 1997 20:45:51 -0400
Links: << >>  << T >>  << A >>

Wayne Turner wrote:

> Now that you have this web site, will it stop you from following-up
> every
> tools-related post with an advertisement for your company?
>
> Just curious.
>
> Wayne

Wayne,

Ouch!

Let me respond to that by telling you more about my company and listing
the website just one more time...........

Only kidding. But honestly, the APS-X84 kits are more of a labor of love
(ask my accountant). We have many other more profitable products which
we will not so unabashedly promote on the use groups. When I first
started I was unable to afford any  serious tools and designed many
first generation products with CPLD technology which  weren't as dense,
and which I couldn't reprogram easily. The kits which I discuss most are
our attempt to correct this. We have committed to do some VHDL examples
and will probably continue to announce those.We do hope, however
selfishly, that the kits will lead others to look at our more profitable
products. The EDA Newsletter and all access to support links are totally
free and will remain so.

I have also seen many other announcements on the NG which I personally
have found useful, but which I have seen similar comments as yours
about.  I appreciate and respect your position and will make an attempt
at being more
sensitive to this in order to accommodate other users.

Thank You

--
______________________________________________
Richard D. Schwarz, President
Associated Professional Systems (APS)
FPGA Solutions/Test Boards/ EDA Software
SIGTEK Spread Spectrum & Comm. Equipment
3003 Latrobe Court, Abingdon, Maryland 21009
Phone: 410-569-5897   Fax: 410-661-2760
Email: aaps@erols.com
Web site: http://www.erols.com/aaps
_______________________________________________

Article: 6123
Subject: Surveys on Reconfigurable Computing now available
From: hauck@ece.nwu.edu (Scott A. Hauck)
Date: Mon, 14 Apr 1997 01:03:41 -0500
Links: << >>  << T >>  << A >>
Two survey articles covering hardware, software, and applications of
reconfigurable systems are now available.  Their titles and abstracts are
given below.  The first was written by myself, while the second is a joint
effort with Anant Agarwal at MIT.  Both can be found at
http://www.ece.nwu.edu/~hauck/publications , at the bottom of the page.

These papers will be submitted for publication soon, and all comments are
welcome.

Scott Hauck
hauck@ece.nwu.edu

-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

The Roles of FPGAs in Reprogrammable Systems

Scott Hauck
Department of Electrical and Computer Engineering
Northwestern University
Evanston, IL  60208-3118  USA
hauck@ece.nwu.edu

Abstract

FPGA-based reprogrammable systems are revolutionizing some forms of
computation and digital logic.  As a logic emulation system they provide
orders of magnitude speedup over software simulation.  As a
custom-computing machine they achieve the highest performance
implementation for many types of applications.  As a multi-mode system
they yield significant hardware savings and provide truly generic
hardware.

In this paper we discuss the promise and problems of reprogrammable
systems.  This includes an overview of the chip and system architectures
of reprogrammable systems, as well as the applications of these systems. 
We also discuss the challenges and opportunities of future reprogrammable
systems.

-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

Software Technologies for Reconfigurable Systems

Scott Hauck                Anant Agarwal
Department of ECE          Department of EECS
Northwestern University    Massachusetts Institute of Technology
Evanston, IL  60208  USA   Cambridge, MA  02139  USA
hauck@ece.nwu.edu          agarwal@lcs.mit.edu

Abstract

FPGA-based systems are a significant area of computing, providing a
high-performance implementation substrate for many different
applications.  However, the key to harnessing their power for most domains
is developing mapping tools for automatically transforming a circuit or
algorithm into a configuration for the system.  In this paper we review
the current state-of-the-art in mapping tools for FPGA-based systems,
including single-chip and multi-chip mapping algorithms for FPGAs,
software support for reconfigurable computing, and tools for run-time
reconfigurability.  We also discuss the challenges for the future,
pointing out where development is still needed to let reconfigurable
systems achieve all of their promise.
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of ECE                        Voice: (847) 467-1849                |
|  Northwestern University             FAX: (847) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@ece.nwu.edu             |
|  Evanston, IL  60208                 WWW: http://www.ece.nwu.edu/~hauck   |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 6124
Subject: Tutorial on Reconfigurable Computing at DAC, June 13th, Anaheim
From: hauck@ece.nwu.edu (Scott A. Hauck)
Date: Mon, 14 Apr 1997 01:07:24 -0500
Links: << >>  << T >>  << A >>
Reconfigurable Systems:  Logic Emulation, Custom Computing, and Beyond

A Design Automation Conference (DAC) Tutorial, June 13th, 1997, Anaheim, CA
(For registration information, please see the DAC website at http://www.dac.com)

Organizer:  Scott Hauck - Northwestern University, Evanston, IL

Presenters:
Michael Butts - Quickturn Design Systems, Inc., Portland, OR
James Gateley - Sun Microsystems, Inc., Mountain View, CA
Scott Hauck - Northwestern University, Evanston, IL
Brad Hutchings - Brigham Young University, Provo, UT
Mark Shand - Digital Equipment Corp., Palo Alto, CA

Audience:  This tutorial is intended for CAD and hardware researchers,
digital logic designers, and others interested in the new opportunities
presented by FPGAs.  Only a basic knowledge of CAD tools and digital logic
design is required.

Description:  Field-Programmable Gate Arrays (FPGAs) are chips that can be
electrically programmed and reprogrammed to implement complex, multi-level
logic.  While commonly thought of as an implementation medium for
glue-logic on circuit boards, they offer great potential for many roles. 
As a logic emulation system, they offer orders of magnitude speedup for
the simulation and verification of integrated circuits.  As a
custom-computing device, they provide world-class performance for numerous
applications.  In this tutorial we will discuss these new opportunities
enabled by FPGA technology, focusing both on what is now possible with
current technology, as well as presenting critical areas for further
innovation.

Scott Hauck will begin the presentation by reviewing FPGA technology,
highlighting their unique features.  He will also explain how these chips
enable new applications, including multi-mode, logic emulation,
custom-computing, and run-time reconfiguration systems.

Michael Butts will then focus on how FPGAs have revolutionized logic
validation.  By considering current and future logic emulation and
rapid-prototyping hardware he will explain how these systems provide huge
speedups for functional simulation.

Brad Hutchings will cover the use of FPGAs for custom computing machines,
systems which provide extremely fast implementations for many different
applications.  He will also discuss run-time reconfiguration, a promising
new technology for multi-tasking digital hardware which may be key to
future high-performance computing.

Although much of FPGA-based system work has been driven by chip
technology, software support for these systems is just as critical as
efficient hardware.  Scott Hauck will present both the successes and
remaining challenges of current CAD tools for multi-FPGA systems.

We will conclude the presentation by focusing on user experiences with
FPGA-based systems.  James Gateley of Sun Microsystems will explain how
logic emulation systems have helped validate several of Sunšs advanced
microprocessors.  Then Mark Shand, part of Digital Equipment Corporationšs
seminal DecPeRLe project, will discuss how FPGA technology has enabled his
group to produce world-class performance, at a relatively low cost, for a
huge set of applications.

We will also feature demonstrations of current commercial and research
reconfigurable systems.  This will provide attendees a chance to explore
this powerful new computing paradigm.


Presenter Biographies

Michael Butts has been Emulation Architect with Quickturn Design Systems
in Portland for the last four years.  He is the co-inventor of logic
emulation, and has written several key patents and papers on
reconfigurable hardware systems.

James Gateley joined Sun Microsystems in 1992 to establish their emulation
program, and is currently Design Verification Manager for the UltraSPARC
III microprocessor.  Starting with the MicroSPARC II, each announced Sun
microprocessor has been successfully emulated, including SuperSPARC II,
UltraSPARC I and UltraSPARC II.

Scott Hauck is an Assistant Professor in ECE at Northwestern University,
specializing in reconfigurable systems.  He has published articles on many
aspects of FPGA architectures, multi-FPGA systems, and CAD algorithms for
FPGA-based systems.  He is the author of upcoming surveys on
reconfigurable hardware and software systems.

Brad L. Hutchings is an associate professor in ECE at Brigham Young
University. In 1993 he established the Laboratory for Reconfigurable Logic
at BYU and currently serves as its director.  He has published many
articles on novel applications of FPGAs, especially run-time
reconfigurability.

Mark Shand has worked on reconfigurable systems since 1988 when he joined
the Digital Paris Research Laboratory.  As a member of the PAM project
(and since) he has worked on all aspects of reconfigurable systems,
including applications, runtime support, CAD algorithms, and board design
and implementation.
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of ECE                        Voice: (847) 467-1849                |
|  Northwestern University             FAX: (847) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@ece.nwu.edu             |
|  Evanston, IL  60208                 WWW: http://www.ece.nwu.edu/~hauck   |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search