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Messages from 6425

Article: 6425
Subject: Re: Cheap way to develop for FPGAs?
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Fri, 23 May 1997 08:52:19 +0100
Links: << >>  << T >>  << A >>
Dr. Vitit Kantabutra wrote:
> 
> Stuart Clubb wrote:
> > Lucent Technologies have announced a special "Summer deal pricing" (at
> > least in Europe).
> 
> Is there an ACADEMIC pricing of this available in the U.S., for Win95 or
> Linux platform?  I'd be interested.  Thanks in advance.

I'm not sure that Lucent is very interested in ACADEMIC sales.  At the
UK conference & exhibition "The Annual Advanced PLD and FPGA Day" on May
14, I visited the Lucent stand and was told that their FPGAs were the
biggest, fastest and best (no surprises there then) and that THEREFORE,
they would be of no interest to my University (!!)  I walked off, more
than a little bemused, and wondered what I could have said to produce
such a response.  Later, I was talking to a delegate from another UK
University, who had had exactly the same experience, so it wasn't down
to me - the company must have a policy of discouraging use of their ICs
in academic institutions.

Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions
Article: 6426
Subject: PLEASE, READ THIS !
From: Ivica Hedes <ihedes@mia.os.carnet.hr>
Date: Fri, 23 May 1997 10:39:18 +0200
Links: << >>  << T >>  << A >>
  This message is in MIME format.  The first part should be readable text,
  while the remaining parts are likely unreadable without MIME-aware tools.
  Send mail to mime@docserver.cac.washington.edu for more info.

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---559023410-1804928587-864376758=:8418--
Article: 6427
Subject: Re: Cheap way to develop for FPGAs?
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Fri, 23 May 1997 09:45:25 GMT
Links: << >>  << T >>  << A >>
On Thu, 22 May 1997 13:09:53 -0700, "Dr. Vitit Kantabutra"
<vkantabu@howland.isu.edu> wrote:

>Stuart Clubb wrote:
>> Lucent Technologies have announced a special "Summer deal pricing" (at
>> least in Europe).
>
>Is there an ACADEMIC pricing of this available in the U.S., for Win95 or
>Linux platform?  I'd be interested.  Thanks in advance.

In the UK. Call me - 01256 707107. I am quite happy to engage with the
academic community. No Honest really I am. Price was for WIN95 or NT
platform.

Stuart

Article: 6428
Subject: Re: Cheap way to develop for FPGAs?
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Fri, 23 May 1997 09:50:30 GMT
Links: << >>  << T >>  << A >>
On Fri, 23 May 1997 08:52:19 +0100, Tim Forcer
<tmf@ecs.soton.ac.uk.nojunk> wrote:

>I'm not sure that Lucent is very interested in ACADEMIC sales.  At the
>UK conference & exhibition "The Annual Advanced PLD and FPGA Day" on May
>14, I visited the Lucent stand and was told that their FPGAs were the
>biggest, fastest and best (no surprises there then) and that THEREFORE,
>they would be of no interest to my University (!!)  I walked off, more
>than a little bemused, and wondered what I could have said to produce
>such a response.  Later, I was talking to a delegate from another UK
>University, who had had exactly the same experience, so it wasn't down
>to me - the company must have a policy of discouraging use of their ICs
>in academic institutions.

Lucent does not have a policy of discouraging academic sales. I was on
the stand, and do not beleive that I have said, any such thing. I am
personally interested in users who want to "push the envelope" so to
speak.

If you got that impression, I apologise, and would wish to know which
person gave you that impression.

Stuart

Article: 6429
Subject: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
From: sloman@sci.kun.nl (Bill Sloman)
Date: 23 May 1997 10:27:04 GMT
Links: << >>  << T >>  << A >>
In article <q0raf0gjxx.fsf@vision.caltech.edu>, Arrigo Benedetti <arrigo@vision.caltech.edu> says:
>
>Dear folks,
>
>during the timing simulation with vhdlsim of a system composed of 3
>Xilinx FPGA's I observe spurious glitches on an output signal with
>a duration of the order of 10 ns, while the clock has a 80 ns period.
>I'm wondering why I get this, as synopsys is supposed to generate
>glitch free logic, right ?
>Are maybe the Xilinx cells poorly modeled ? The three FPGA's are
>instantiated in a top level test bench entity, and the signals generated
>by the test bench are carefully timed in order to avoid hold/setup
>violations on the input flip-flops.
>Any idea?

I'd think paranoid - the simulator is more likely to miss glitches
that will appear in reality than to generate spurious glitches that
won't.

Try and look at the low level logic the compiler has produced, and in 
particular, the equations defining the glitch-afflicted output.

Bill Sloman (sloman@sci.kun.nl)        | Precision analog design
TZ/Electronics, Science Faculty,       | Fast analog design and layout
Nijmegen University, The Netherlands   | Very fast digital design/layout
                                       |  e-mail for rates and conditions.
Article: 6430
Subject: Re: Cheap way to develop for FPGAs?
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 23 May 1997 08:49:17 -0400
Links: << >>  << T >>  << A >>
Peter wrote:

> Does it support XC3010-XC3090, for which Lucent/AT&T were a 2nd
> source?
>
> If it does, then it is good value.
>
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to z80@digiserve.com.


The APS-X84-FB1 package supports the AT&T/XILINX 3000 series as well as
the smaller 4000 and 5200 series parts, and CPLDs. The entire system
including router and synthesis, simulation and FPGA test board can be
had for $499.00.These
kits are available now.

see:

http://www.erols.com/aaps

--
______________________________________________
Richard D. Schwarz, President
Associated Professional Systems (APS)
FPGA Solutions/Test Boards/ EDA Software
SIGTEK Spread Spectrum & Comm. Equipment
3003 Latrobe Court, Abingdon, Maryland 21009
Phone: 410-569-5897   Fax: 410-661-2760
Email: aaps@erols.com
Web site: http://www.erols.com/aaps
_______________________________________________

Article: 6431
Subject: Re: Pointer to a BER Circuits
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 23 May 1997 09:14:31 -0400
Links: << >>  << T >>  << A >>
David Fraser wrote:

> Hi,
>         I'm looking for a BERT (bit error rate test) circuit to
> implement in an FPGA.  I've heard that it is possible to construct a
> shift register type circuit that will generate a bit pattern on its
> output that can be transmitted onto a communications network.
> Assuming that the data is looped back somewhere, the circuit would
> also check the incoming bit pattern to see if any bit errors have
> occured.
>         Does anyone know of any references to such a circuit?
>
> Thanks
>         David Fraser
>
> ****************************************************
> David Fraser, dfraser@fpmx.com
> Design Engineer, Fitel-PMX
> 24 Colonnade Rd, Nepean, Ontario, K2E 7J6 Canada

 David,

We are working on just such a circuit. It will be implemented in a
XILINX 520x FPGA(the 5200 FPGAs can be had for as little as 4 bucks!!).
We sell development kits with the all you need (including the hardware)
to develop FPGAs and CPLDs for XILINX. The kits include router, VHDL
synthesizer, schematic capture, simulator, Xchecker cables and X84 FPGA
board.

In about two weeks a FREE VHDL/FPGA  SYNTHESIS guide in HTML will be
posted with various examples. The guide is a no nonsence guide to
FPGA/VHDL synthesis and gets right into designs. The Last lab is a
programmable PN generator which allows you to program up the any of the
different PN patterns  needed for BERTs. Additional labs will follow.
The next scheduled lab will be one on correlators (pattern matching)
then one which will combine the PN and Correlator to produce a BERT. The
neat thing about it is that the X84 FPGA board is a PC ISA board which
is reconfigurable and controllable via the PC ISA bus. So when this
design is completed, you will essentially have a reconfigurable BERT
board. This ISA card platform has really been a plus. It is very
practical and reuseable for many deifferent designs. It can also be
turned on its side and used outside the PC by connecting up a common PC
Power Supply to the Disk Drive type power connector on the FPGA board.
Then download takes place via the provided XCHECKER cable, or on board
eprom socket.

The kits can be seen at:

http://www.erols.com/aaps

______________________________________________
Richard D. Schwarz, President
Associated Professional Systems (APS)
FPGA Solutions/Test Boards/ EDA Software
SIGTEK Spread Spectrum & Comm. Equipment
3003 Latrobe Court, Abingdon, Maryland 21009
Phone: 410-569-5897   Fax: 410-661-2760
Email: aaps@erols.com
Web site: http://www.erols.com/aaps
_______________________________________________

Article: 6432
Subject: Re: Low power PLD?
From: sloman@sci.kun.nl (Bill Sloman)
Date: 23 May 1997 15:34:53 GMT
Links: << >>  << T >>  << A >>
In article <864399833.8709@dejanews.com>, kevintsmith@compuserve.com says:
>
>Bill,
>
>Have you considered using an FPGA rather than a CPLD?  Antifuse FPGAs
>like QuickLogic's are very low power (not as low as the Phillips part) and
>flexible enough to do your more complex designs.  The standby current of
>our parts at 5V is about 2ma; at 3V, around 500uA.  All pASIC2 parts (the
>2003 is under $15 in moderate volumes) have 4 independent clock networks.
>
>Your design sounds like it would fit into our slowest speed grade device.
>The design tools (QuickWorks) are superior to nearly everything in the
>FPGA industry and our tech support is excellent also (hotline calls always
>reach a live apps engineer - not a "case number"!).

Before I get too excited by the prospect, could you tell me how much
I'd have to pay for the QuickLogic design tool? The US dollar price
would be a perfectly adequate indication.

Obviously, the price of the part is important to my client, but I'm 
selling design services, and the price of the programming software is
definitely an item on my budget.

I've got a similar problem with Peter Alfke's response from Xilinx, not
that I've got room on this board for an SPROM for the program (more's the
pity).

Bill Sloman (sloman@sci.kun.nl)        | Precision analog design
TZ/Electronics, Science Faculty,       | Fast analog design and layout
Nijmegen University, The Netherlands   | Very fast digital design/layout
                                       |  e-mail for rates and conditions.
Article: 6433
Subject: Re: Low power PLD?
From: kevintsmith@compuserve.com
Date: Fri, 23 May 1997 10:11:27 -0600
Links: << >>  << T >>  << A >>
Bill,

Have you considered using an FPGA rather than a CPLD?  Antifuse FPGAs
like QuickLogic's are very low power (not as low as the Phillips part) and
flexible enough to do your more complex designs.  The standby current of
our parts at 5V is about 2ma; at 3V, around 500uA.  All pASIC2 parts (the
2003 is under $15 in moderate volumes) have 4 independent clock networks.

Your design sounds like it would fit into our slowest speed grade device.
The design tools (QuickWorks) are superior to nearly everything in the
FPGA industry and our tech support is excellent also (hotline calls always
reach a live apps engineer - not a "case number"!).

Since you seem (by your email address) to be in the Netherlands, give
Thomas Oelsner a call at 011-44-181-846-9023 in Hammersmith, London,
England. He's also at 100417.637@compuserve.com. --- Kevin Smith
QuickLogic FAE Mesquite, TX, USA kevintsmith@compuserve.com

In article <5lhngs$h0t$1@wnnews.sci.kun.nl>,
  sloman@sci.kun.nl (Bill Sloman) wrote:
>
> In article <3366edb8.1614528@news.rt66.com>, mma@rt66.com (Mark Aaldering) says:
> >
> >On 29 Apr 1997 11:35:03 GMT, sloman@sci.kun.nl (Bill Sloman) wrote:
> >
> >>I've got to fit 8 clock extractors/resynchronisers into one or two SMD
> >>PLDs - each has two inputs, three outputs and either three or four
> >>flip-flops depending on what the PLD can be made to do. The system is
> >>clocked at 6MHz.
> >>
> >>But my biggest constraint is that I've only got 50mA for the PLD/PLDs.
>
> 	<snip>
>
> >By my back of the envelope calculation, you need 16 inputs, 24
> >outputs, and 32 Macrocells, and of course low power. This should
> >easliy fit in a CoolRunner Fast Zero Power CPLD - My rough estimate is
> >that total power consumed in a 5V PZ5064 would definitely be less than
> >10mA, probably in the neighborhood of 4mA. This device is available in
> >a 7.5nS Tpd at the power stated above. 3V versions also shipping. The
> >rational behind a 64 Macrocell suggestion is that at 40 I/Os, you're
> >just above the 32 Macrocell devices I/O capability - of course you
> >could partition this into two 32's...
> >
> >For more info, datasheets, etc  refer to our website at
> >
> >         www.coolpld.com
>
> Well, when I tried to fit it into two PZ5032's, the XPLA software pointed
> out that the PZ5032 has only got two clock networks, and thus won't
> support four independent clocks. I hadn't picked this up from my
> reading of the data sheet. I'd already had to reject the AMD MACH110
> because of essentially the same problem, and I thought I'd read the
> Philips data sheet very carefully.
>
> The PZ5064 apparently will support 4 independent clocks, so I hope it
> really is obtainable.
>
> Bill Sloman (sloman@sci.kun.nl)        | Precision analog design
> TZ/Electronics, Science Faculty,       | Fast analog design and layout
> Nijmegen University, The Netherlands   | Very fast digital design/layout
>                                        |  e-mail for rates and conditions.

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6434
Subject: Re: Cheap way to develop for FPGAs?
From: spp@bob.eecs.berkeley.edu
Date: 23 May 1997 16:27:10 GMT
Links: << >>  << T >>  << A >>
Is there a version of the Lucent design system that is
not limited to 400 registers?

Steve
Article: 6435
Subject: RE: Reverse Engineering
From: "Gregory M. Haskins" <bruman@wpi.edu>
Date: Fri, 23 May 1997 12:30:26 -0400
Links: << >>  << T >>  << A >>
Nevermind my last post...I found the information I need....thanks anyway

-gmh

Gregory M. Haskins              Research Assistant 
bruman@wpi.wpi.edu    		CAIS Laboratory
ECE Dept Grad Student 		Worcester Ma
Worcester Polytechnic Inst.     (508)831-5757
http://leonie.wpi.edu/bruman	http://ece.wpi.edu/Research/crypt

Article: 6436
Subject: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
From: Tom Burgess <tburgess@drao.nrc.ca>
Date: Fri, 23 May 1997 10:41:08 -0700
Links: << >>  << T >>  << A >>
Arrigo Benedetti wrote:
> 
> during the timing simulation with vhdlsim of a system composed of 3
> Xilinx FPGA's I observe spurious glitches on an output signal with
> a duration of the order of 10 ns, while the clock has a 80 ns period.
> I'm wondering why I get this, as synopsys is supposed to generate
> glitch free logic, right ?

If the output is combinatorial, glitches are unavoidable for many
logic functions if there is no way to control the skew of the inputs
to the combinatorial block. For example, a 2-input NAND gate will
glitch on a 00, 01, 10, 11, 00 ... binary sequence at the 01, 10
transition if the least-significant bit arrives later than the MSB.
There is an intermediate 11 state which would be visible in a timing
simulation. Hence the suggestion to register combinatorial outputs.

In a (non-CPLD) FPGA, unlike an ASIC, there is no practical way to
guarantee matched routing delays between arbitrary CLBs, so glitches are
unavoidable unless the combinatorial function can be modified to be
skew-tolerant (difficult, I think). Best to keep the glitches within
the CLB, and have only registered signals travelling between CLBs or
to the outside world. This also reduces dynamic power consumption
be reducing wasteful transitions.

	regards, tom
Article: 6437
Subject: Re: FPGA gate counting: No truth in advertising
From: "Kevin Smith" <kevintsmith@compuserve.com>
Date: Fri, 23 May 1997 17:27:28 -0400
Links: << >>  << T >>  << A >>
I wanted to issue a clarification.  I realize my choice of units is
incorrect - 
I was using a shortcut when I specified the impedance of various
interconnect
schemes.  "RC" was intended to mean Resistance*Capacitance, or RC
constant, of a given method.  

Breaking my numbers out, you get:

Metal-to-metal antifuse:
R = 30 ohms
C = 1 fF

Substrate antifuse:
R = 200-500 ohms
C = 5 fF

SRAM cell:
R = 600-800 ohms
C = 50 fF

Sorry for the confusion.
---
Keb'm

kevintsmith@compuserve.com wrote in article
<864164607.7777@dejanews.com>...
> In article <337A1935.5570@xilinx.com>,
>   jwbrooks@xilinx.com wrote:
> >
> > kevintsmith@compuserve.com wrote:
> >
> > Don't believe any vendor on FPGA gates.....
> >
> > You will be better served by counting Flip-flops, look-up tables( or
> > their equivalent), I/Os,
> > and RAM bits ( If applicable ). Gate counting is only good between
> > FGPAs and/or CPLDs from the same vendor. Like XC4000 vs XC5200...
> >
> > Routing plays a huge factor in the ability to utilize these "gates".
> > The amount you can route will often depent on your design, and speed
> > requirements.
> >
> > "gates" are for ASICs only.....
> >
> > Good luck.
> 
> Sorry, but I disagree.	You CAN believe a couple vendors on FPGA gates.
> Part of the above statement is true:  You WILL be better served by
> counting Flip-flops, LUTs, I/Os, etc, because these are more directly
> mappable to your design (you can be reasonably sure how many flip-flops
> you need before you start synthesis or schematic entry).
> 
> Routing in the parts determines the ability to utilize these resources
> only if the chosen architecture has limited routing resources. There are
> two main limitations of routing resources in an FPGA: (1) The logic used
> to hook up gates takes up so much silicon area that you can't populate
> the die with enough routing to hook up all the gates, or (2) The
> resistance of the interconnect is sufficiently large that using too many
> will drastically affect the delay through the path, killing your
> performance.
> 
> QuickLogic provides routing that has neither of these problems.  There is
> sufficient routing wire and interconnect to easily hook up the logic
> cells and I/Os in a device that has every logic cell used and every I/O
> pre-placed.  The low resistance and capacitance of this type of
> interconnect give 1,000 times less impedance (RC = 30ohms for QuickLogic
> vs. RC=40kohms for Xilinx's SRAM interconnect).
> 
> Therefore, you get routing and performance more similar to an ASIC.  You
> also get gate counts that are actually achievable!  A 7,000-gate ASIC
> design will (really) fit into a 7,000-gate QuickLogic device.  However,
> the data sheets provide flip-flop, I/O, and logic cell information so you
> can see for yourself.
> 
> We don't inflate the die size to allow for all that additional routing,
> either.  The link fits neatly between metal layers and is a smaller
> diameter than the metal trace it connects.
> 
> Check out our webpage at www.quicklogic.com for more information.  I know
> the claims sound far-fetched because every FPGA vendor in the past has
> made such promises.  In this case, it's not marketing hype, just superior
> technology.
> 
> Regards,
> ---
> Kevin Smith
> QuickLogic FAE
> (972) 222-2478
> kevintsmith@compuserve.com
> 
> -------------------==== Posted via Deja News ====-----------------------
>       http://www.dejanews.com/     Search, Read, Post to Usenet
> 
Article: 6438
Subject: Workshop for Women in Design Automation
From: Sue Drouin <sue_drouin@mentorg.com>
Date: Fri, 23 May 1997 15:12:42 -0700
Links: << >>  << T >>  << A >>
WORKSHOP FOR WOMEN IN DESIGN AUTOMATION

Sunday, June 8, 1997  9:00AM to 4:00PM
Anaheim Convention Center, Anaheim, CA 
Room A6

"Power and Perceptions" 

Women in today's workplace still face perceptions and myths that date 
back more than 25 years. To move beyond these perceptions, women are 
learning more about themselves and discovering their "personal power" 
and how to use their power to accelerate their careers.

Attend the Workshop for Women in Design Automation, part of the Design 
Automation Conference, to hear from industry professionals that have 
successfully used their "personal power" to achieve their career goals 
and break down perceptions.

Workshop Chair: Eileen Boerger - Vice President, Mentor Graphics Corp. 

Organizing Committee: 
Sue Drouin - Corporate Marketing, Mentor Graphics Corp.
Peggy Herrington - Design Engineering, Intel Corp.
Ann Votino - Design Engineering, Intel Corp.
Debbie Woods - Design Automation, VLSI Technology 

WORKSHOP HIGHLIGHTS

Featured Speaker: Ellen Hancock,Vice President, Technology Office, Apple 
Computer

Power and Perceptions Panel:
Deborah Harvey, Area Sales Manager - VLSI Technology
Kerry Araujo, Director of Strategic Partnerships - Mentor Graphics Corp.
Linda Geppert, Senior Associate Editor - IEEE Spectrum
Deirdre Hanford, Vice President, Corp. Applications Engr.
Design Tools Group. - Synopsys, Inc. 

Leadership Development for Women in Technology (afternoon session)

Networking Social


WORKSHOP FEE: Member ACM or IEEE: US $40 Non-member: US $60
(includes a continental breakfast, lunch and Networking Social)


For more information or to register, call: (303) 530-4333 or fax: (303) 
530-4334
mail to: DAC - 5303 Spine Rd., Ste. A - Boulder, CO 80301
Web: http://www.preas.com/preas/dawomen.html
Article: 6439
Subject: Job opportunities for FPGA experience
From: "Robin M. Morneault" <rmorno@eden.com>
Date: Fri, 23 May 1997 18:07:09 -0700
Links: << >>  << T >>  << A >>
Title: Digital Hardware Designer
Location: Redmond, WA or Austin, TX

Duties:  Member of a high performance team designing state-of-the-art 
emulation hardware to support X86 architecture.

Requirements: 3 years experience doing embedded microprocessor-based 
digital design.  Knowledge of the X86, 16, and 32 bit architectures is a 
real plus.  Knowledge of Assembly and C.  Experience in designing with 
various forms of programmable logic PAL's, GAL's, FPGA, etc.  
Understanding of microprocessor emulation and the operation of emulators.
-- 
Robin Morneault
Professional Recruiter 
Career Consultants Staffing Services
512-346-6660 voice
512-346-6714 fax
headhunter@eden.com
Career Consultants Staffing Services, Inc. has been professionally 
staffing for 25 years as a full service staffing firm that provides 
executive search, direct hire, contract, technical and temporary 
services.
Article: 6440
Subject: Re: Anyone using Actel software?
From: actelfae@aol.com (ACTELFAE)
Date: 24 May 1997 01:07:44 GMT
Links: << >>  << T >>  << A >>
ACTEL Software is GREAT.
I have a few years experience with Actel.  Their silicon is fast, and the
software is 100% automatic Place and Route.  The envy of all silicon
vendors.

Regards.
Article: 6441
Subject: Xilinx future features?
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: 24 May 1997 05:28:03 GMT
Links: << >>  << T >>  << A >>
Over on the Xilinx home page there is a very interesting
NetPresentation(tm) by Wim Roelandts, the Pres. and CEO of Xilinx, on the
future of FPGAs -- or more precisely the continuing evolution of the 4K
family.  Much of the talk discusses the transition to 0.25 micron and
smaller processes and the ramifications for mixed voltage systems, speed,
cost, etc.  Quite interesting.

The really tantalizing content occurs about ten minutes into the talk,
where a slide lists some of the new architectural features on the way. 
Here are some highlights:

	1998
	32,000 logic cells (400K gates)
	fast re-configure
	hierarchical memory solution
	...

	1999
	65,000 logic cells (800K gates)
	build-in logic analyzer
	D/A & A/D support
	custom cores
	high speed differential interface (500 MHz) 
	...

What does this portend?

32K cells, 64K cells -- whew, I still find 800 4-LUT 4010Es pretty roomy.

Fast reconfiguration (partial reconfiguration too, I hope): great.  The 4K
family is not strong in this area.  It would be even better if it shared
some of the XC6200's penchant for direct memory mapped access to internal
device registers and/or SRAMs.

"Hierarchical memory solution" -- perhaps *both* fine grained distributed
select-RAM *and* larger shared blocks of RAM a la the Altera 10K EABs.  Or
even a three-level hierarchy -- for example, 16-bits per logic block
(select RAM), plus 4x256x8 SRAM per 16x16 region, plus one central 16x4Kx8
SRAM.

"Built-in logic analyzer" -- hey, Xilinx is already unique in their device
readback capability.  (Which makes a pretty darn good poor man's simulator,
by the way.)  I suppose they'll add a way to shift out or read out selected
registers and RAM contents, and perhaps 4-LUT outputs, instead of the
current 4K behaviour of dumping everything including the configuration
bits.

D/A & A/D support -- high integration to capture more of those DSP design
wins of course.

custom cores -- one can hope for a dedicated PCI or even AGP interface
implementation

high speed differential interface -- RMBS?  Even if not, fast inter-chip
interconnect could make it much easier to partion large designs across
arrays of FPGAs and reduce the pressure to go to higher and higher pin
counts.

This is going to be fun.  Or as Steve Ballmer once said, "It's a great time
to be us."

Jan Gray

Article: 6442
Subject: Re: Cypress WARP question
From: vaughan@wave.co.nz
Date: 24 May 1997 09:44:05 GMT
Links: << >>  << T >>  << A >>
In <5m2qfc$j3p@samba.rahul.net>, "Stephen P. Pope" <spp@rahul.net> writes:
>There is a Cypress product, on CD, entitled "Cypress WARP Version 4.0".
>The current Cypress databook does not to describe a product
>by this exact name; the products listed there are "Warp2", 
>"Warp2+", "Warp3", and "Warp3 Pro Series Built-in".
>
>Does "WARP Version 4.0" correspond to any of these?
>
>Thanks.
>Steve

I have Warp2 release 4.1
Article: 6443
Subject: Re: What is M1?
From: timolmst@cyberramp.net
Date: Sat, 24 May 1997 11:49:59 GMT
Links: << >>  << T >>  << A >>
Simon Bacon <SimonBacon@tile.demon.co.uk> wrote:

>For those of us who are not on the M1 pre-release program - possibly
>because we don't have paid-up software support - what is M1?

M1 is the first release of Xilinx developement software to contain the
back-end place-and-route tools from NeoCad.

>From other posts, it sounds as if XNF is being dropped.  Is that
>correct?

I don't know about that. They have changed the file type from XNF to
XTF, but I don't expect that they have substantialy changed the
netlist file format.

>Will we have to abandon our home-grown tools which manipulate
>and/or generate XNF?

Again, I don't know. What home-frown tools do you have?



Article: 6444
Subject: What is M1?
From: Simon Bacon <SimonBacon@tile.demon.co.uk>
Date: Sat, 24 May 97 14:16:07 GMT
Links: << >>  << T >>  << A >>
For those of us who are not on the M1 pre-release program - possibly
because we don't have paid-up software support - what is M1?

From other posts, it sounds as if XNF is being dropped.  Is that
correct?

Will we have to abandon our home-grown tools which manipulate
and/or generate XNF?

---
Regards
Simon

Article: 6445
Subject: Best way to learn VHDL?
From: Robert Trent <trent@helix.net>
Date: Sat, 24 May 1997 15:22:00 -0700
Links: << >>  << T >>  << A >>
Okay, I've been using schematic capture for all of my designs (Actel
1240s and 1280s, Xilinx 5210 and 5215).  This summer I'll be starting on
a new large audio signal processing design and I want to design with
VHDL.  I'm not sure, at this point, what chip I'll be using but I've
been eyeing some of the larger Altera 10K series FPGAs.  I think I'll be
needing about 50,000 gates.

So what's the best way to learn VHDL?  Any recommended texts? Courses? 
Tutorials?  Or do I just dive in?  I'll be talking to some of the FAEs
soon but I want some less biased opinions from this newsgroup...

Robert.
Article: 6446
Subject: Looking for FAQ
From: slam@lodestone.cnet.att.com (simon.lam(65)-754-2315)
Date: 25 May 1997 04:37:14 GMT
Links: << >>  << T >>  << A >>
Folks,

Does anyone know if there is a FAQ site for this nesgroup? 

Thanks in advance!

Article: 6447
Subject: Re: Best way to learn VHDL?
From: "William E. Lenihan III" <lenihan3we@earthlink.net>
Date: Sun, 25 May 1997 00:45:24 -0700
Links: << >>  << T >>  << A >>
Robert Trent wrote:
> 
> Okay, I've been using schematic capture for all of my designs (Actel
> 1240s and 1280s, Xilinx 5210 and 5215).  This summer I'll be starting on
> a new large audio signal processing design and I want to design with
> VHDL.  I'm not sure, at this point, what chip I'll be using but I've
> been eyeing some of the larger Altera 10K series FPGAs.  I think I'll be
> needing about 50,000 gates.
> 
> So what's the best way to learn VHDL?  Any recommended texts? Courses?
> Tutorials?  Or do I just dive in?  I'll be talking to some of the FAEs
> soon but I want some less biased opinions from this newsgroup...
> 
> Robert.

I started off learning VHDL by (a) reading books [Doug Perry] and
articles and (b) looking at other people's code, then going out and
doing small chunks of RTL code in otherwise mostly-schematic designs. It
has been and still is a slow climb towards doing total-VHDL designs.

If you don't want to make the slow transition that I did, then I think
it is essential to have an expert at your side. VHDL is too stiff and
verbose a language to learn by yourself if you are under a real project
deadline. If you don't have an in-house expert, your org will have to
bite the bullet and hire a consultant. Johan Sandstrom (Manhattan Beach,
CA) or SEVA Technologies (San Diego, CA  ... I think) are 2 VHDL experts
that come to mind. Their email addresses can be found from Integrated
System Design magazine's directory.

-- 
=====================================================================
 William Lenihan                            lenihan3we@earthlink.net

    "The greatest barrier to communication is the delusion that
     it has already occurred."       -- Peter Cummings
=====================================================================
Article: 6448
Subject: Re: What is M1?
From: timolmst@cyberramp.net
Date: Sun, 25 May 1997 08:08:21 GMT
Links: << >>  << T >>  << A >>

>I don't know if the xnf file format will be dropped from the design flow
>with the M1 release, but I am certain I've heard one or more Xilinx reps
>say that their plan for some time in the future involves completely
>replacing the use of xnf with the edif file format. 

M1 definately has EDIF I/O, but they still use something called an XTF
file, which I think is an XNF file in disguise.

Article: 6449
Subject: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
From: "William E. Lenihan III" <lenihan3we@earthlink.net>
Date: Sun, 25 May 1997 01:10:20 -0700
Links: << >>  << T >>  << A >>
Arrigo Benedetti wrote:
> 
> Dear folks,
> 
> during the timing simulation with vhdlsim of a system composed of 3
> Xilinx FPGA's I observe spurious glitches on an output signal with
> a duration of the order of 10 ns, while the clock has a 80 ns period.
> I'm wondering why I get this, as synopsys is supposed to generate
> glitch free logic, right ?
> Are maybe the Xilinx cells poorly modeled ? The three FPGA's are
> instantiated in a top level test bench entity, and the signals generated
> by the test bench are carefully timed in order to avoid hold/setup
> violations on the input flip-flops.
> Any idea?
> 
> thanks in advance
> 
> -Arrigo
> --
> Arrigo Benedetti                    e-mail: arrigo@vision.caltech.edu
> Caltech, MS 136-93                              phone: (818) 395-3695
> Pasadena, CA 91125                              fax:   (818) 795-8649


I once wrestled with a glitchy multiplexer, that was driving the
edge-sensitive write-enable of a RAM, and (re-)discovered the wonderful
world of function and logic hazards (see Modern Digital Design by
Richard Sandige, McGraw-Hill, 1990).

Inquiries to Synopsys revealed that the design compiler family does NOT
produce glitch-free logic clouds. Even if you introduce functionally
redundant "cover terms" into your HDL equations, they will be optimized
out by the synthesis algorithms. Essentially, combinatorial logic clouds
should not drive edge-sensitive devices. If they do, you ought to find a
way to register them (as others have mentioned) before reaching their
edge-sensitive destination.

Also, when it comes to FPGAs and CPLDs, this problem is not just
peculiar to synthsis: if you are thinking about doing this part of your
design in schematic and adding the cover terms there, be warned that
most vendor's mapping and P&R tools will also remove redundant logic in
the NETLIST it is fed, regardless of whether it came from schematic or
synthesis. The only exception is if the cloud is small enough to fit in
one LUT - these are usually glitch-free (though the vendor may not
guarantee it). 

-- 
=====================================================================
 William Lenihan                            lenihan3we@earthlink.net

    "The greatest barrier to communication is the delusion that
     it has already occurred."       -- Peter Cummings
=====================================================================


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