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Messages from 6375

Article: 6375
Subject: Re: Cadence or World Technology, or other NT vendors...
From: jhesse@netcom.com (John Hesse)
Date: Mon, 19 May 1997 17:53:50 GMT
Links: << >>  << T >>  << A >>
In article <3379d2a2.493272@nntp.a001.sprintmail.com>,
Mark Champion <mchampion@Xbigfoot.com> wrote:
>...
>On the other hand, ASIC designers will commonly use Verilog.  If you
>do an ASIC, most of the ASIC vendors will require Verilog XL sign off.
>That pretty much means you will have to buy Verilog XL from Cadence -
>about $20-25K.  I'm not sure what VHDL ASIC designers do for signoff.
>
>mchampion@Xbigfoot.com

World Technology has a Verilog development system for NT at a "special" 
price of $8,400 for 2 seats. Any comments on how good this system is? 

I need to do a verilog simulation to verify a design--but will not be 
making chips from it. I need a solid development system with a good 
interface (as this will be my first non-toy verilog project).
The price of $20-25K for Cadence is very steep for the short term 
use: 6-9 months. Ouch.

BTH, I selected Verilog because I've taken a class on it and it suits the 
design very well (I don't want to learn VHDL :).  Comments on NT Verilog 
products would be appreciated. 

Cheers,

John
-- 
 - - - - - - - - - - - - - - -
John Hesse
Moss Beach, Calif
jhesse@netcom.com
 - - - - - - - - - - - - - - - 
Article: 6376
Subject: Re: Fast comparator
From: Steve Wiseman <steve@sj.co.uk>
Date: Mon, 19 May 1997 19:50:39 +0100
Links: << >>  << T >>  << A >>
Svenn-Ivar wrote:
> 
> I've been thinking of using an FPGA as a trigger circuit in a (not so
> high-end) digital scope. Functions I need are high speed comparison of
> two 10-bit digital values against each other and against predetermined
> values. Output would be an indication if to trig or not.
> I'm not familiar to FPGA's or other 'programmable logic' so I would like
> to know if this is possible to do, before I go any further. With high
> speed I mean about 10ns from value input to indication output.
> Suggestions are highly appreciated!

Hi, 
  why the need for 10nS? If you were prepared to accept a longer, but
fixed, delay, you could pipeline the compare as deep as you like, and
make your life easier. Assuming your 'scope was 'idling' by sampling the
data and writing to RAM, and the trigger was merely an indication to
stop sampling a set number of samples later, the pipeline could be
trivially compensated out. I'm also impressed that you're designing in
100MSa/s, 10 bit ADCs. Perhaps the trigger only needs to be 8 bits
accurate? Any chance of sharing your analogue front-end design?

just a couple of suggestions, hope they help. 

steve
Article: 6377
Subject: Re: VHDL PCI FPGA Implementation
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Mon, 19 May 1997 21:32:34 GMT
Links: << >>  << T >>  << A >>
On 18 May 1997 21:58:15 GMT, "Steven K. Knapp"
<optmagic@ix.netcom.com> wrote:

<snip>
>You can judge the compliance for yourself by downloading the PCI Protocol
>Compliance Checklist at
>'http://www.xilinx.com/products/logicore/lounge/pcim/docs/pcicompl.pdf'. 

Design by checkbox compliance is not, IMHO a good way to check whether
a solution is a suitable design. For example:

Altera's pci_a core which claims "full PCI compliance":

On page 6 of document dsdma_01.pdf altera states:
"To allow the pci_a to pass the PCI set-up requirement, the framen,
trdyn, and stopn signals are split into two unidirectional (input,
output) signals. For example, the PCI signal trdyn is connected to the
input trdyn_in and the output trdy_out. The input trdyn_in is
connected to a dedicated input on the FLEX 10K device, and the output
trdyn_out is connected to an I/O pin on the FLEX 10K device."

Does that mean Altera has two pins on a single PCI signal?
I thought the PCI spec only allowed one pin load per signal? It'll
sure break the 10pF rule. If so, then Altera can claim PCI compliance
as much as they like, they would not be "fully compliant".

On a side issue, I would also be fascinated to know how they meet the
clk2q, AND the necessary setup and hold times, when there is only one
flipflop in the IOB.

Xilinx's PCI solution:

Document pcids.pdf page 4 indicates that in burst mode when supplying
data, the Initiator and targets both supply data to the PCI bus at 50%
data rate as a wait state insertion is required on every cycle.

I couldn't find any publish VI characteristics data for Xilinx. Is it
available? Does it meet the PCI spec?

Lucent's solution supplies data at a full single cycle, thus having 2x
the performance of the Xilinx core. It uses one pin per signal, and
achieves all the simple "finger in the air" requirements of setup/hold
plus clk2q for compliance. The master also has a FIFO etc. etc. All
this in 3.3V and 5V parts too.

On the datasheet evidence  published by vendors, I would venture to
suggest that Altera is not truly compliant, Xilinx is compliant (where
are the VI curves), but suffers a performance hit, and Lucent is
compliant with no performance hit.

I guess APP01's comment of:

>And this kit is the ONLY one that is "really" PCI compliant.
>
>Caution.. Read the specs carefully and compare teh data books.

Is valid.

Just reading those pdf's as suggested.
Stuart

Article: 6378
Subject: Job opportunity, Xilinx experience, Berkeley CA
From: "Dzintar Dravnieks" <dz@gigaops.com>
Date: 20 May 1997 00:28:26 GMT
Links: << >>  << T >>  << A >>
Giga Operations Corporation

A leading edge, Reconfigurable Computing Company in Berkeley, CA

Job Openings:

Engineer with current Xilinx XC4000E series FPGA design experience. 

Immediate Opening, Full Time Position (possibly consulting leading to full
time position)

Sign on Bonus (paid after 90 days work time)

Reference Bonus (paid after 90 days work time)

Substantial Stock Options Available

Job Description:

Engineer with current Xilinx XC4000E series FPGA design experience.  

Ideal candidate has strong background in algorithm analysis for
partitioning between software, hardware, and FPGA executables..

Ideal candidate has strong background in partitioning and execution of
algorithms between multiple FPGAs, memories, interconnect, and I/O.

Xilinx PCI Logicore experience is highly desirable, but not required.

Possible senior position as Systems Architect, CTO, or VP Engineering.

Desirable experience for senior position includes FPGA design with
schematics & VHDL/Verilog tools, digital and analog hardware design,
software design, software tool design, and surface 
mount manufacturing experience.

A background in Video, DSP, or Telecommunications is a major plus.

Immediate task priorities are:

(1) learn current system architecture 
(2) support OEM, engineering, academic customers  
(3) create customer required Xilinx PCI Logicore executables 
(4) create and modify FPGA designs for customer requirements 
(5) support sales process by evaluating customer requirements and analyzing
and
executing the mapping of customer algorithms into Giga Ops' hardware
architecture.

Please email resume to paul@gigaops.com or fax to 510-848-5667.  
Article: 6379
Subject: Re: VHDL or Verilog?
From: henrik@chronologic.com (Henrik Eriksson)
Date: Tue, 20 May 1997 03:22:17 GMT
Links: << >>  << T >>  << A >>
Some Companies(few) actually sign off  using VITAL (VHDL).

Another way(common in Europe where VHDL is big) is to translate(or
write out) the netlist using for instance Synopsys in Verilog format.
Then use FusionHDL(handles both VHDL & Verilog)  from Viewlogic that
can simulate the testbench in VHDL, but uses VCS(Verilog) to get the
accuracy and sign-off from the Vendor.
VCS has sign-off with most of the major ASIC vendors.

Henrik


Volker Hetzer <hetzer.abg@sni.de> wrote:

>Amr G. Wassal wrote:
>> 
>> On Wed, 14 May 1997, Mark Champion wrote:
>> 
>> > On the other hand, ASIC designers will commonly use Verilog.  If you
>> > do an ASIC, most of the ASIC vendors will require Verilog XL sign off.
>> > That pretty much means you will have to buy Verilog XL from Cadence -
>> > about $20-25K.  I'm not sure what VHDL ASIC designers do for signoff.
>> >
>> > mchampion@Xbigfoot.com
>> >
>> > Mark Champion - Leave out the "X" to send me email
>> >
>> >
>> 
>> Waht do you mean by signoff, anyways?
>It's when you tell the IC-Company that the code you produced is the
>one the ASIC should be compatible to.
>Then the IC-Company starts to produce ASICs (yes, there are
>risc-prods...)
>and when the ASIC does not do what you want, you have to prove that the
>ASIC is not compatible to the code you provided.
>
>But now I'm interested too. How to sign off a VHDL-project?
>
>Volker

Article: 6380
Subject: Use your networked computers for large scale simulations
From: Active Tools Corporation <davida@activetools.com>
Date: Tue, 20 May 1997 15:16:30 +1000
Links: << >>  << T >>  << A >>
FOR IMMEDIATE RELEASE

Contact:

Sergij Foski
Active Tools, Inc.
Phone: (415) 882-7062
Fax: (415) 680-2369
email: sergij.foski@activetools.com


Active Tools Announces Clustor(tm) 1.1 for Exploiting 
the Combined Power of Networked Computers

San Francisco, CA - May 12, 1997 -- Active Tools, Inc. 
today announced the release of Clustor 1.1, a software tool 
for distributing and managing computationally intensive tasks. 

"Clustor delivers computing power to users with ever 
increasing needs for more computing cycles." said Rok Sosic, 
President and CEO of Active Tools, Inc. "With Clustor, they 
can routinely combine the power of networked computers."

Clustor greatly simplifies and speeds up parametric executions 
- running the same application numerous times with different 
input parameters. It generates jobs, speeds up the task by 
distributing the jobs over a network and collects the results. 
Jobs can be distributed over a local area network or over Internet. 
Version 1.1 of Clustor provides new features for load monitoring 
and resource sharing.

Clustor is targeted at users, such as engineers, scientists 
and researchers. It provides an intuitive graphical user 
interface for all phases of executing jobs on a network of 
computers: from task preparation, job generation to job execution. 
Now, the combined power of networked computers can be exploited
by users with no knowledge of programming parallel or distributed 
applications.

Clustor is already being used in fields, such as VLSI 
circuit design,  electronic design automation, bioinformatics, 
operations research, computer graphics, ecological and environmental 
modeling, laser and particle physics.

According to Dr. Andrej Sali, Assistant Professor at 
Laboratory of Molecular Biophysics, Rockefeller University in 
New York "We found Clustor extremely helpful in squeezing more CPU 
time from our workstations, resulting in a  highly increased job 
turnaround time and productivity."

Clustor version 1.1 is currently available for major Unix 
environments such as Digital Unix, Hewlett Packard HP-UX, IBM AIX, 
Silicon Graphics Irix, Sun  Solaris and Linux. A version of Clustor 
for Windows NT environment will  be released later this year.

Clustor 1.1 for Unix is priced at $695. Additional computational 
nodes are $149. Clustor 1.1 for Linux is priced at $495 and $99, 
respectively. Academic discount of 40% is available to academic 
institutions for non-commercial use. Clustor can be purchased 
directly from Active Tools. Copies of Clustor and free 30-day 
evaluation licenses are available at http://www.activetools.com/.

Active Tools, founded in 1995, is a developer of software tools 
for high performance computing. The founders have been developing 
software tools for more than 15 years in both industry and academia. 
Active Tools is a privately held company with offices in United States 
and Australia.

Clustor and Clustor Node are trademarks of Active Tools, Inc. 
All other company and product names mentioned may be trademarks 
or registered trademarks of the respective companies with which 
they are associated.
Article: 6381
Subject: Re: Fast comparator
From: Tim Warland <twarland@nortel.ca>
Date: Tue, 20 May 1997 08:29:24 -0400
Links: << >>  << T >>  << A >>
Svenn-Ivar wrote:
> 
> I've been thinking of using an FPGA as a trigger circuit in a (not so
> high-end) digital scope. Functions I need are high speed comparison of
> two 10-bit digital values against each other and against predetermined
> values. Output would be an indication if to trig or not.
> I'm not familiar to FPGA's or other 'programmable logic' so I would like
> to know if this is possible to do, before I go any further. With high
> speed I mean about 10ns from value input to indication output.
> Suggestions are highly appreciated!
> 
Since the application you describe is combinatorial, it is best 
implemented in a CPLD not an FPGA (unless you intend to pipeline 
it through clocked flip flops).  Since you're putting one in the 
design, you can start thinking of other functions to shoe horn in.

Cheers
Tim Warland
ASIC Engineer
-- 
You better be doing something so that in the future
you can look back on "the good old days"

My opinions != Nortel's opinion;  Nortel's Hardware :-)
Article: 6382
Subject: Re: FPGA gate counting: No truth in advertising
From: Tim Warland <twarland@nortel.ca>
Date: Tue, 20 May 1997 08:38:25 -0400
Links: << >>  << T >>  << A >>
APP01 wrote:
> 
> Ok.. yes everyone counts gates differently at least until a year or so
> ago.
<snip> 
> Now as far as ASIC versus FPGA gates,  I have a general rule of thumb
> that an FPGA will require about 2.5 x Asic gates. This is very dependent
> upon tge FPGA architecture and the design. Some FPGA;s have narrow LUT
> functions, which can increase the required gates..
> 
Concur. The current gate counting philosophy is crap at best. I think
a more realistic approach is just to give the number of flip flops
and we'll assume each FF has a LUT in front of it.  This gives the
idea of number of cells.  FPGA vendors used gates to compare to ASIC
Gate
Arrays, however there is no correlation between the two so the idea
should be dropped. As noted above I compare a 10k100 to a 20,000
gate ASIC (which gives some overhead for how well/poorly the design
fits and for routing).

Cheers

Tim Warland
ASIC Engineer
-- 
You better be doing something so that in the future
you can look back on "the good old days"

My opinions != Nortel's opinion;  Nortel's Hardware :-)
Article: 6383
Subject: Problem in Leonardo synthesis targetting Altera
From: Mark Sandstrom <Mark.Sandstrom@martis.fi>
Date: Tue, 20 May 1997 16:13:48 +0300
Links: << >>  << T >>  << A >>
Hi!

I'm synthesizing by Leonardo v4.03 to Altera FLEX10K CPLDs. 
If I load and resolve the FLEX10K modgens, the edif produced 
by the write altera -command contains cell referencies to 
"BUF":s.

The Altera's place and route tool Maxplus2 (v7.2) doesn't 
accept this edif and issues an error message: 
"Error: Can't find design file 'buf'".

I've been told that FLEX10K libraries that Maxplus2 uses 
don't contain an element called "BUF".

There is no problem with cell referencies to "AND2", "OR2" etc.

If I don't load and resolve the modgens in Leonardo, 
the Maxplus2 accepts the Leonardo's edif output, but the 
synthesis result is not good enough.

Is there any known solution to this problem?

I'd appreciate any information concerning this or other possible
problems associated with Leonardo -> Altera synthesis flow.

Best regards,

Mark H. Sandstrom
Article: 6384
Subject: Re: Problem in Leonardo synthesis targetting Altera
From: Tim Warland <twarland@nortel.ca>
Date: Tue, 20 May 1997 09:52:45 -0400
Links: << >>  << T >>  << A >>
Mark Sandstrom wrote:
> 
> Hi!
> 
> I'm synthesizing by Leonardo v4.03 to Altera FLEX10K CPLDs.
> If I load and resolve the FLEX10K modgens, the edif produced
> by the write altera -command contains cell referencies to
> "BUF":s.
> 
> The Altera's place and route tool Maxplus2 (v7.2) doesn't
> accept this edif and issues an error message:
> "Error: Can't find design file 'buf'".
> 
<snip>

As a wild ass'd guess (WAG) I'd suggest you check your EDIF
netlist reader settings. I believe you have to point explicitly
to the LMFs in the Leonardo software.

Cheers
Tim Warland
ASIC Engineer

Free Advice - you get what you pay for
-- 
You better be doing something so that in the future
you can look back on "the good old days"

My opinions != Nortel's opinion;  Nortel's Hardware :-)
Article: 6385
Subject: Re: Cadence or World Technology, or other NT vendors...
From: Richard Nuth <nuth@col.hp.com>
Date: Tue, 20 May 1997 08:31:43 -0600
Links: << >>  << T >>  << A >>
John Hesse wrote:
> I need to do a verilog simulation to verify a design--but will not be
> making chips from it. I need a solid development system with a good
> interface (as this will be my first non-toy verilog project).
> The price of $20-25K for Cadence is very steep for the short term
> use: 6-9 months. Ouch.
> 
> BTH, I selected Verilog because I've taken a class on it and it suits the
> design very well (I don't want to learn VHDL :).  Comments on NT Verilog
> products would be appreciated.

John,

I have Simucad's SILOS III installed on my PC at home and find it to be
quite suitable for Verilog simulations.  It runs fine under NT 3.51 and
NT 4.0.  The simulation environment is better integrated than many I
have seen, and you can also run "batch" mode simulations with it.  They
have a demo version of the tool with limited capability, but you can at
least look at the UI this way.

Their WWW page is: http://www.simucad.com

I believe that the price is still less than $4K.

Richard Nuth
nuth@col.hp.com or Nuth@compuserve.com
Article: 6386
Subject: Re: X-BLOX
From: Brad Taylor <brad@gigaops.com>
Date: Tue, 20 May 1997 09:43:42 -0700
Links: << >>  << T >>  << A >>
Kate Meilicke wrote:
> 
> Xilinx isn't dropping the concept of XBLOX.  XBLOX is being replaced by
> a better tool called LogiBLOX in the M1 software.  It works the same way
> as XBLOX except you have to define the bus width.  One of the major
> advantages is faster runtime with LogiBLOX.  The other VHDL and Verilog
> simulation files if you instantiated LogiBLOX components in your HDL.
> 
> Kate
> Xilinx FAE

There is only one problem with LogiBlox. I really hope I wrong here, but
I can't find any way to make a macro in .xnf format. Which means I can't
use it with anything but M1. 
-
Brad
Article: 6387
Subject: Gatefield ???
From: ccwest@ix.netcom.com (Bill Seiler)
Date: Tue, 20 May 1997 21:35:17 GMT
Links: << >>  << T >>  << A >>
Anyone have any experence with Zycad's Gatefield parts.

I'm interested in the new 100K .6 micron parts

Thanks

Bill Seiler
Circuit City / Patapsco West  
3255-4 Scott Blvd, Suite 105
Santa Clara, CA 95054
408 982 5420 Direct
408 982 5430 FAX
ccwest@ix.netcom.com 


Article: 6388
Subject: Re: Cheap way to develop for FPGAs?
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Tue, 20 May 1997 21:58:08 GMT
Links: << >>  << T >>  << A >>
On Tue, 13 May 1997 12:32:25 +0100, Christos Dimitrakakis
<mbge4cd1@afs.mcc.ac.uk> wrote:

>Is there a cheap way to develop for FPGAs, suitable for the enthusiast?

Lucent Technologies have announced a special "Summer deal pricing" (at
least in Europe). It offers:

Workview Office Designer
	Schematics
	Simulation
	VHDL synthesis (limited to 400 registers)
ORCA VISTA place & route software
	Timing driven map, place and route
	Device editor (for macro generation etc.)
	Static timing analysis
	Back annotation to WVOffice above
	Support upto and including the 2C10A

List price is 995 US dollars for the whole lot. This offer valid until
end of August.

(Commercial plug)
Any readers in the UK looking for an improved price can call me:
01256 707107

Stuart Clubb

Article: 6389
Subject: Re: xilinx xblox with capture ver 7.00
From: David Dye <davidd@xilinx.com>
Date: Tue, 20 May 1997 15:04:41 -0700
Links: << >>  << T >>  << A >>
Paul S Secinaro wrote:
> 
> "William E. Lenihan III" <lenihan3we@earthlink.net> writes:
> 
> >XBLOX is being dumped by Xilinx, so avoid it until you know what, if
> >anything, will replace it. Better yet, look into synthesis for those
> >design components that you were thinking of using XBLOX for.
> 
> I would hope that they're moving towards implementing a standard LPM
> library.  Anyone know for sure?
> 
> --
> Paul Secinaro (pss1@christa.unh.edu)
> Synthetic Vision and Pattern Analysis Laboratory
> UNH Dept. of Electrical and Computer Engineering


XBLOX is being upgraded to a tool called LogiBLOX.  This tool will be
part of the M1 toolset that is currently in Pre-release, with the full
release coming this summer.

LogiBLOX is similar to XBLOX in that it will provide custom components
that can be placed in a design, but it has some improvements, including:

- A Graphical User Interface is used to make it very easy to create the
LogiBLOX components.

- LogiBLOX components are compiled when they are created, so there is an
underlying EDIF, VHDL or Verilog model for each component that is
built.  There is no need for programs like XSIMMAKE with M1; they are
ready to simulate when they are built.

A conversion guide is shipped with the M1 software to assist users
upgrading exsiting XBLOX designs to use LogiBLOX.

Watch the Xilinx Web Site (http://www.xilinx.com) for more information
in the near future.

-- 
David Dye
Software Applications Engineer
Xilinx Inc., San Jose, CA
Article: 6390
Subject: Re: FPGA gate counting: No truth in advertising
From: kevintsmith@compuserve.com
Date: Tue, 20 May 1997 16:51:20 -0600
Links: << >>  << T >>  << A >>
In article <337A1935.5570@xilinx.com>,
  jwbrooks@xilinx.com wrote:
>
> kevintsmith@compuserve.com wrote:
>
> Don't believe any vendor on FPGA gates.....
>
> You will be better served by counting Flip-flops, look-up tables( or
> their equivalent), I/Os,
> and RAM bits ( If applicable ). Gate counting is only good between
> FGPAs and/or CPLDs from the same vendor. Like XC4000 vs XC5200...
>
> Routing plays a huge factor in the ability to utilize these "gates".
> The amount you can route will often depent on your design, and speed
> requirements.
>
> "gates" are for ASICs only.....
>
> Good luck.

Sorry, but I disagree.	You CAN believe a couple vendors on FPGA gates.
Part of the above statement is true:  You WILL be better served by
counting Flip-flops, LUTs, I/Os, etc, because these are more directly
mappable to your design (you can be reasonably sure how many flip-flops
you need before you start synthesis or schematic entry).

Routing in the parts determines the ability to utilize these resources
only if the chosen architecture has limited routing resources. There are
two main limitations of routing resources in an FPGA: (1) The logic used
to hook up gates takes up so much silicon area that you can't populate
the die with enough routing to hook up all the gates, or (2) The
resistance of the interconnect is sufficiently large that using too many
will drastically affect the delay through the path, killing your
performance.

QuickLogic provides routing that has neither of these problems.  There is
sufficient routing wire and interconnect to easily hook up the logic
cells and I/Os in a device that has every logic cell used and every I/O
pre-placed.  The low resistance and capacitance of this type of
interconnect give 1,000 times less impedance (RC = 30ohms for QuickLogic
vs. RC=40kohms for Xilinx's SRAM interconnect).

Therefore, you get routing and performance more similar to an ASIC.  You
also get gate counts that are actually achievable!  A 7,000-gate ASIC
design will (really) fit into a 7,000-gate QuickLogic device.  However,
the data sheets provide flip-flop, I/O, and logic cell information so you
can see for yourself.

We don't inflate the die size to allow for all that additional routing,
either.  The link fits neatly between metal layers and is a smaller
diameter than the metal trace it connects.

Check out our webpage at www.quicklogic.com for more information.  I know
the claims sound far-fetched because every FPGA vendor in the past has
made such promises.  In this case, it's not marketing hype, just superior
technology.

Regards,
---
Kevin Smith
QuickLogic FAE
(972) 222-2478
kevintsmith@compuserve.com

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6391
Subject: Engineering Opportunity - http://www.digjobs.com
From: msherman@digjobs.com (M. Sherman)
Date: Wed, 21 May 1997 00:21:36 GMT
Links: << >>  << T >>  << A >>
If you're interested in looking at career opportunities, we're
looking for hardware and software engineers to fill positions for 
PC and semiconductor companies from San Jose to Boston. 

We're looking for engineers who have broad hardware experience (from
ASIC design to PCB design) as well as software engineers (from
low-level embedded systems to Internet developers) .

Our clients are Fortune 100 PC and semiconductor companies
offering very competitive compensation packages, full relocation
benefits, signing bonuses and matched 401K programs.

If you're interested in state-of-the-art technology, please contact me
via fax, phone or email and I'll give you information on the job and
the company. We'll also assist in preparing your resume, providing
cost of living differentials and providing information on companies
currently looking for engineers with your skills.

Look forward to hearing from you.

Regards,
Michael Sherman
msherman@digjobs.com
Digital RESOURCES, Inc.
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Article: 6392
Subject: Aust. SMT PCB Design Course
From: B Olney <info@aedc.com.au>
Date: Wed, 21 May 1997 12:28:41 +1000
Links: << >>  << T >>  << A >>
Advanced Design for SMT  (Right First Time Design)

The two day workshop offered by the Australian Electronics Development
Centre (AEDC) on Advanced Design For SMT presents in detail the tried
and proven generic design rules for dense, double sided SMT design of
multi-layer PCB's. The course material is non-application specific and
the presenter has had extensive experience with many different CAD
systems.

This course is most suited to design personnel who are designing surface
mount boards with more than 4 layers at high clock speeds. However, the
principles taught in this course can be applied to single/double sided
boards using surface mount components. 

Further details of the course are available at URL
http://www.aedc.com.au/ASMT.htm

Course Schedule for June/July 1997

Melbourne       5th & 6th June
Brisbane        16th & 17th June
Sydney          3rd & 4th July

Please see http://www.aedc.com.au for a complete schedule of courses.

___________________________________________________

Barry Olney                   http://www.icd.com.au
Managing Director                       

In-Circuit Design Pty Ltd       Ph: +61 3 9205 9595
VeriBest Solutions Centre       Fax:+61 3 9205 9410
Suite 211, Princess Tower       Mbl:+61 4 1117 0827
1 Princess Street,                              
Kew, VIC 3101, Australia    Email:bolney@icd.com.au
___________________________________________________


Article: 6393
Subject: Re: universal PCI-Interface with FPGA?
From: "Austin Franklin" <dark8room@ix.netcom.com>
Date: 21 May 1997 04:45:23 GMT
Links: << >>  << T >>  << A >>
> After doin some digging, I found the ORCA to be the only one that was
> Fully Compliant. 

I do not believe what you say to be correct.  The Xilinx 4kE series is
fully PCI compliant.

There are three levels of PCI compliance, one is electrical, two is timing
and three is protocol.  The first one either is or isn't, and the X4ke is. 
The second is a matter of levels of logic (design), placement and routing,
and again, the X4ke can do that too.  The third is mostly design (providing
it is designed to make timing...), and that can be made in any part...if
designed correctly.

What about the Xilinx 4kE series do you not believe to be PCI compliant?  I
have done 6 PCI interfaces using Xilinx 4kE parts, and have only had
trouble meeting timing with a burst master (because it uses raw PCI
signals) but with proper design and placement, meeting timing can be done.

I do not use the Xilinx Logicore PCI interface, I have developed my own,
before theirs was available...

Austin Franklin
darkroom@ix.netcom.com

Article: 6394
Subject: Re: VHDL PCI FPGA Implementation
From: "Austin Franklin" <dark8room@ix.netcom.com>
Date: 21 May 1997 05:01:53 GMT
Links: << >>  << T >>  << A >>
> Xilinx's PCI solution:
> 
> Document pcids.pdf page 4 indicates that in burst mode when supplying
> data, the Initiator and targets both supply data to the PCI bus at 50%
> data rate as a wait state insertion is required on every cycle.

That is a design issue, not a chip issue.  I have done master designs that
do not have this problem in a Xilinx 4kE.
 
> I couldn't find any publish VI characteristics data for Xilinx. Is it
> available? Does it meet the PCI spec?

I know the Xilinx 4kE series makes the PCI V/I curve, 'cause I worked with
someone from Xilinx characterizing this.  The data is available in the
Xilnx data book dated 9/96, page 13-9 under the heading "Voltage/Current
Characteristics of XC4000-Family Outputs", and in the A/C specifications
section of the 4kE section.

> The master also has a FIFO etc. etc. 

So do the Xilinx 4kE parts...

The ORCAs are nice parts, but so are the X4kE parts...  I can't vouch for
the ORCA or Altera parts making PCI spec or not...but I can for the Xilinx
4kE.

Austin Franklin
darkroom@ix.netcom.com

Article: 6395
Subject: Re: Problem in Leonardo synthesis targetting Altera
From: Mark Sandstrom <Mark.Sandstrom@martis.fi>
Date: Wed, 21 May 1997 09:31:37 +0300
Links: << >>  << T >>  << A >>
Tim Warland wrote:
> 
> Mark Sandstrom wrote:
> >
> > Hi!
> >
> > I'm synthesizing by Leonardo v4.03 to Altera FLEX10K CPLDs.
> > If I load and resolve the FLEX10K modgens, the edif produced
> > by the write altera -command contains cell referencies to
> > "BUF":s.
> >
> > The Altera's place and route tool Maxplus2 (v7.2) doesn't
> > accept this edif and issues an error message:
> > "Error: Can't find design file 'buf'".
> >
> <snip>
> 
> As a wild ass'd guess (WAG) I'd suggest you check your EDIF
> netlist reader settings. I believe you have to point explicitly
> to the LMFs in the Leonardo software.

My "EDIF Netlist Reader Settings" in Maxplus2 is "Exemplar". 

> 
> Cheers
> Tim Warland
> ASIC Engineer
> 
> Free Advice - you get what you pay for
> --
> You better be doing something so that in the future
> you can look back on "the good old days"
> 
> My opinions != Nortel's opinion;  Nortel's Hardware :-)
Article: 6396
Subject: Re: Problem in Leonardo synthesis targetting Altera
From: Duncan Davis <duncan.davis@gecm.com>
Date: 21 May 1997 07:27:09 GMT
Links: << >>  << T >>  << A >>

This sounds similar to a problem we had with inputting Leonardo EDIF into 
MAXPLUS2. To solve it we had to play around with the Library Mapping File 
(LMF) options within MAXPLUS2. 

I think MAXPLUS2 has several 'default' type options. None of these 
defaults seemed to work and we eventually found an LMF buried somewhere in 
the LEONARDO software. I can't remember exactly where it was buried but 
once MAXPLUS2 was pointing to it we were able to proceed with place and 
route no problem.

Hope this helps


Duncan

-- 
============================================================
Duncan Davis                           | 
Senior Development Engineer            | Opinions expressed
GMRDS, SilverKnowes , Edinburgh, UK    | are my own, not
duncan.davis@gecm.com                  | necessarily those 
DIRECT 0131 343 5906 GNET 72 709 5906  | of my employer
============================================================


Article: 6397
Subject: Re: Fast comparator
From: David Moloney <dave@ssd.ie>
Date: Wed, 21 May 1997 10:31:01 +0100
Links: << >>  << T >>  << A >>
I have used a fast comparator proposed in


"Evaluation of A+B = K Conditions without carry propagation"
J. Cortadella and J. Llaberia
IEEE Transactions on Computers, vol 41, no.11, Nov 1992, pp 1484-1488


The verilog code for a 10-bit K=0 case is:


module cmp_pg10(zero,a,b);

  output       zero;
  input  [9:0] a;
  input  [9:0] b;

  wire   [9:0] p;
  wire   [9:0] g;
  wire   [9:0] y;

  /* propagate & generate logic */
  assign g    = a&b;
  assign p    = a|b;

  /* iterative comparator according to Cortadella & Llaberia */
  assign x    = a^b;
  assign y    = x^{p[8:0],1'b0};

  /* multi-bit OR gate to perform zero-detection */
  assign zero = ~(|y);

endmodule /* cmp_pg10() */


This comparator will detect for instance if a-b = 0 if b
is inverted and 1 is added to convert it to a twos complement
negative number.


- David


Svenn-Ivar wrote:
> 
> I've been thinking of using an FPGA as a trigger circuit in a (not so
> high-end) digital scope. Functions I need are high speed comparison of
> two 10-bit digital values against each other and against predetermined
> values. Output would be an indication if to trig or not.
> I'm not familiar to FPGA's or other 'programmable logic' so I would like
> to know if this is possible to do, before I go any further. With high
> speed I mean about 10ns from value input to indication output.
> Suggestions are highly appreciated!
> 
> ----------------------------------------
> Svenn-Ivar Svendsen, Student
> Dept. of Electrical Engeneering
> sis@hekta.iet.hist.no
> http://hekta.iet.hist.no/~sis
Article: 6398
Subject: Re: FPGA technology: No truth in MARKETING
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 21 May 1997 10:10:39 GMT
Links: << >>  << T >>  << A >>

I've seen some pretty stupid B*L@ S#I& in my reading of posts in various
news groups, but this one belongs in alt.conspiracy.not.thinking.clearly

Kevintsmith (Of Quicklogic) responds to jwbrooks (Of Xilinx)

Most of article deleted to conserve electrons

>(Kevintsmith)
>Sorry, but I disagree.	You CAN believe a couple vendors on FPGA gates.
>Part of the above statement is true:  You WILL be better served by
>counting Flip-flops, LUTs, I/Os, etc, because these are more directly
>mappable to your design (you can be reasonably sure how many flip-flops
>you need before you start synthesis or schematic entry).

So far so good

>Routing in the parts determines the ability to utilize these resources
>only if the chosen architecture has limited routing resources. There are
>two main limitations of routing resources in an FPGA: (1) The logic used
>to hook up gates takes up so much silicon area that you can't populate
>the die with enough routing to hook up all the gates, or (2) The
>resistance of the interconnect is sufficiently large that using too many
>will drastically affect the delay through the path, killing your
>performance.

Holding my breath now, because I KNOW what's comming ...

>
>QuickLogic provides routing that has neither of these problems.

Didn't have to hold my breath very long.

If Quicklogic doesn't have these problems (in particular (1)), then why
does Altera have the 10K100, Xilinx has the 4085XL, Lucent has 2C40,
(which allowing for gate discounts, all have available gates somewhere
between 30K and 100K, depending on how you use it and how much on-chip RAM
you use), and the biggest QL part I've heard of is less than 10K gates 
(and no on chip RAM).

Part of the answer is the silicon technology used, but part is the great 
secret of the antifuse crowd. Yes the antifuses are small (much smaller
than the configuration SRAM cells in other FPGAs, but to blow these 
fuses, you need BIG power transistors on either side to source and sink 
the programming current. When did you last hear an antifuse vendor talk 
about those transistors, the area they take up, and the capacitive load 
they leave on each net when they aren't being used to program the fuses.


>  There is
>sufficient routing wire and interconnect to easily hook up the logic
>cells and I/Os in a device that has every logic cell used and every I/O
>pre-placed.  The low resistance and capacitance of this type of
>interconnect give 1,000 times less impedance (RC = 30ohms for QuickLogic
>vs. RC=40kohms for Xilinx's SRAM interconnect).

Normally I would have just left this post go by, but the above is what 
really set me off. ( As those who have seen me post before, you are 
probably aware that I am not a highly opinionated person, and am only too 
happy to let bygones be bygones )

Let's see now .... the antifuse devices have these 30ohm links, and an
unmentioned pair of power transistors associated with either side of the
fuse (yes, I know that these transistors can be shared by multiple
antifuses, so the total number is FAR smaller than the number of
antifuses). 

The pass transistor of the SRAM FPGA is 40Kohms (according to Kevin), and 
is therefore 1000 times worse. If this were true, then it would be 
reasonable to expect the SRAM devices to be 1000 times slower. Last time
I looked, muxes were often built out of pass transistors, just like the
the muxes that make up the logic section of the QL devices. Are these also
40K ohms?

Well, as it turns out, 40K is off by a little. The correct number is 
probably around 100 to 200 ohms. Both for SRAM FPGA pass transistors, and 
the pass transistors that are used in muxes, and every where else to 
implement gates and flipflops, etc. (In the I/O, they are much lower 
resistance).

The antifuses do have lower resistance than small pass transistors, but 
some (but maybe not all) of this gain is lost because of the programming 
transistors.


Should I think about editing this article, or just post it ???

I'll post it. 

Philip Freidin


Article: 6399
Subject: Re: X-BLOX
From: Kate Meilicke <kate.meilicke@xilinx.com>
Date: Wed, 21 May 1997 09:44:06 -0400
Links: << >>  << T >>  << A >>
> I really hope I wrong here, but
> I can't find any way to make a macro in .xnf format. 

That is right.  LogiBLOX is only for M1.

Kate


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