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Sorry if this is ask before, I'm new to this group. I'm currently a student and am interested to know which is better. Especially for the application to PCI,ISA connections. Thanks & Regards, JereminArticle: 6501
>Thankyou Len, I was beginning to think that I was the only one who >thinks of synthesis as meaning VHDL or Verilog, rather than hooking a >bunch of symbols together in a drawing package. VHDK and Verilog are not the ONLY forms of logic synthesis available. I believe that the current base Foundation software package includes ABLE synthesis, and ACTIVE-CAD schematic ccapture, with functional and timing simulation. I don't know if the version sold with the APS kit contains this or not, but the copy I just bought does, and I only paid $99 for it. Oh BTW, it goes to 8000 gates, which will support a pretty complex design.Article: 6502
>The gate is never used in isolation. Skew between the input >signals to the CLB can cause the glitching described by the >(more) original poster. How do you guarantee that there is >no skew between the input signals (or so little that it doesn't >matter)? In the case of Xilinx LCAs, it can (pragmatically) be >done by placing the sources of the input signals right next to >the 'NAND' gate, and carefully verifying (with the design editor >or timing analyzor) that the delays from these sources to/thru >the gate are small and matched. Does this guarantee absence of >glitches? I don't know. I would not rely on this, as I think you basically say. Given the unpredictable nature of FPGA interconnect, one cannot guarantee anything much about relative propagation delays of signals. I suppose the only situation in which my last post is relevant is when only one input is changing. THEN there should be no glitches at the gate output. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 6503
On 22 May 1997 16:44:44 GMT, "Austin Franklin" <dark8room@ix.netcom.com> wrote: >The design I 'use' does not have this problem for target or master... ;-) Sorry Austin, I should have responded faster. I bow to your superior engineering skills (to Xilinx). Have they offered you money yet? I therefore summarise my comments to: Lucent is fully PCI compliant. Xilinx is fully PCI compliant, if you redesign the core they sell you. Altera is not PCI compliant. Deathly silence from 2610 Orchard Parkway. Hmm, maybe I should put a press release out... StuartArticle: 6504
On Mon, 26 May 1997 20:47:42 GMT, stuart.summerville@practel.com.au (Stuart Summerville) wrote: >Hi all, > >I have a 208pin PQFP fpga (0.5mm pitch) on a board. I am having >problems with pin connections to the board. Attempting to re-heat the >solder to make a clean connection seems to create problems with >surrounding pins - it doesn't take much to get a minute solder bridge >between two pins. > >Two questions: > >1) Do any of you find such packages tend to come in with such >connection problems? > >2) What is the feeling about attempting to re-solder such pins if a >connection seems to be flakey? Am I wasting my time trying to fix it? >Maybe if some pins have flakey connections then others on the same >chip are likely to (eg. if some are bent down too much, then obviously >the others are at a different level...). > It's a real bugger Apparantly you can get soldering iron adaptors which have a sphere on the end which makes the solder pearl thus preventing shorts. I've never seen one but everybody who has thinks it's the best thing since sliced white. Check Weller and Ersa maby they can help. Anything else is a mess. >--------------------------------------------- >Stuart Summerville >Project Engineer >Practel International >442 Torrens Road, Kilkenny, SA 5009 >Tel: (61.8) 8268 2196 Fax: (61.8) 8268 2882 >Email: stuart.summerville@practel.com.au >--------------------------------------------- Hans htd-ibhd@remove.this.t-online.de Life is hard, life is earnest And our hearts though young and brave Softly, like muffled drums a beating Funeral marches to the grave.Article: 6505
95486158j wrote: > > timolmst@cyberramp.net wrote: > > > > >Thankyou Len, I was beginning to think that I was the only one who > > >thinks of synthesis as meaning VHDL or Verilog, rather than hooking a > > >bunch of symbols together in a drawing package. > > > > VHDK and Verilog are not the ONLY forms of logic synthesis available. > > I believe that the current base Foundation software package includes > > ABLE synthesis, and ACTIVE-CAD schematic ccapture, with functional and > > timing simulation. I don't know if the version sold with the APS kit > > contains this or not, but the copy I just bought does, and I only paid > > $99 for it. Oh BTW, it goes to 8000 gates, which will support a pretty > > complex design. > > Where and how to order the $99 package?? > > -- > Yau Man Wai , Roger > Higher Diploma in Electronic Engineering Year 2 > Department of Electronic Engineering > The Hong Kong Polytechnic University > http://www.acad.polyu.edu.hk/~95486158j These packages will be student editions of the Foundation software, available only with student ID. Also keep in mind the kit has: No Xchecker Download Cables No VHDL No maintenance No test boards No 5200 series support No M1 path (new router) Gate limit of 4008 The student kit is ok for students and a great idea by XILINX, but for serious applications and supported software and hardware, I would check out the prices and suppport at http://www.erols.com/aaps. These kits include VHDL and gate densitities to 30,000 gates currently.Article: 6506
| I seem to remember that a LUT is glitches only for single input
^^^^^^^^
glitchless
| transitions.
|
My apologies. I hit the accept button on the spell checker a little too
quickly.
| --
| Steven Knapp
| OptiMagic(tm) Logic Design Solutions
| E-mail: sknapp @ optimagic.com
| Programmable Logic Jump Station: http://www.netcom.com/~optmagic
|
Article: 6507timolmst@cyberramp.net wrote: > > >Thankyou Len, I was beginning to think that I was the only one who > >thinks of synthesis as meaning VHDL or Verilog, rather than hooking a > >bunch of symbols together in a drawing package. > > VHDK and Verilog are not the ONLY forms of logic synthesis available. > I believe that the current base Foundation software package includes > ABLE synthesis, and ACTIVE-CAD schematic ccapture, with functional and > timing simulation. I don't know if the version sold with the APS kit > contains this or not, but the copy I just bought does, and I only paid > $99 for it. Oh BTW, it goes to 8000 gates, which will support a pretty > complex design. Where and how to order the $99 package?? -- Yau Man Wai , Roger Higher Diploma in Electronic Engineering Year 2 Department of Electronic Engineering The Hong Kong Polytechnic University http://www.acad.polyu.edu.hk/~95486158jArticle: 6508
I am new to this area. Can any point out a FAQ or any suitable site on the web where someone like me can find information? -- ----------- Henry Fernandes (hff135@cs.usask.ca) http://www.cs.usask.ca/homepages/grads/hff135/index.html - Glory Glory Man UnitedArticle: 6509
Kate Meilicke wrote: > > Xilinx is switching from XNF to EDIF in the M1 software. The current > version of M1 still supports the XNF format. This includes XNF, XTF (A > flattened XNF file generated after XBLOX and XNFPREP in the XACT > 6.0.1/5.2.1 software) and SXNF (Synopsys XNF). > > Kate Meilicke > Xilinx FAE Kate: So, is it true to say that new, non-legacy designs done in M1 will involve EDIF files only, but if you are doing something special involving importing older designs into the M1 toolset, then the XNF file format might come into play? Under what circumstances would the M1 tool want to use XNF? Also, would the M1 tools like to see SEDIF files from Synopsys rather than SXNF? Bill Lenihan Hughes Aircraft wlenihan@ccgate.hac.comArticle: 6510
Ahhhh.. But if you have seen the news lately you'll notice the Altera
IS fully PCI compliant. The've just released a core product.
Regards,
Aaron Quantz \^ ^/
)@ @(
+---------------------------oOO--(_)------------------------------------+
+ Mgr Software Development, Turret Control Systems +
+ HR Textron | Phone: (805) 253-5471 +
+ 25200 W. Rye Canyon Rd. | Fax: (805) 253-5962 +
+ Valencia, CA USA 91355-1265 | Email: aquantz@ibm.net +
+ Visit the Textron web site: http://www.textron.com +
+-----------------------------------Oooo--oOO---------------------------+
oooO ( )
( ) ) /
\ ( (_/
\_)
Article: 6511
Could the convener of comp.arch.fpga please e-mail me? We are starting a
Web-based newsgroup in which you may be interested.
rcj
____________________________________________
"Brains aren't computers, they're cognizers"
rcj@cognizer.com (R. Colin Johnson)
____________________________________________
Smart Technology Editor, EE Times
Editorial Advisor, Intl.J.of Neurocomputing
Snailmail: 10075 SW Barbur. Blvd, Bldg.5
M/S 405, Portland, Ore. 97219
Voice: 503/246-6464 Fax/293-1736
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WEB SITES
Smart Technologies SIG: www.eet.com/smart
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Article: 6512Free Adult Internet Connection Worldwide Via Our Bbs. Follow the link and enjoy... http://cybercity.hko.net/la/interbbs/freenet/free.htmArticle: 6513
=====>Larice@vidisys.ccn.de (Larice Robert) wrote: [snip] #>leonardo is the most expensive of these tools (aprox 16000$). But in my #>opinion its capabilities go far beyond what you can do with the other tools. #>Due to Price, and due to our inexperience concerning HDL tools our decision #>around Jan 97 was to go for synplicity. At the very last moment Exemplar #>announced Linux support for Leonardo, and I investigated a demo installation #>of Leonardo. I was such impressed that we have bought it around April. #>Note: #> The leonardo Price for Linux is the same as for Windows. #> The Price for Sun and HPUX is aprox twice as high. #> So with Linux you can use this tool on a full fledged Unix #> (on a cheap intel based PC) for the same price as the Windows version. #>around Jan 97 was to go for synplicity. At the very last moment Exemplar #>announced Linux support for Leonardo, and I investigated a demo installation #>of Leonardo. I was such impressed that we have bought it around April. #>Note: #> The leonardo Price for Linux is the same as for Windows. #> The Price for Sun and HPUX is aprox twice as high. #> So with Linux you can use this tool on a full fledged Unix #> (on a cheap intel based PC) for the same price as the Windows version. #>Larice Thanks for the informative reply, I appreciate it tremendously. This has helped me get a good perspective. good luck on your new upgrade. I'll remember to ask you for some pointers. Daniel +_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_ Robotics website http://www.euronet.nl/users/ragman/robotics.html Email work : daniel@betronic.nl Email home : ragman@euronet.nl Smail: Oud Wulvenlaan 35-2, 3523XS Utrecht, Netherlands,Europe WWW: http://www.euronet.nl/users/ragman Back home: Margate, Florida Hometown : Elmont, New York ...exploring cyberspace before it runs out of space... +_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_Article: 6514
On Thu, 29 May 1997 20:29:00 GMT, aquantz@ibm.net (Aaron Quantz) wrote: >Ahhhh.. But if you have seen the news lately you'll notice the Altera >IS fully PCI compliant. The've just released a core product. If by a core product you mean the pci_a megacore function, then I am sorry, but I have to disagree. At: http://www.altera.com/html/products/mc-pci_a.html#comp They state compliance with REV2.1, yet list just 3 base parameters clk2q, setup, and 33MHz clock. I have seen no electrical checklist with a nice row of tick boxes. Read the documentation, it's only a megabyte of pdf. Then read the PCI spec. and compare. I refer you again to page 6 of dsdma_01.pdf from the literature section. Altera say they have two pins on three different PCI signals. The two pin approach undoubtedly breaks the spec of 10pF maximum load on a pin. The Altera solution gives a maximum 20pF, so they fail. Another spec requirement is for the clock pin to have sub 12 pF, Altera is listed as maximum 15pF. Fail again Altera is not compliant. Of course they could change their specifications, like they did with the EAB, that would be up to them. Until they do, and ship guaranteed product, the pci_a core cannot claim to be compliant. Of course, it_probably_works, but so does a 6 nS SRAM in a 5 nS design requirement, MOST OF THE TIME. Those who would choose to follow such dubious engineering practices do so at their own, and company's, risk. Anyone want to disagree? Still silence from the boys in blue. StuartArticle: 6515
It may the the intention of Xilinx to move away from XNF in the future. However, as someone who is using M1 in conjuction with Exemplar's Leonardo synthesis tool, XNF is the only method of getting the synthesized design from Leonardo into M1. This is because the current release of Leonardo produces EDIF that is incompatable with M1. Leonardo is due to be 'fixed' in release 4.1 which I think is due from release some time around July '97. Regards Barry ================================================================== Barry T. Paterson : Views expressed are my Senior Development Engineer : own and not those of GEC. GEC Marconi Avionics : Edinburgh : Scotland UKArticle: 6516
Hi
In a new design I use a Xilinx 5215-5 with a BG 352 package.
Now my PCB is done and since 2 months I am waiting for this device,
and I am still waiting news from my French #$%^&@ dealer.
So if you can help me to find as soon as possible 5 pieces at first
of this chip it will realy help me.
Thanks.
Thierry
thierry.bogey@cern.ch
Article: 6517Hi, I need some documentation sites on FPGAs, their uses, advantages etc. Can anyone provide a resourceful URL? Thanks, Venkat.Article: 6518
Henry F Fernandes (hff135@skorpio3.usask.ca) wrote: : I am new to this area. Can any point out a FAQ or any suitable site on the : web where someone like me can find information? Try: http://www.mrc.uidaho.edu/fpga/fpga.html I too was on the lookout for some documentation, but the tutorial on this site should help you get started. Venkat.Article: 6519
Reconfigurable Computing Enthusiasts,
I would like to solicit preliminary input on the following (draft) proposal
for creating a newsgroup devoted to reconfigurable computing.
As you may know, the original charter for Comp.arch.fpga intended
this newsgroup as a discussion place for reconfigurable computing.
(See ftp://ftp.uu.net/usenet/news.announce.newgroups/comp/comp.arch.fpga)
At that time, Comp.arch.fpga was deemed the most appropriate name
for such a newsgroup.
At this time, I think it's worthwhile to consider creating a new newsgroup
devoted to reconfigurable computing, leaving Comp.arch.fpga to serve in
its current (very useful) role. If you're intersted in reconfigurable
computing, please read the draft proposal below.
In order to keep the discussion open to everyone, please post any
comments to Comp.arch.fpga
Thanks,
--Mike Alexander
*-----------------------------------------------------------------------------*
| (Draft RFD also at http://www.eecs.wsu.edu/~alexande/draft_rfd.html) |
*-----------------------------------------------------------------------------*
===============================================================================
(DRAFT) REQUEST FOR DISCUSSION
Group Name: comp.arch.rpu
Status: unmoderated
Distribution: world wide
Summary: Discussions related to reconfigurable computing systems
Proposed by: Michael J. Alexander (alexander@eecs.wsu.edu)
This is a formal Request For Discussion (RFD) on the creation of an
unmoderated newsgroup, comp.arch.rpu
CHARTER
The proposed unmoderated newsgroup Comp.arch.rpu will be open
to discussions on topics related to reconfigurable computing,
which can be described as the practice of using in-system-reconfigurable
processing units (RPU) to accelerate operations in general-purpose computing.
Appropriate topics include, but are not limited to, programming tools,
languages and systems that support dynamic configuration; reconfigurable
processing architectures and RPUs, both commercial and research; and
applications of reconfigurable computing.
RATIONALE
Reconfigurable computing is an emerging field that represents a significant
departure from traditional computing models (e.g., von Neuman). Although
many of these systems use FPGAs, reconfigurable computing systems represent
an important new computing paradigm, making such discussions less and less
appropriate for Comp.arch.fpga, which is largely focused on CAD tools and
issues pertinant to traditional static FPGA designs (e.g., ASICs, glue logic).
Until quite recently, reconfigurable computing has meant computing systems
built from FPGA devices. However, a new generation of FPGA-like devices,
which are often called reconfigurable processing units (RPU), support
key features such as partial fast reconfiguration. RPUs enable a new
computing paradigm based on ``virtual hardware'', where application-specific
hardware is time-multiplexed on the RPU in order to meet adaptive computing
requirements. Reconfigurable computing systems are hardware/software systems
in which hardware functionality is not fixed a priori, but rather is tailored
at runtime to meet application computational requirements.
It appears from its charter that Comp.arch.fpga was intended to be a
vehicle for discussing FPGA-based computational engines and systems such as
those that have appeared at the IEEE workshops FCCM 93-97. Discussions
on Comp.arch.fpga focus largely on the use of FPGA CAD tools and design
techniques, which are extremely useful to the general, larger FPGA-design
community. Rather than ``reclaim'' Comp.arch.fpga as the proper domain
to discuss reconfigurable computing, it would be most beneficial to allow
Comp.arch.fpga to maintain its current function (as the proper discussion
place for FPGAs) and introduce a new group, Comp.arch.rpu, devoted
to discussing the use of reconfigurable processing units.
===============================================================================
Article: 6520John Lundgren wrote: > > Bharat Kurani (Bharat.Kurani@add.ssw.abbott.com) wrote: > : I need address/phone/fax list of all semiconductor companines > You can find a number of semiconductor companies on the Web, have a look at one of our pages, http://www.itutech.com/semi.htm. ------------------------------------------------------------------------ Chris Sakkas (chris@itutech.com) ftp://itutech.com ITU Technologies (sales@itutech.com) http://www.itutech.com See our web page for PIC development tools and Caller ID->RS-232 products! VISA/MasterCard/AE accepted Phone:(513)661-7523 FAX:(513)661-7534 Toll Free Order Line: 1-888-4-ITU-TECHArticle: 6521
Ole Christian Midtbust wrote: > > I have to interface a marine electronic device (GPS) with a superior system. The question > is if the NMEA standard 2.0 has a HW restriction when it comes to stretch, or is it > just a SW protocol?. > I'm using RS 422, RS 232 and RS 485. Rs 232 is used in connection to > an INT 803 interface with current loop. > > e-mail: ole-christian.midtbust@norcontrol.no > > Best regards > > Ole Chr. > According to my copy of the 2.0 specification, RS-422 is given as a minimum requirement (I've used RS-232 with my GPS), but gives no further restrictions on the hardware. It is primarily a software spec. Good luck, and let me know if you have further questions. Matt Smith -- |-----------------------------------------------------------| | Matthew S. Smith -- Design Engineer | | | | Opinions expressed are mine, but may be shared by others. | | | | Custom Circuits -- Engineering Consulting Services. | | Microprocessor-based solutions to real-world problems. | | Visit http://www.tnrealestate.com/cc for details. | |-----------------------------------------------------------|Article: 6522
Bharat,
Check out this page for phone/fax numbers of semiconductor companies.
http://www.mindspring.com/%7Ethe1/semi.html
Roger McBride
Article: 6523Dear Mr Kayvon Irani 30.05.97 Sorry that I forgot to mention, that I have no access to the flash. I thought this was obvious by the question. Nobody out there to have an answer? Jimmy D.Article: 6524
Is it possible? Jimmy D.
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Compare FPGA features and resources
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