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Messages from 11550

Article: 11550
Subject: Re: vector product minimization problem
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 22 Aug 1998 15:34:19 -0400
Links: << >>  << T >>  << A >>
Stanley Chow wrote:
> 
> In article <35DCA3C7.9A810F57@visicom.com>,
> John L. Smith <jsmith@visicom.com> wrote:
> >> z=x6 + x7
> >> y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)
> >>
> >> Can you get less than 11?
> >
> >I don't think so Dan, add up the number of 1-bits (or 0-bits +1 if this isless) in
> >the co-efficients, then subtract 1 (because you always start with
> >one):
> >
> >coef:               1 2 3 4 5 6 7 8
> >#of adds(or subs):  1 1 2 1 2 2 2 1  -> Total-1 = 11
> 
> This is not a true lower bound.
> 
> It is possible for a single addition to produce two bit, for exmaple:
> 
>    x = a+b
>    y = 2x + x   = 3a+3b
>    z = 4y + y   = 15a + 15b
> 
> In three additions, the result has 8 one-bits.

Stanley,

No, this is not a lower bound. Also John's calculation is wrong. He
shows 2 bits set in the coefficient 7. It should be three bits giving a
total of 13 bits with 12 adders. But this gives you the upper bound
actually. 

In order to use fewer adders, you need to take advantage of common bits
in the coefficients. The above exaple takes advantage of the 2 and the 4
bits common to both the 6 and the 7 coefficients. This is shown in the
expression z = x6 + x7. This allows the result of this addition to be
used in two places from the original expression eliminating one adder. 

That is also what you have shown in your example where you have
eliminated 4 adders by using this process twice. 

I think that you can see this by expressing each product as a sum of the
products of the binary coefficients and the variable. Then find an
optimal grouping of coefficients that eliminates additions. Of course
this is not an algorithm. But I think this is the mathmatical basis for
finding one. You need to search this space for optimal groupings. 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 11551
Subject: Re: half full flag in a xilinx async fifo?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 22 Aug 1998 15:50:02 -0400
Links: << >>  << T >>  << A >>
Dan Kuechle wrote:
> 
> Anybody out there got a good solution for a half full flag for a fifo?  I
> was planning on using Xilinx sync dual port ram to get a 16 deep fifo.  The
> write clk and read clk are app the same frequency (~53 mhz) but are from 2
> different xtal sources so are async to each other.
> 
> My fifo basics are rusty...I've always used a full u/d counter to do this
> in the past, but can't with this design due to the different clocks.  I
> know that when the read pointer = the write pointer the fifo is either full
> or empty, but don't know what relationship indicates half full.  Could
> someone help me out?  The flag does not need to be exact, and I can re-sync
> to eliminate any glitches.  Even a false half full indication would not
> cause a problem as long as it happens right around the half full point.
> 
> Thanks
>    Dan

There seems to be no shortage of answers to this question. I just
designed such a circuit. However I took advantage of the fact that I was
not using the FIFO at full speed. My clock is 33 MHz (could be faster)
but the write data only arrives at 160 ns intervals. The read output has
to be full speed. So I ran the entire FIFO circuit off of the read clock
and simply(?) synchonized the write request signal to the read clock.
This worked very well and was very simple. 

I got the half full flag by using three counters. The read and write
counters are 4 bit up counters. The data counter is up/down with enough
control logic to handle the simultaneous read/write case (hold count). I
can't remember is I made the data counter 5 bits or just 4 bits. 5 bits
are needed to indicate the full 0 to 16 range. Of course half full is
when this counter is at 8 (or greater). 

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 11552
Subject: Re: professional autorouters
From: "Chr. Moecking" <uCon_electronics@csi.com>
Date: Sun, 23 Aug 1998 00:26:24 +0200
Links: << >>  << T >>  << A >>
Hi Michael,

you wrote:
>My question is: What autorouter do you use and recommend? Should we
>switch to a totally different environment
>with integrated placer and autorouter or is there a really good
>autorouter which can read our Protel design files?

I've never found a better autorouter than my brain and my hands, so
you better make it manually.

Regards, Chr. Moecking
Engineering Office Moecking
Am Wasserbau 7
D-72144 Dusslingen
Germany
Article: 11553
Subject: Re: vector product minimization problem
From: benyamin@my-dejanews.com
Date: Sun, 23 Aug 1998 00:44:55 GMT
Links: << >>  << T >>  << A >>

> Calculating 11*A + 13+B would mean K=2, L=4, or that no more than 3 additions
> are required.  I do not see how this could be done.  Does your upper limit
> equation assume subtraction is permitted?
>
> Patrick Kling
>
Yes, the lower bound of .5*KL-1 I proposed may indeed be faulty, becuase I
don't think 11*A + 13*B can be done in less than 4 adds *or* subtracts.

My original thinking is that the worst case is a complete binary tree of size
K- 1.  Since we are "repeating" the tree for L bitplanes, a complete tree
would then be of size KL-1.  Performing additions on every leaf of the tree
corresponds to all 1's in the coefficient bit vectors, such numbers being a
power of 2 minus 1.

However, *possibly* the following may be true, although I haven't totally
figured it out.  Adding the ones is equivalent to adding the zero's of the
inverted data, thus the worse case is not all 1's, but half 1's and half 0's;
this case would make two bit vectors orthogonal, and no common subexpressions
exist.  Hence the .5 the in upper bound.

The scheme would work something like this:  For the sake of example let A=8
and B=9.  11*8 + 13*9 = 205 = 11001101.  Flip the bit vectors of 11 and 13 to
get 4 and 2 respectively (thus, it's not 2's complement!).  Then, the
computation becomes 4*A + 2*B, which is nicely done with one adder.  You then
take the result and invert it and add another term C.  Thus, 4*8 + 2*9 = 50 =
0110010, when inverted = 1001101 + C.

C is a function of A and B, but since we have hacked up the numbers and not
taken proper binary negatives, I am not quite sure how to express C for
arbitrary problems.  I believe there is some truth to this since in our
example above C is a clean 2^7.  Now if C can be expressed in 1 or 2 adds,
then we meet the bound of 3.

I have not thought about it much, so this may all be garbage, and I should
come up with a more conservative bound!!

Any thoughts?
Dan
benyamin@ucla.edu

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 11554
Subject: Looking for info on modified booth
From: Steve Martindell <s-martindell@__nospammm__ti.com>
Date: Sun, 23 Aug 1998 17:31:40 -0500
Links: << >>  << T >>  << A >>
Currently using modified-booth multiply algorithm that reduces
the numbers of add and shifts by 2X. Is there a version that reduces
the number of add and shifts by a higher amount say 3X or 4X?
All the literature I've seen only discusses the 2X version.
I' not interested in CSD versions.
   thanks,
      steve martindell
      s-martindell@_nospamm_ti.com


Article: 11555
Subject: ASIC, FPGA, DSP USA jobs (and work visa)
From: garynlang@aol.com (Garynlang)
Date: 23 Aug 1998 23:56:02 GMT
Links: << >>  << T >>  << A >>
We received so many good resumes from this 
news group people. We are working on them
and we will place them in southern California.

But we still have more openings for good people.
If you are good in ASIC, FPGA, DSP and related 
areas please contact us, we bring you in US.
(Does anyone know an RPG-400 programmer.
We need AS400 people as well.)
RF engineers? Just give us an EMAIL.
Gary
Gary N. Lang
Vice President of ACD,Inc.
E-mail: garynlang@aol.com
Fax:  1-949-362-8046 (USA)
Article: 11556
Subject: New Evolutionary Electronics Book
From: adrianth@cogs.susx.ac.uk (Adrian Thompson)
Date: 24 Aug 1998 02:28:59 GMT
Links: << >>  << T >>  << A >>
Book Announcement:
~~~~~~~~~~~~~~~~~~
Hardware Evolution: Automatic Design of Electronic Circuits in Reconfigurable
Hardware by Artificial Evolution.

Adrian Thompson,
University of Sussex, UK.
http://www.cogs.susx.ac.uk/users/adrianth/

Summary
^^^^^^^
In reconfigurable hardware, the behaviours and interconnections of the
constituent electronic primitives can be repeatedly changed. Artificial
evolution can automatically derive a configuration causing the system to
exhibit a pre-specified desired behaviour. A circuit's evolutionary fitness is
given according to its behaviour when physically instantiated as a hardware
configuration: `intrinsic' hardware evolution.

There is no distinction between design and implementation, nor are design
abstractions used: evolution proceeds by taking account of changes in the
overall physical behaviour of the system when variations are made to its
internal structure. This contrasts with top-down design methodologies, where
hardware details are mainly considered only in the final stages. It would be
infeasible for conventional methods to consider all of the semiconductor
physics of the components and their interactions at all stages of the design
process, but this is the essence of intrinsic hardware evolution.

After removing the constraints on circuit structure and dynamics normally
needed to permit design abstractions, evolution explores beyond the scope of
conventional design into the entire repertoire of behaviours that the physical
hardware can manifest. A series of experiments is used to explore the
practicalities, culminating in a simple but non-trivial application. The
circuits may seem bizarre, but are highly efficient in their use of silicon.
The experiments include the first intrinsically evolved hardware for robot
control, and the first intrinsic evolution of the configuration of a
Field-Programmable Gate Array (FPGA). There is great potential for real-world
applications: some hurdles remain, but a promising solution is proposed.

It is also shown that effects arising from evolutionary population dynamics
can exert an influence towards compact circuits, or give some degree of
fault-tolerance. Additionally, fault-tolerance requirements can be
incorporated into fitness criteria. Evolved fault-tolerance is integrated into
the way the system operates, rather than explicitly relying on spare parts
(redundancy).

Ordering Information
^^^^^^^^^^^^^^^^^^^^
Springer-Verlag, 1988.
Distinguished Dissertations Series
ISBN 3-540-76253-1
http://www.springer.co.uk/comp/books/distinguished.html
email: postmaster@svl.co.uk
Article: 11557
Subject: Paul Donachs Thesis
From: Cm Heong <r24558@email.sps.mot.com>
Date: Mon, 24 Aug 1998 16:12:11 +0800
Links: << >>  << T >>  << A >>
Anyone knows how I can get a copy of Paul Donach's PhD thesis?

The 1996 URL  posted here http://www.cs.qub.ac.uk/~P.Donachy/thesis/  no
longer works.

Thanks,

C M Heong
Motorola Semiconductor
Seremban, Malaysia
r24558@email.sps.mot.com


Article: 11558
Subject: Re: Altera FLEX10K ClockLock/ClockBoost ?
From: Jamie Lokier <spamfilter.aug1998@tantalophile.demon.co.uk>
Date: 24 Aug 1998 11:06:58 +0100
Links: << >>  << T >>  << A >>
Nicolas Matringe <nicolas@dot.com.fr> writes:
> Someone from Altera told me that it was only available with the 10K100DX
> I'm quite surprised because it's not mentionned anywhere in the databook

It is mentioned in the on line documentation with Maxplus2 though.

-- Jamie
Article: 11559
Subject: Re: Data I/O Chiplab and NT
From: Jamie Lokier <spamfilter.aug1998@tantalophile.demon.co.uk>
Date: 24 Aug 1998 11:16:36 +0100
Links: << >>  << T >>  << A >>
Tim Forcer <tmf@ecs.soton.ac.uk.nojunk> writes:
> We have two Data I/O Chiplab 48 "project" programmers, which are nice
> units.  But they are unusable under Windows NT due to the dreaded port
> access problem.  Data I/O's UK agents state that no software upgrade
> will allow function under NT, and we've tried various tricks involving
> public-domain drivers such as giveio.sys without success.

It might be possible to run it under Wine in Linux or NetBSD/FreeBSD, if
you have such systems.  Wine allows direct I/O port access if configured
for it.

It won't work if the software requires precise (microseconds) timing
though.  I couldn't get Rainbow's dongle driver to work for this reason.
OTOH, someone reported that AutoCAD's dongle driver worked.

I don't recommend trying unless you're already into Linux or BSD.

-- Jamie
Article: 11560
Subject: Re: professional autorouters
From: Roy Battell <moorhen@moorhen.demon.co.uk>
Date: Mon, 24 Aug 1998 13:31:03 +0100
Links: << >>  << T >>  << A >>
In article <35DD8489.2E3F673B@physik.uni-giessen.de>, Michael Traxler
<Michael.Traxler@physik.uni-giessen.de> writes
>Hello electronic experts!
>
>At the University of Giessen we use the Protel design system for our
>quite complex (now 6 layer boards)
>PCBs. We are content with the schematic part of Protel but totally
>disappointed of the "neuro autorouter".
>It cannot use blind and buried vias and it has no macro capability,
>simply it's not a professional tool and not
>good enough for our purposes.
>My question is: What autorouter do you use and recommend? Should we
>switch to a totally different environment
>with integrated placer and autorouter or is there a really good
>autorouter which can read our Protel design files?
>
>Thanks a lot for your answers,
>
>    Michael Traxler
>    II. Physikalisches Institut
>    University of Giessen
>
I asked Vutrax Tech support for their comments and received the 
following which you might find of interest.

Vutrax utilises two routing engines, our own, Vuroute, which is a Multi-
layer Ripup and Retry autorouter offering Blind and Buried vias,
Mitring, Track Widening and Multiple Rules directives for special
clearance directives this obviously can only run with the Vutrax PCB
design Software.

We are really not sure if Protel offer and interface into the Specctra
Autorouter from Cadence which we also recommend. It is a shape based
autorouter which very efficient and fast. There is a Base Autorouter,
which can be purchased on a layer restriction basis:- 2, 4, 6 or
Unlimited signal layers all with unlimited ground/powerplane layers.
Extra modules can be added which include:-

Design For Manufacture - DFM (essential) Mitring, Testpoints etc
Advance Rules - ADV - Special clearance options
Hybrid - HYB - Buried vias, Wire Bonding
Fast - FST - Parallelisn control, Match Length control, Shielding
EditRoute - Interactive routing
 
Vutrax supports just the Specctra Autorouting/Edit Routing software but
not the Autoplacment routines. The current product we are distributing
is Specctra version 7.1.

The pricing details for Vutrax and Specctra which includes the interface
module are on our Web site at:-

http://www.vutrax.co.uk   
-- 
>

-- 
Roy Battell.
    To use this address remove the digits included to remove Spam ...
    Mail: moorhen@moorhen.demon666.co.uk

Article: 11561
Subject: Free VHDL editor
From: twinsparc <twinsparc@sussex.ac.uk>
Date: Mon, 24 Aug 1998 16:38:32 +0100
Links: << >>  << T >>  << A >>
As title suggest, a VHDL editor made by people who use VHDL every day

download it from
http://www.geocities.com/SiliconValley/Grid/6044/Ved.html

and if you want to notify you about updates (if I ever bother) send me
an e-mail
twinsparc@geocities.com

Article: 11562
Subject: Re: Altera FLEX10K ClockLock/ClockBoost ?
From: Nicolas Matringe <nicolas@dot.com.fr>
Date: Mon, 24 Aug 1998 19:22:00 +0200
Links: << >>  << T >>  << A >>
Jamie Lokier wrote:
> 
> Nicolas Matringe <nicolas@dot.com.fr> writes:
> > Someone from Altera told me that it was only available with the 10K100DX
> > I'm quite surprised because it's not mentionned anywhere in the databook
> 
> It is mentioned in the on line documentation with Maxplus2 though.

Another problem with Altera : the information is scattered

Nicolas MATRINGE                   DotCom SA
Conception électronique            16 rue du Moulin des Bruyères
Tel: 00 33 1 46 67 51 00           92400 COURBEVOIE
Fax: 00 33 1 46 67 51 01
Article: 11563
Subject: Programmable logic News
From: "mdisman" <mdisman@ix.netcom.com>
Date: 24 Aug 1998 17:45:14 GMT
Links: << >>  << T >>  << A >>
The Programmable Logic News & Views website has been updated with a summary
of the June 1998 edition of the newsletter.

http://www.plnv.com

Murray Disman

Editor
Article: 11564
Subject: Technical Bookstore Update
From: sales@itutech.com (ITU Technologies)
Date: Mon, 24 Aug 1998 18:57:07 GMT
Links: << >>  << T >>  << A >>
Hello!

We've just completed another updated of our Technical Bookstore that
focuses on titles relating to all areas of electronics --  including
robotics, microcontrollers, radio and more.  We are trying to find
books that are outstanding in their field.

We are looking for recommendations for additions to our bookstore.  If
you have any suggestions please e-mail them to books@itutech.com and
we will review your suggestions.

Please see our bookstore at http://www.itutech.com/techbooks.htm

Thanks!

Chris
------------------------------------------------------------------------
Chris Sakkas    (chris@itutech.com)     ftp://itutech.com   
ITU Technologies (sales@itutech.com)    http://www.itutech.com
See our web page for PIC development tools and Caller ID->RS-232 products!
VISA/MasterCard/AE accepted Phone:(513)661-7523 FAX:(513)661-7534
Toll Free Order Line: 1-888-4-ITU-TECH
Article: 11565
Subject: 8B/10B coding
From: fname lname <username@nortel.com>
Date: Mon, 24 Aug 1998 16:40:25 -0400
Links: << >>  << T >>  << A >>
Is there any public domain code for 8B/10B encoding/decoding? I need
an FPGA implementation that can handle gigabit traffic...
If so, I would like to get a copy.

thanx in advance
bye
rao
Article: 11566
Subject: 8B/10B coding
From: Paparao Palacharla <paparao@nortel.com>
Date: Mon, 24 Aug 1998 16:42:07 -0400
Links: << >>  << T >>  << A >>
Is there any public domain code for 8B/10B encoding/decoding? I need
an FPGA implementation that can handle gigabit traffic...
If so, I would like to get a copy.

thanx in advance
bye
rao

email: paparao@nortel.ca
Article: 11567
Subject: Job opportunities for FPGA Applications Engineers
From: Sara Reinstein <sreinstein@earthlink.net>
Date: Mon, 24 Aug 1998 14:32:45 -0700
Links: << >>  << T >>  << A >>
     Field Applications Engineers / FPGA and DSP
Location
     Boston, MA
     Los Angeles, CA
     Philadelphia, PA
     San Jose, CA (2 positions)

Description

Avnet, Inc., a Fortune 500 company with $5 billion in annual sales, with
locations located throughout the world, is currently recruiting Field
Applications Engineers. Hamilton Hallmark, a leading division of Avnet
continues to invest in the technical resources and infrastructure to do
business in the new marketplace. As a result, we now support
distribution’s largest and most progressive technical organization.

HH Field Applications Engineers are technical members of our sales team.
FAEs advocate both the existing and emerging technical solutions of the
suppliers on our linecard. FAEs may support one or more supplier lines
or have responsibility for specific vertical areas of technology, such
as Programmable Products, DSP, Analog, or Communications.

FAEs must be self motivated, work well with others, posses excellent
communication skills, and have a minimum three years design experience
in the product lines and/or technology that they support. Previous
customer support background a plus. Some travel required. BSEE
preferred.

Boston, MA, Los Angeles, CA, and Philadelphia, PA positions will support
PLD / FPGA manufacturing lines. Candidates must have PLD / FPGA design
experience.

San Jose, CA positions will support PLD / FPGA or DSP manufacturing
lines. Candidates must have PLD / FPGA or DSP design experience.


Avnet offers competitive salaries, tuition reimbursement, stock purchase
plans and a comprehensive benefits package.
For more information or to submit a resume, contact
sreinstein@earthlink.net or call 602/704-0609 or fax resume to
602/704-0599, Attention: Sara Reinstein.

You may also view other technical career opportunities at
http://www.hh.avnet.com/career/career_opportunity.html


EEO M/F/D/V


Article: 11568
Subject: Re: professional autorouters
From: "K. Tyler" <tylereng@pacbell.net>
Date: Mon, 24 Aug 1998 16:12:43 -0700
Links: << >>  << T >>  << A >>
AbdulraHman Lomax wrote:

> I've spent a *lot* more money on routers and gotten much worse than
> Route 98. Yes, it may not do blind vias (I haven't actually checked.)
> But, then again, I've never used a blind via and don't plan to in the
> near future: why raise my customers fab cost?
>
> AbdulraHman Lomax

  Are you saying Blind vias or intended to say Buried vias ?

K.Tyler

Article: 11569
Subject: Re: professional autorouters
From: marjan@vom.com (AbdulraHman Lomax)
Date: Mon, 24 Aug 1998 23:29:09 GMT
Links: << >>  << T >>  << A >>
"Chr. Moecking" <uCon_electronics@csi.com> wrote:

>Hi Michael,
>
>you wrote:
>>My question is: What autorouter do you use and recommend? Should we
>>switch to a totally different environment
>>with integrated placer and autorouter or is there a really good
>>autorouter which can read our Protel design files?
>
>I've never found a better autorouter than my brain and my hands, so
>you better make it manually.

Non sequitur. Yes, human beings are very good at routing, or at least
they *can* be. However, sometimes a job simply does not require the
level of optimization that a human being can apply; in these cases an
autorouter can be very useful. So what if there are a few more vias:
vias are cheap, and unless production quantities are high, vias are
cheaper, much cheaper, than human labor. Now, if via count *does*
matter, or really good minimization of trace lengths, then manual
routing may, indeed, be better.

The Protel 98 router, from what I have seen, is very good indeed. Not
as good as I am, but I do not expect all of my assistants to be as
good at PC design as I am. And the router is *much* faster than me....

I've spent a *lot* more money on routers and gotten much worse than
Route 98. Yes, it may not do blind vias (I haven't actually checked.)
But, then again, I've never used a blind via and don't plan to in the
near future: why raise my customers fab cost?

Of course, there are jobs where they are really useful, I am sure. I
just don't see them in general commercial work. Protel 98 supports
blind vias even if the autorouter doesn't.


AbdulraHman Lomax
marjan@vom.com
P.O. Box 423
Sonoma, CA 95476
USA
Article: 11570
Subject: Re: New Evolutionary Electronics Book
From: jim@rst-engr.com (Jim Weir)
Date: Mon, 24 Aug 1998 23:29:17 GMT
Links: << >>  << T >>  << A >>

->Summary
->^^^^^^^
->In reconfigurable hardware, the behaviours and interconnections of the
->constituent electronic primitives can be repeatedly changed. Artificial
->evolution can automatically derive a configuration causing the system to
->exhibit a pre-specified desired behaviour. A circuit's evolutionary 

Oh BOY.  If the summary is this readable, I just can't WAIT to curl up with
this sucker some cold evening when I can't sleep.  {;-)

Jim
Article: 11571
Subject: PROM alternative
From: jcvilleneuve@hotmail.com
Date: Tue, 25 Aug 1998 03:01:01 GMT
Links: << >>  << T >>  << A >>


Hello there!!!

Is anybody has used something else than a PROM for the configuration cycle of
their FPGA (example direct CPU to fpga)?



Thank you, Jici

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Article: 11572
Subject: Re: PROM alternative
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Tue, 25 Aug 1998 03:57:55 GMT
Links: << >>  << T >>  << A >>
jcvilleneuve@hotmail.com wrote:

>Hello there!!!

>Is anybody has used something else than a PROM for the configuration cycle of
>their FPGA (example direct CPU to fpga)?

Yep.  It works pretty good too.  Did it with a Xilinx part once.  I
had to 'hack into' their bitstream file to do it, though.  Wrote up a
program to create a 'C' array file from the Xilinx bitstream file
(automatically), and then downloaded it to the FPGA part from a CPU at
boot-up time.  

Interestingly enough, that project re-configured the same FPGA using
two different circuits.  It was used on a sensor which measured the
speed of light.  During the first part of the measurement cycle, the
FPGA was used as a really fancy timer/counter (500 MHz+ operation).
Once some data samples were taken, the FPGA was re-configured as a
special kind of hardware averager.  That way, we got away with a
smaller and cheaper part.

Wade Peterson
Silicore Corporation / www.silicore.net




Article: 11573
Subject: Re: professional autorouters
From: "Seth Goodman" <sethg@midplains.net>
Date: Mon, 24 Aug 1998 23:58:13 -0500
Links: << >>  << T >>  << A >>
I find that the Specctra autorouter from CCT is excellent if you are willing
to spend the time to tell it what is important.  However, rather than go
with blind and buried vias, I would suggest adding more layers or tightening
the design rules (if your fabricators allow you to).  These via types are
wonderful in concept but are seldom used due to yield problems.  But if you
must, there are board houses that can fabricate them and Specctra does
support them.

Seth Goodman
Goodman & Associates
Verona, WI
USA


K. Tyler wrote in message <35E1F36B.7223C43D@pacbell.net>...
>AbdulraHman Lomax wrote:
>
>> I've spent a *lot* more money on routers and gotten much worse than
>> Route 98. Yes, it may not do blind vias (I haven't actually checked.)
>> But, then again, I've never used a blind via and don't plan to in the
>> near future: why raise my customers fab cost?
>>
>> AbdulraHman Lomax
>
>  Are you saying Blind vias or intended to say Buried vias ?
>
>K.Tyler
>


Article: 11574
Subject: looking a job around Austin
From: kosby <kos@mail.utexas.edu>
Date: Tue, 25 Aug 1998 00:28:08 -0500
Links: << >>  << T >>  << A >>
Hello? I'm a Ph.D. student in computer engineering at UT, Austin.
I'm looking for a part-time(20hrs/week)job during semesters and a
full-time job during next summer.
I have 3 years industrial experience of Altera's EPLD/CPLD programming
using schematic capture or AHDL and digital H/W board design. I have 2
years experience in ASIC design using VHDL through Synopsys synthesis
tool.
Could you give any information for me to get a relevant job around
Ausitn, Texas? I have been looking for it but I couldn't find any direct
connection to companies. Your relpy or comments will be appreciated.

-- kosby


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