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Messages from 6925

Article: 6925
Subject: Altera FLEX10K initialization
From: "Pete Burch" <pete.burch@REMOVErl.ac.uk>
Date: 9 Jul 1997 15:57:52 GMT
Links: << >>  << T >>  << A >>
When a FLEX10K has completed configuration, and is into the initialization
stage of command mode, I understand that all registers are reset. Should I
take this to mean that all LE registers are cleared (ie hold logic 0)? It
would seem that IOE registers cannot be set to anything other than logic 0
as they have no preset connection.

Also, if I set the 'release clears before tri-states' option, 

a) how many clock cycles elapse between clear being released and tri-state
being released
b) what is the core of the device doing in this time


Thanks in advance

Pete Burch

System Design Group
Rutherford Appleton Laboratory
Article: 6926
Subject: ANNOUNCE: Free seminars on language-based FPGA design (UK)
From: David Pashley <david@fpga.demon.co.uk>
Date: Wed, 9 Jul 1997 17:10:38 +0100
Links: << >>  << T >>  << A >>
Next week we are hosting a series of regional seminars on VHDL and
Verilog based design for FPGA and CPLD devices using Viewlogic Workview
Office.

We will perform a complete design demo, from mixed schematic and VHDL
through to implementation in an FPGA. Although the demo will be VHDL
based (SpeedWave simulator + ViewSynthesis), we will be introducing the
Verilog flow (Chronologic VCS + ViewSynthesis) now available within the
Workview Office suite.

The technical level will be suitable for those wishing to transition
from schematic-based design, whether or not they are already using
Viewlogic tools. There will be no non-engineer presenting at any point.

The seminar locations are Bracknell - Tuesday 15th, Manchester Wed.
16th, Cambridge Thur. 17th, Edinburgh Fri. 18th.

Please email or call Caroline Hawkins if you wish to attend.
-- 
David Pashley                 <
 ------------------------  <  <  <  ---------- Email: david@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
| * The EDA Source *       <  <  <               Fax: +44 1280 700577      |
 ---------------------------  <  ------------------------------------------
Article: 6927
Subject: Re: Generating Sine/Cosine digitally
From: mikesw@dhp.com (M Sweger)
Date: 9 Jul 1997 17:08:49 GMT
Links: << >>  << T >>  << A >>
Ralph Reinhold (ralph.r.reinhold@boeing.com) wrote:
: Rune Bæverrud wrote:
: > 
: > Marc 'Nepomuk' Heuler wrote:
: > 
: > > While digging the books, one could find
: > >
: > > sin(A+B) = sin(A) * cos(B) + cos(A) * sin(B)
: > > cos(A+B) = cos(A) * cos(B) - sin(A) * sin(B)
: > >
: > > So if you can tolerate 4 MULs and 2 ADDs per iteration, you can hardcode
: > > sin(B) and cos(B) for the desired frequency, and start off at sin(A)=0 and
: > > sin(B)=1.  Each iteration of the formula (4xMUL 2xADD) gives the next
: > > sin/cos pair for your frequency.
: > >
: > > They run indefinitely.
: > >
: > > There's another technique, a sinusodial oscillator, which requires only one
: > > multiplication and an ADD per iteration.
: > >
: > > Init:   y(-1)= 0
: > >         y(-2)= -A * sin W
: > >
: > >         with A= Amplitude of Sinus
: > >              W= 2*pi* Frequency / Samplerate
: > >
: > > Each sinus output is calculated as y(n) = 2* cos W * y(n-1) - y(n-2)
: > >
: > > I have not made a detailed comparison yet, but from first tests it seems
: > > that the first method is more exact, when using 16 bit fixed point
: > > arithmetic.
: > 
: > Do you have any idea of the stability and accuracy of these algorithms?
: > An oscillator will usually have a loop gain >1, resulting in the
: > oscillator 'taking off' and use all the bandwidth of the
: > adder/integrator registers. It will usually limit itself with nasty
: > clipping (chopping of the tops) when the registers no longer are large
: > enough to hold the accumulated values.
: > 
: > The original example I provided here actually does work, but I would
: > love to find out if the loop gain could be set to exactly 1. If it could
: > - this sin/cos generator could wipe out any lookup-table based generator
: > easily, because of the much higher resolution. For instance, you could
: > easily generate a new sin/cos pair at every clock cycle, 50MHz clock is
: > no big deal, and you could have the resolution you want, like a 32 bit
: > result. And you could easily do this in the smallest FPGAs available.
: > Now - that would be something...
: > 
: > Regards,
: > Rune Baeverrud
: No one has heard of the CORDIC algorithm?

Hi,
	Yes, I have heard of the CORDIC algorithm.

--
	Mike,
	mikesw@whiterose.net

Article: 6928
Subject: Re: fast scopes: how?
From: A William Sloman <sloman@sci.kun.nl>
Date: Wed, 09 Jul 1997 14:02:06 -0700
Links: << >>  << T >>  << A >>
Joseph H Allen wrote:

> In article <MPG.e24e9c7dd0c4326989831@nntp.aracnet.com>,
> bob elkind <eteam.nospam@aracnet.com> wrote:
>

        <snip>

> The transmission line techniques were really cool.  For example, to
> make a
> fast high power amplifier you might put a bunch of low power
> amplifiers in
> parallel- the problem is that the output capacitances will all end up
> in
> parallel too.  To fix it, put inductors between the amplifiers.  Each
> amplifier will now only see its own output capacitance, and those
> capacitances and the inductors make a transmission line (so you have
> to
> terminate it and feed the amplifiers with a matched transmission line
> so the
> delays are matched).

This begins to sound like Percival's distributed amplifier, where the
inputs tothe amplifiers, and the outputs from the amplifiers go to taps
on an
input and an output transmission line respectively.

Cherry's textbook liked it a lot - how to get unlimited gain from
amplifiers of
finite gain-bandwidth product. I met Percival when I worked for EMI from

1976 to 1979, but never got to talk to him about that particular
invention.

>
>
> You can also lower the node capacitance of deflection plates by using
> a
> whole bunch of them in parallel but separated by inductors and
> terminated.
>
> T-coils can reduce the rise time of conventional amplifiers driving
> capacitive loads by almost 60%.

> None of this will compete with GaAs multi-chip modules, of course, but
> it is
> still impressive how far you can go with conventional discretes.

My project at Cambridge Instruments used a bunch of 5GHz npn and pnp
transistors in spots where the Gigabit Logic GaAs wouldn't hack it.

                                            Bill Sloman, Nijmegen

Article: 6929
Subject: Re: Generating Sine/Cosine digitally
From: terry.harris@dial.pipex.com (Terry Harris)
Date: Wed, 09 Jul 1997 23:03:20 GMT
Links: << >>  << T >>  << A >>
Ralph Reinhold <ralph.r.reinhold@boeing.com> wrote:

>No one has heard of the CORDIC algorithm?

Yes but can it efficiently (in digital hardware) generate a sinewave
rather than just the sine of an angle?

On a perhaps more practical note if you want an analog sinewave then a
walsh transform generator might give you the best sinewave for your
buck.

Can anyone give or point me at some theory for walsh sinewave
generators?

Cheers Terry...
Article: 6930
Subject: Re: fast scopes: how?
From: acj@ultranet.com (Jon Goguen)
Date: 9 Jul 1997 23:10:11 GMT
Links: << >>  << T >>  << A >>
I don't know if it's already been mentioned, but some fast scopes work by
scanning the electron beam across a small CCD, using it to store the
trace.  The CCD framew can then be read out and processed like an ordinary
video frame.  The technique is called scan conversion, and can realize
effective sampling rates in 100 GS/s range even in single-shot mode.  I
have an old Tek 7912AD, which uses this technique with a vidicon-like tube
rather than a CCD.

Somehow, it seems like cheating.

Cheers,

Jon
Article: 6931
Subject: Simulating large VHDL design (FPGA backannotated)
From: Georg Diebel <g_diebel@lis.e-technik.tu-muenchen.de>
Date: Thu, 10 Jul 1997 08:13:15 +0200
Links: << >>  << T >>  << A >>
Hi everybody,

I just ran into a problem that left me swinging in the breeze ...
If anybody could give me a hint or point me to a solution, I'd be 
really happy.

Now the Problem:

I have a VHDL design targeted for a Altera FLEX FPGA (10K50).
I have it compiled with the Altera Tools and now want to do 
a simulation with the actual timing values (post place-and-
route).
With the Altera SW, there are 2 possibilities to do that:
(A) you can get a VHDL-file which contains *everything*, including
    delays;
(B) you can use a SDF-file in combination with an Altera-provided
    VITAL-Library and an appropriate VHDL-netlist.

Now, doing this, I get a 2.4 MB VHDL-file in case (A), and even
bigger files for (B): 3.4 MB VHDL, ~4 MB SDF.

When I try to simulate these designs (Synopsys VSS), first everything 
looks good, but when I try to set a trace (view a waveform), the
simulator gets to work (on what I don't know) and won't stop and
won't react to anything (at least for the 4 hours I had the patience
to wait).

OK, then I figured that this VHDL design simply was too large for
the *interpreted* VHDL-simulator from Synopsys and hence tried to
analyze the VHDL for the "compiled" mode. This took about 3 hours
(yes, only analyze & compile) before the job ran out of memory and
aborted. Oh, I was running it on a UltraSparc with 600 MB physical
memory and about 1.2 Gig of swap space ... wouldn't know where to
find a bigger machine here at the institute.

Now, what to do?
I hope that there are some folks who had similar problems and solved
them. After all, a "post-layout" simulation of a complete design
in a programmable device isn't so terribly unusual, no?


Looking forward to any ideas!

Yours, Georg.

-- 
All opinions expressed are mine, not my employers'.

######  #   #   #    #  ###  Georg Diebel
  #  #  ## ##   #    # #     Institute for Integrated Circuits
  #  #  # # #   #    #  ##   Technical University of Munich
  #  #  #   #   #    #    #  g_diebel@lis.e-technik.tu-muenchen.de
  #  ####   #   #### # ###   Phone 0049-89-289-28578
Article: 6932
Subject: Re: Xilinx Prom Generation Problem
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 10 Jul 1997 10:06:31 GMT
Links: << >>  << T >>  << A >>

You sure have a problem, but I don't think it is hopeless, but it is going
to be messy. 

This would be an excellent chance for me to take some well deserved
potshots at Xilinx for creating this stupid situation, but I'll help
you instead. (By the way, did you call their customer support? or
try their email support at hotline@xilinx.com ?)

Anyway, here is the solution.

1) check that the total bitstream length you are going for is less 
   than the maximum length (which is about 16 million bits). Your
   basic bitstream is about 1459539, so no big probs here.
   (the sum of each bitstream taken from the 1994 data book for the
   XC4000H parts, and the 1996 data book for the XC4000E and XC4000EX
   parts. Sum the value of the program data size, not the prom data
   sizes.)

2)  Now go create RAW bit stream files for the XC4000H devices and the
    XC4020E device. The makebits command is "makebits -b filename.lca"

3)  Now go create the same thing for your XC4036EX. The program is
    called bitgen. I don't have the docs in front of me, (because
    there are no hard copy docs for M1 :-(  ), but I seem to remember
    that the menu item you need to select is 'ascii' bitstream. From
    the command line, you include the '-b' option

4)  Now take each of the files created, and edit them in a text editor.
    Remove the text from the beginning of each file, and also the header
    line: (make sure you have an editor that can handle long lines)

This is what the XACT stuff will look like. Delete the first 8 lines,
( YES, including the first line of data. ) make a copy of the first line
of data from one of the files. We will use it as a template later.

Xilinx LCA great-design.lca 4005HMQ240
File great-design.rbt
Wed Feb 12 03:11:09 1997
Wed Feb 12 03:11:09 1997
Source
Version
Produced by makebits version 5.2.1
1111111100100000011001110001000110011111
01010111111111101111111010111111101011111110101111 etc ...
01111111111111011111111101111111110111111111011111 etc ...
01111111110111111111011111111101111111110111111101 etc ...
01011111111101111111110111111111111111110011010101 etc ...


The M1 stuff looks like this: (delete 8 lines, including the first
data line.)

Xilinx ASCII Bitstream
Created by Bitstream M1.2.6
Design name: 	Test01.ncd
Architecture:	xc4036EX
Part:        	4036exdip16
Date:        	Fri Feb 28 23:16:48 1997
Bits:        	832523
1111111100100000001111001000100110011111
010101111111111011111110101111111010111111101111010101  etc ...
011111111111110111111111011111111101111111110111111111  etc ...
011110111101101101110111111111111111111111111111110110  etc ...
011111111101111111111011111111101111111110111111111011  etc ...


5) Now join all the files together, in the same order as the daisy chain.
   The first section of combined file it the data for the first chip
   in the chain. The last section is for the last chip.
   Be real careful that all you have in the file is the data bits (minus
   the headers that you deleted).

6) count how many bits there are. The answer should be real close
   to 1459539. (file length cant be used as it includes CR and LF
   characters. We only want the total of '0' and '1' characters)

7) Now comes the best bit (a pun) of all. You need to build a new header.
   Start with one of the headers that you saved.
   The bits are:
	P   Preamble
        S   Start Code
        L   Length Count
        T   Tail Pad

   1111111100100000001111001000100110011111
   PPPPPPPPSSSSLLLLLLLLLLLLLLLLLLLLLLLLTTTT

Take the length count that you calculated in step 6, and add 40 to it
(which is the length of the header) then add 1 for each chip in daisy
chain (6 in your case). The sum might be 1459585 or maybe a slightly
higher (but not more than 50 higher). Convert to a 24 bit binary number:
000101100100010110000001

Insert this number in-place of the 'L' field of your saved header, and then
with your bright new combined header, put it at the beginning of your
combined bitstream file. it will look something like this now: 

1111111100100001011001000101100000011111
010101111111111011111110101111111010111111101111010101  etc ...
011111111111110111111111011111111101111111110111111111  etc ...
011110111101101101110111111111111111111111111111110110  etc ...
011111111101111111111011111111101111111110111111111011  etc ...

8) go to the end of the file and add at least 6 (because there are 6 chips)
   extra '1' bits. I would probably add 20.

9) The file is now ready to go into whatever you are going to store
   the bitstream in, i.e. PROM, RAM, Floppy, paper tape, whatever.
   During configuration, the data is sent to the first chip starting
   at the left of the first line, and just sending the data in the
   same order that it is in the file. If you need to convert the data
   into byte wide data, and then serialize it during download, REMEMBER
   to maintain the order. 

10) When downloading the bitstream, I usually clock the CCLK an extra
    10 to 20 times beyond the length of the bitstream, so I might add
    additional pad '1' bits at the end of the stream, but NOT change
    the length count at the beginning.


ALSO:  The 4003H and 4005H parts are being discontinued by Xilinx so
       remember to buy as many as you will ever need now.


In article <01bc8b71$a2df9be0$fbf64092@hobbit> "Piet du Toit" <pdtoit@csir.co.za> writes:
>I have a got SERIOUS problem.
>
>I have got a PCB (already build up) with the following devices in a Slave
>serial Chain.
>
>4005H pq240
>4020E hq240
>4003H pq208
>4003H pq208
>4005H pq240
>4036EX hq304
>
>I have got BIT files for all the devices. 
>The Problem is that (according to Xilinx) there is NO way that I can create
>a single PROM file for this serial chain.

Well I think I have shown that it isn't impossible, just stupidly
difficult. 
 
>
>The Xact 6.x software can NOT  load a 4036EX bit file and the 
>M1 (NT 4.0) software can NOT  load a 4000H or 4000 bit file.
>
>Does anybody know how to merge these files externally ?

See above :-)

>From what I understand, there are some extra Pre-ambles in the PROM file
>for a Serial Chain.

Not really. Just remove the headers from all but the first bitstream,
and edit the header at the beginning.

>
>PS.
>How could Xilinx NOT have forseen this problem scenario ???

I could answer this question too, but although this may surprise you,
I am more pissed about this than you are.

>
>Thanks 

Your Welcome.

Philip Freidin.


>Piet
>______________________
>E-mail: pdtoit@csir.co.za


Article: 6933
Subject: Re: fast scopes: how?
From: rbmccammon@mmm.com (Roy McCammon)
Date: Thu, 10 Jul 1997 08:34:19 -0500
Links: << >>  << T >>  << A >>
Bill Sloman wrote:
> My project at Cambridge Instruments used a bunch of 5GHz npn and pnp
> transistors in spots where the Gigabit Logic GaAs wouldn't hack it.

Would you kindly share the idenities of those 5GHz transistors.



Opinions expressed herein are my own and may not represent those of my employer.

Article: 6934
Subject: Re: Generating Sine/Cosine digitally
From: "Tom Burgess" <tburgess@drao.nrc.ca>
Date: 10 Jul 1997 17:25:37 GMT
Links: << >>  << T >>  << A >>
A few more references for those with access to an engineering library:

Al-Ibrahim & Al-Khateeb,
"Digital sinusoidal oscillator with low and uniform frequency spacing"
IEE Proc.-Circuits Devices & Systems V.144 #3, June 97
-this contains 10 references, 2 of which are listed below.

Fliege & Wintermantel
"Complex digital oscillators & FSK modulators"
IEEE Trans.on Signal Processing, Feb 92.

Oppenheim & Schafer
"Digital Signal Processing"
(Prentice Hall, 1975)

I first saw this method described in Hal Chamberlin's classic "Musical
Applications of Microprocessors", which
is regrettably out of print. It has been used since the dawn of time for
generating FFT twiddle factors on the fly,
as in the Numerical Recipes FFT code.

	regards, tom (tburgess@drao.nrc.ca)

Rune Bæverrud <r@acte.no> wrote in article <33C39567.5DCE65E0@acte.no>...
> Hi All,
> 
> I've been asked to provide some references for the ideas that has been
> presented on this subject.
> 

Article: 6935
Subject: http://www.love.com
From: randy97
Date: 10 Jul 97 18:30:53 GMT
Links: << >>  << T >>  << A >>
Looking to find people in your area that enjoy the same things
as this newsgroup?

Check out http://www.love.com

It's free, it's new, and it's awesome.

Rand

Article: 6936
Subject: Re: Xilinx Prom Generation Problem
From: murray@pa.dec.com (Hal Murray)
Date: 10 Jul 1997 20:58:37 GMT
Links: << >>  << T >>  << A >>
Philip's recipe matches what we have been doing for years.

I've never been able to figure out how many extra bits to add.
It's always been simpler to add "enough" than worry about it.

I suggest writing a program to do it.  My fingers are too fat to
do that much editing by hand without botching something.  Besides,
after you fix a bug in a chip you will have to do it all over again.

Article: 6937
Subject: Re: Generating Sine/Cosine digitally
From: Glenn Fasnacht <gfasnacht@gwis.com>
Date: Thu, 10 Jul 1997 17:21:03 -0400
Links: << >>  << T >>  << A >>
These have been a bunch of good answers, but if you can live with the
limitations, there is a much simpler answer.

Analog Devices makes an AD9850 DDS on a chip.

This device will generate sine waves from sub Hz to 40 MHz. Crystal
stable, and programmable with .03 Hz resolution. 

Hook up a 125 MHz osc. to the chip (they are avaialble), write a 40 bit
word to it (either serially or parallel), and youv'e got sine waves.

The 40 bit word sets the frequency, and the phase. Hook two to the same
clock, reset both chips at the same time, write the 40 bit words to
each, one in phase, one 90 deg out of phase, start them, and your
running.
Article: 6938
Subject: VHDL Synthesis in Xilinx Foundation Series
From: yadav@cse.iitb.ernet.in (Navneet S Yadav)
Date: Fri, 11 Jul 1997 07:17:44 GMT
Links: << >>  << T >>  << A >>

hi,

	if anyone has used the VHDL synthesizer available with
Xilinx Foundation series could they summarize their experience ?
especially how does it compare to viewlogic's vhdl synthesizer
and to Synopsys FPGA Express for PCs. 

	is the Synopsys FPGA Express for PCs synthesizer as good
as the one which they offer on unix workstations ?

	i would appreciate an email reply besides the news posting.
news delivery at our site is rather unreliable.

	thanks in advance.

cheers,
yadav

email:yadav@cse.iitb.ernet.in
Article: 6939
Subject: Re: VHDL Synthesis in Xilinx Foundation Series
From: Georg Diebel <g_diebel@lis.e-technik.tu-muenchen.de>
Date: Fri, 11 Jul 1997 12:46:52 +0200
Links: << >>  << T >>  << A >>
Navneet S Yadav wrote:
> ... 
>         if anyone has used the VHDL synthesizer available with
> Xilinx Foundation series could they summarize their experience ?
> especially how does it compare to viewlogic's vhdl synthesizer
> and to Synopsys FPGA Express for PCs.
> 
>         is the Synopsys FPGA Express for PCs synthesizer as good
> as the one which they offer on unix workstations ?
> ... 
> email:yadav@cse.iitb.ernet.in

Hi yadav,

I do not use Xilinx tools or the Synopsys FPGA Express, but 4 weeks
ago I participated at a Xilinx Symposium where they talked at length
about their new software package M1. 
There one of their officials told everyone that Xilinx had signed 
an agreement with Synopsys so that the FPGA Express is now included
in the Xilinx M1 Foundation Series as OEM. 
They told the whole bunch of participants (200 engineers from all over
Europe) so I think they meant it for-real.

Hope this helps, 

Georg.

-- 
All opinions expressed are mine, not my employers'.

######  #   #   #    #  ###  Georg Diebel
  #  #  ## ##   #    # #     Institute for Integrated Circuits
  #  #  # # #   #    #  ##   Technical University of Munich
  #  #  #   #   #    #    #  g_diebel@lis.e-technik.tu-muenchen.de
  #  ####   #   #### # ###   Phone 0049-89-289-28578
Article: 6940
Subject: Re: fast scopes: how?
From: sloman@sci.kun.nl
Date: Fri, 11 Jul 1997 09:51:51 -0600
Links: << >>  << T >>  << A >>
In article <33C4E4DB.3B11@mmm.com>,
  rbmccammon@mmm.com (Roy McCammon) wrote:
>
> Bill Sloman wrote:
> > My project at Cambridge Instruments used a bunch of 5GHz npn and pnp
> > transistors in spots where the Gigabit Logic GaAs wouldn't hack it.
>
> Would you kindly share the identities of those 5GHz transistors.

We used quite a few BFR92 (NPN) and BFT92 (PNP), mostly for level
shifting. They are SOT-23 packaged parts, stocked by Farnell. I doubt if
we saw the full 5GHz bandwidth, since we always used them with 33R
"base-stoppers" - that is a 33R resistor mounted close to the base input
to stop them oscillating.

Until recently, Farnell Stocked the BFR91 (NPN) and the BFQ51 (PNP) in the
bulkier SOT-37 strip-line package, which is rather easier to handle.

Cheap 5GHz transistors have been around since the 1970's. See "Nanosecond
pulse stretcher" in J.Phys. E: Sci. Instrum. Vol.12 pages 686-7 (1979).

Farnell now stocks 10GHz parts (but only NPN), and an acquaintance who
works for Philips in Nijmegen (the boyfriend of one of my wife's graduate
students) has told me that Siemens are selling 50GHz parts cheap, and
offered me a couple of 500GHz parts from a batch he'd made....

                    Bill Sloman, Nijmegen

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6941
Subject: Re: fast scopes: how?
From: Mike <NoSpam@Today.Thanks>
Date: Fri, 11 Jul 1997 20:56:38 -0700
Links: << >>  << T >>  << A >>
sloman@sci.kun.nl wrote:
<...> 
> Until recently, Farnell Stocked the BFR91 (NPN) and the BFQ51 (PNP) in the
> bulkier SOT-37 strip-line package, which is rather easier to handle.
> 
> Cheap 5GHz transistors have been around since the 1970's. See "Nanosecond
> pulse stretcher" in J.Phys. E: Sci. Instrum. Vol.12 pages 686-7 (1979).
> 
> Farnell now stocks 10GHz parts (but only NPN), and an acquaintance who
> works for Philips in Nijmegen (the boyfriend of one of my wife's graduate
> students) has told me that Siemens are selling 50GHz parts cheap, and
> offered me a couple of 500GHz parts from a batch he'd made....
> 
>                     Bill Sloman, Nijmegen
> 
> -------------------==== Posted via Deja News ====-----------------------
>       http://www.dejanews.com/     Search, Read, Post to Usenet

I'll take a couple of those 500GHz parts - how do I contact your friend ?:)

Mike
Article: 6942
Subject: Re: Altera FLEX10K initialization
From: Steve@s-dewey.removetostopspam.demon.co.uk (Steve Dewey)
Date: Sat, 12 Jul 97 18:39:48 GMT
Links: << >>  << T >>  << A >>
Pete

This appears to be the kind of question that should be directed to Altera's
tech. help desk. Send mail to sos@altera.com 

I have always found them very helpful & prompt.

However, if you have tried them, and not received a satisfactory response,
then I think that a lot of people on this group would like to know,
especially given the perpetual flame-war that appears to be waged between
Altera & Xylinx ;-)

Regards

Steve

P.S. Anyone in the UK got Maxplus 8 yet ?


In article <01bc8c80$dacb2460$c513f682@te2lisbon>
           pete.burch@REMOVErl.ac.uk "Pete Burch" writes:

> When a FLEX10K has completed configuration, and is into the initialization
> stage of command mode, I understand that all registers are reset. Should I
> take this to mean that all LE registers are cleared (ie hold logic 0)? It
> would seem that IOE registers cannot be set to anything other than logic 0
> as they have no preset connection.
> 
> Also, if I set the 'release clears before tri-states' option, 
> 
> a) how many clock cycles elapse between clear being released and tri-state
> being released
> b) what is the core of the device doing in this time
> 
> 
> Thanks in advance
> 
> Pete Burch
> 
> System Design Group
> Rutherford Appleton Laboratory
> 

-- 
Steve Dewey
Steve@s-dewey.removetostopspam.demon.co.uk.
Too boring to have an interesting or witty .sig file.


Article: 6943
Subject: Re: Xilinx Prom Generation Problem
From: z80@dserve.com (Peter)
Date: Sat, 12 Jul 1997 19:07:24 GMT
Links: << >>  << T >>  << A >>
Philip,

I am sure to have missed something obvious, but why cannot one use the
old DOS version of Makeprom to combine all the files?


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 6944
Subject: $$$$ NEW SYSTEM, BETTER THAN "ADD ME TO YOUR MAILING LIST" $$$
From: a19@a.a
Date: 13 Jul 97 17:05:56 GMT
Links: << >>  << T >>  << A >>

I have participated in the standard "Please put me on your mailing list" letter and found it to be worth
my time (I get 1 or 2 handfulls or letters every day) but I also found that it's results were nowhere
near what I expected due mainly to people not sending in the money but rather spreading the letter
without paying for it. I participated in that mainly as an experiment and found that there are a
tremendous amount of people willing to do it. I thought about how to, first, eliminate the "non-pay"
problem and, second, to create a monthly income. I came upon the solution and decided to start a new
program. I decided that there were 3 things that this new program needed in order to work for everyone
and they were: 1.) It needed to be very simple and easy for anyone to do, and, 2.) It needed to be
inexpensive enough for even the poorest of people, and, 3.) It needs to be DUPLICATABLE. I think you
will find this program to meet those requirements. I have put lots of thought into it and I ask that you 
PLEASE do NOT modify it. This WILL WORK if you follow it. This system is based on the unconditional
"loaning" of money to people. Simply say, "I am loaning you this $2 as an act of goodwill to help you in 
your financial need, you may pay me back if and when you can." You should find 5 or more people who will 
send $2 to the 5 needy people on this list AND MAINTAIN 5 or more people who will do the same. You
should put your name on postition number 5 and move each of the other names up one position. The name
originally on position number 1 gets removed. You should be able to contact each of your 5 or more
people to see if they are going to be active this month. If not then you need to find one or more people 
to be active in order to maintain at least 5. I am not speaking about the 5 people on the list but
rather the 5 new people you have found. I would highly suggest having more than 5 in any given month.
Now I know that this would be extremely easy to do since I can think of at least 20 people myself who
will do this consistently. The key is to maintain at LEAST 5 active people. If you don't then you can't
expect for the rest of the people to do it either and you can't expect for this system to work. This
system is a no-brainer, and if someone can't afford the $10 + stamps for this then they truly ARE in
need! It is OK to use the internet to find people but I think it would be easier to find them through
people that you know. This way it will be easier for you to contact them every month to ask about their
being active, unless someone is willing to give you their e-mail address. Here are some numbers:
-----------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 4 active members @ $2 each:

Level 1:  $2 x 4 people = $8,  Total now $8
Level 2:  $2 x 16 people = $32, Total now $8 + $32 = $40
Level 3:  $2 x 64 people = $128, Total now $8 + $32 + $128 = $168
Level 4:  $2 x 256 people = $512, Total now $8 + $32 + $128 + $512 = $680
Level 5:  $2 x 1024 people = $2048, Total now $8 + $32 + $128 + $512 + $2048 = *** $2728 ***

Yearly income: $2728 x 12 months = $32,736
------------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 5 active members @ $2 each:

Level 1:  $2 x 5 people = $10,  Total now $10
Level 2:  $2 x 25 people = $50, Total now $10 + $50 = $60
Level 3:  $2 x 125 people = $250, Total now $10 + $50 + $250 = $310
Level 4:  $2 x 500 people = $1000, Total now $10 + $50 + $250 + $1000 = $1310
Level 5:  $2 x 2500 people = $5000, Total now $10 + $50 + $250 + $1000 + $5000 = *** $6310 ***

Yearly income: $6310 x 12 months = $75,720
------------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 6 active members @ $2 each:

Level 1:  $2 x 6 people = $12,  Total now $12
Level 2:  $2 x 36 people = $72, Total now $12 + $72 = $84
Level 3:  $2 x 216 people = $432, Total now $12 + $72 + $432 = $516
Level 4:  $2 x 1296 people = $2592, Total now $12 + $72 + $432 + $2592 = $3108
Level 5:  $2 x 7776 people = $15552, Total now $12 + $72 + $432 + $2592 + $15552 = *** $18660 ***

Yearly income: $18660 x 12 months = $223,920
------------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 7 active members @ $2 each:

Level 1:  $2 x 7 people = $14,  Total now $14
Level 2:  $2 x 49 people = $98, Total now $14 + $98 = $112
Level 3:  $2 x 343 people = $686, Total now $14 + $98 + $686 = $798
Level 4:  $2 x 2401 people = $4802, Total now $14 + $98 + $686 + $4802 = $5600
Level 5:  $2 x 16807 people = $33614, Total now $14 + $98 + $686 + $4802 + $33614 = *** $39214 ***

Yearly income: $39214 x 12 months = $470,568
------------------------------------------------------------------------------------------------------
Keep in mind that it does not matter what day of the month that someone chooses to be active. It DOES
matter that they are active on that day EVERY month. The key to this is DUPLICATION! You must treat this 
as a business. If you treat it like a hobby that is how it will treat you. You could even organize small 
meetings with your people and their prospects and work with your leaders.
Think of how easy this would be for you, how reasonable this is, and of how good the chances are of it
working for you. You may need to hire someone to open all the envelopes.

NOTE: I decided on $2 instead of $1 because it is more feasible and it won't matter much for someone to
send $2 as opposed to $1. Also I was against $5 as that becomes too expensive to duplicate.

Mail $2 every month with a piece of paper saying "I am loaning you this $2 as an act of goodwill to help 
you in your financial need, you may pay me back if and when you can" to the following needy people:


#1 Robert Jezil
   114 Jefferson Ave.
   Slidell, LA 70460

#2 Phil Walther Jr.
   9495 Annapolis Lane North
   Maple Grove, MN 55369

#3 C. E. Burkman
   170 University Ave. W
   Suite 12-129
   Waterloo, Ontario
   N2L 3E9

#4 A. Bailey
   1207 Reeves Road
   Plainfield, IN 46168

#5 J. Martin
   P.O. Box 2292
   Reston, Va. 20195  

Article: 6945
Subject: $$$$ LOAN BUSINESS, EASY MONTHLY INCOME, NO BRAINER $$$$
From: a12@a.a
Date: 13 Jul 97 17:05:58 GMT
Links: << >>  << T >>  << A >>

I have participated in the standard "Please put me on your mailing list" letter and found it to be worth
my time (I get 1 or 2 handfulls or letters every day) but I also found that it's results were nowhere
near what I expected due mainly to people not sending in the money but rather spreading the letter
without paying for it. I participated in that mainly as an experiment and found that there are a
tremendous amount of people willing to do it. I thought about how to, first, eliminate the "non-pay"
problem and, second, to create a monthly income. I came upon the solution and decided to start a new
program. I decided that there were 3 things that this new program needed in order to work for everyone
and they were: 1.) It needed to be very simple and easy for anyone to do, and, 2.) It needed to be
inexpensive enough for even the poorest of people, and, 3.) It needs to be DUPLICATABLE. I think you
will find this program to meet those requirements. I have put lots of thought into it and I ask that you 
PLEASE do NOT modify it. This WILL WORK if you follow it. This system is based on the unconditional
"loaning" of money to people. Simply say, "I am loaning you this $2 as an act of goodwill to help you in 
your financial need, you may pay me back if and when you can." You should find 5 or more people who will 
send $2 to the 5 needy people on this list AND MAINTAIN 5 or more people who will do the same. You
should put your name on postition number 5 and move each of the other names up one position. The name
originally on position number 1 gets removed. You should be able to contact each of your 5 or more
people to see if they are going to be active this month. If not then you need to find one or more people 
to be active in order to maintain at least 5. I am not speaking about the 5 people on the list but
rather the 5 new people you have found. I would highly suggest having more than 5 in any given month.
Now I know that this would be extremely easy to do since I can think of at least 20 people myself who
will do this consistently. The key is to maintain at LEAST 5 active people. If you don't then you can't
expect for the rest of the people to do it either and you can't expect for this system to work. This
system is a no-brainer, and if someone can't afford the $10 + stamps for this then they truly ARE in
need! It is OK to use the internet to find people but I think it would be easier to find them through
people that you know. This way it will be easier for you to contact them every month to ask about their
being active, unless someone is willing to give you their e-mail address. Here are some numbers:
-----------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 4 active members @ $2 each:

Level 1:  $2 x 4 people = $8,  Total now $8
Level 2:  $2 x 16 people = $32, Total now $8 + $32 = $40
Level 3:  $2 x 64 people = $128, Total now $8 + $32 + $128 = $168
Level 4:  $2 x 256 people = $512, Total now $8 + $32 + $128 + $512 = $680
Level 5:  $2 x 1024 people = $2048, Total now $8 + $32 + $128 + $512 + $2048 = *** $2728 ***

Yearly income: $2728 x 12 months = $32,736
------------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 5 active members @ $2 each:

Level 1:  $2 x 5 people = $10,  Total now $10
Level 2:  $2 x 25 people = $50, Total now $10 + $50 = $60
Level 3:  $2 x 125 people = $250, Total now $10 + $50 + $250 = $310
Level 4:  $2 x 500 people = $1000, Total now $10 + $50 + $250 + $1000 = $1310
Level 5:  $2 x 2500 people = $5000, Total now $10 + $50 + $250 + $1000 + $5000 = *** $6310 ***

Yearly income: $6310 x 12 months = $75,720
------------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 6 active members @ $2 each:

Level 1:  $2 x 6 people = $12,  Total now $12
Level 2:  $2 x 36 people = $72, Total now $12 + $72 = $84
Level 3:  $2 x 216 people = $432, Total now $12 + $72 + $432 = $516
Level 4:  $2 x 1296 people = $2592, Total now $12 + $72 + $432 + $2592 = $3108
Level 5:  $2 x 7776 people = $15552, Total now $12 + $72 + $432 + $2592 + $15552 = *** $18660 ***

Yearly income: $18660 x 12 months = $223,920
------------------------------------------------------------------------------------------------------
Monthly income model per level and total for maintaining 7 active members @ $2 each:

Level 1:  $2 x 7 people = $14,  Total now $14
Level 2:  $2 x 49 people = $98, Total now $14 + $98 = $112
Level 3:  $2 x 343 people = $686, Total now $14 + $98 + $686 = $798
Level 4:  $2 x 2401 people = $4802, Total now $14 + $98 + $686 + $4802 = $5600
Level 5:  $2 x 16807 people = $33614, Total now $14 + $98 + $686 + $4802 + $33614 = *** $39214 ***

Yearly income: $39214 x 12 months = $470,568
------------------------------------------------------------------------------------------------------
Keep in mind that it does not matter what day of the month that someone chooses to be active. It DOES
matter that they are active on that day EVERY month. The key to this is DUPLICATION! You must treat this 
as a business. If you treat it like a hobby that is how it will treat you. You could even organize small 
meetings with your people and their prospects and work with your leaders.
Think of how easy this would be for you, how reasonable this is, and of how good the chances are of it
working for you. You may need to hire someone to open all the envelopes.

NOTE: I decided on $2 instead of $1 because it is more feasible and it won't matter much for someone to
send $2 as opposed to $1. Also I was against $5 as that becomes too expensive to duplicate.

Mail $2 every month with a piece of paper saying "I am loaning you this $2 as an act of goodwill to help 
you in your financial need, you may pay me back if and when you can" to the following needy people:


#1 Robert Jezil
   114 Jefferson Ave.
   Slidell, LA 70460

#2 Phil Walther Jr.
   9495 Annapolis Lane North
   Maple Grove, MN 55369

#3 C. E. Burkman
   170 University Ave. W
   Suite 12-129
   Waterloo, Ontario
   N2L 3E9

#4 A. Bailey
   1207 Reeves Road
   Plainfield, IN 46168

#5 J. Martin
   P.O. Box 2292
   Reston, Va. 20195  

Article: 6946
(removed)


Article: 6947
Subject: Re: Xilinx Prom Generation Problem
From: fliptron@netcom.com (Philip Freidin)
Date: Sun, 13 Jul 1997 20:16:19 GMT
Links: << >>  << T >>  << A >>

What you missed is that MAKEPROM refuses to load the XC4036EX bitstream,
because it says the partnumber is invalid (it looks in the partlist.xct
file, and doesn't find it). You could dink with this file (maybe) and
create an entry that would allow makeprom to continue, but you might bump
into other problems (can makeprom handle a device bigger than it was
designe for?, what other things might get broken when the partlist file is
modified, ...). On the other hand, it might work. 

Or you can do the ascii edit I proposed, which I know works.

Oh yes, what about the Prom File formatter in M1? It refuses to load the
XC4000H series bitstreams, and once you try, it then refuses to load
anything after that.

Philip Freidin


In article <33c7bbcb.252207314@news.netcomuk.co.uk> z80@dserve.com (Peter) writes:
>Philip,
>I am sure to have missed something obvious, but why cannot one use the
>old DOS version of Makeprom to combine all the files?
>Peter.
>Return address is invalid to help stop junk mail.
>E-mail replies to z80@digiserve.com.


Article: 6948
Subject: Best FPGA language for portability
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Mon, 14 Jul 1997 00:23:39 GMT
Links: << >>  << T >>  << A >>
I've got a couple of circuits that I think are salable
to FPGA users.  I'd like to package them as 'core'
logic and sell them.  However, I'm trying to decide on the
best approach to FPGA tools.

For example, is there a version of VHDL that would
work (without modification) on XILINX, Lucent and 
Altera FPGAs?

So far, the most portable logic tools that
I've found have been ABEL.  Yep...that surpised
me too.

Any comments on this subject would be most
welcome.



-----------------------------------------------------
Wade D. Peterson         | TEL: 612.722.3815
Consultant to Industry   | FAX: 612.722.5841
3525 E. 27th St. No. 301 |---------- EMAIL ----------
Minneapolis, MN  55406   | peter299@maroon.tc.umn.edu
---------------- Committed to Quality ---------------

Article: 6949
Subject: Re: Generating Sine/Cosine digitally
From: bohdan@ihgp4.ih.lucent.com (-Bodnar,B.L.)
Date: 14 Jul 1997 14:03:52 GMT
Links: << >>  << T >>  << A >>
In article <33C3916F.7CEE@ix.netcom.com>,
Stephen R. Synakowski <srs1@ix.netcom.com> wrote:
>> Probably the most stable method (avoids accumulated offsets from
>> rounding errors) is to accumulate phase in an device that that adds a
>> user selected delta phase to a total at fixed intervals(clock) and
>> applies the count to a sine/cos lookup prom. You can achieve arbitrary
>> precision this way. I haven't seen the initial post, so I am not sure of
>> desired frequencies.
>> --
>> 
>> It is better to keep one's mouth closed and be thought a fool,
>> than to open it and remove all doubt.         Abraham Lincoln
>>         I really have to start listening to Abe.  ;>)
>> 
>>                         Hank McCall
>
>Just a thought, but this might be overkill. Since a square wave is made
>up of an infinite number of sines and harmonics of the fundamental freq,
>you could filter a square wave to pass only the fundamental frequency,
>producing the sinewave. (I think). Purely digital would need a digital
>filter (which in turn needs an simple anti aliasing analog). Therefore
>this may be of no use to you. I thought the concept was neat though.
>Steve

These articles are all very interesting.  However, I've yet to see the
simplest approach mentioned:  using a lookup table with the sine/cosine values
stored.  I recall this technique being used at a senior computer design class
at Illinois Institute of Technology in the early 1980s -- using a lookup table
approach to build a microprocessor controlled universal function generator.
Although only 256 point quantization was used (the microprocessor was the
MC6802), signal quality was quite good.  For higher speed operation, DMA could
probably be used (the lab experiment was simply to demonstrate the concept).

Cordially,

Bohdan Bodnar
bbodnar@lucent.com


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