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Messages from 7800

Article: 7800
Subject: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
From: ebild@metronet.de (Egon Bild)
Date: Thu, 16 Oct 1997 19:31:38 GMT
Links: << >>  << T >>  << A >>
On Thu, 16 Oct 1997 11:19:11 -0400, Ray Andraka
<no_spam_randraka@ids.net> wrote:

>for the 8 pin Amp .100 SIP connector:
>pin    description
>1	VCC
>2	SDO (from the device)
>3	SDI (to the device)
>4	/ispEN
>5	Key (plugged hole in connector)
>6	MODE
>7	GND
>8	SCLK

Thanks for your answer. The pinout for the 8 pin Amp .100 SIP
connector is in the "dlcable.pdf" sheet to, but how does the
25-pin parallel port adapter on the PC side look like ?

Thanks in advance,
Egon.
Article: 7801
Subject: Re: I looked up Altera in an Italian dictionary.....
From: qwerty@WPI.EDU (Michael David Scott)
Date: 16 Oct 1997 20:40:48 GMT
Links: << >>  << T >>  << A >>
Ray Andraka (no_spam_randraka@ids.net) wrote:
: Michael David Scott wrote:
: > 
: > Adam Elbirt (aelbirt@viewlogic.com) wrote:
: > 
: > : Achim Gratz wrote:
: > : >
: > : > "Austin Franklin" <dar8kroom@ix.netcom.com> writes:
: > : >
: > : > > They don't call the Mazda Miata the Miata in Portugal....you might want to
: > : > > look that one up too!
: > 
: > For a similar reason that the old show "Joanny loves Chaci" was the most
: > popular premiere ever to air in Korea.
: > 
: > Go figure what Chaci means.
: 
: Ciaci (pronounced chaci) in polish means Aunt

Not in Korean.



Article: 7802
Subject: Re: I looked up Altera in an Italian dictionary.....
From: "alberto" <alberto.plt@interplanet.it>
Date: 16 Oct 1997 20:58:55 GMT
Links: << >>  << T >>  << A >>

I don't know wether they research for the Italian meaning of Altera, but I
can say that here in Italy say Altera with the accent on the letter 'e'
while the word you found in the dictionary has an accent on the letter 'A'.
Actually I never tought about the Italian translation and I can say that
Altera sells a lot in Italy.


						ciao!!

						Alberto

Austin Franklin <dar8kroom@ix.netcom.com> scritto nell'articolo
<01bcd810$d267b6e0$52625ecf@drt1>...
> This is NOT meant to be any kind of a slander or slight towards
Altera...in
> fact, I highly respect the company and the people I have worked with from
> there.  But...while I was in Italy, for some reason, I decided to look up
> the meaning of 'Altera' in an Italian dictionary...and here's exactly
what
> it read...
> 

Article: 7803
Subject: Re: Can I use M1.3 with Protel Schematic 3.2 ?
From: "Erik de Castro Lopo" <e.de.castro@fairlightesp.com.au>
Date: 17 Oct 1997 03:20:30 GMT
Links: << >>  << T >>  << A >>


Peter <z80@ds.com> wrote in article
<3445db9c.5666487@news.netcomuk.co.uk>...
[SNIP]
> I am now looking at the M1 place & route software, but this is NT

Also runs on Win95.

> only. (It also does not support XC3000 but that is another story -
> apparently the next version will). This makes the old Viewdraw stuff a
> pain to use because its DOS extender does not run in a NT DOS box.
> 
> So I am looking at alternative schematic entry solutions which don't
> cost a fortune like Workview Office.
> 
> Protel Schematic 3.2 is not too bad as Windows schematic entry progs
> go. It comes with loads of Xilinx library parts. But it will not
> (AFAIK) emit XNF directly.

I'm using Protel 2.4 which does output XNF netlists although this is
an optional extra. XNF netlists may have been dropped from version 3,
but I think that would be unlikey. I do know however that Xilinx is 
moving towards EDIF format netlists which Protel already supports.



> Peter.
> 
> Return address is invalid to help stop junk mail.
> E-mail replies to z80@digiXYZserve.com but
> remove the XYZ.
> 
Article: 7804
Subject: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
From: "bertrand" <bertrand@prodigy.net>
Date: 17 Oct 1997 07:45:39 GMT
Links: << >>  << T >>  << A >>
The DB25 parallel port pinout and the 5 wire interface pinout are described
in the ISP section (section 8) of the 1996 data book. The latest
information is also available on the Lattice web page under ISP Hardware
and Software section. Specifically, the information that you are looking
for is contained within ISP Architecture and Programming document of this
section.

-- ISP is Lattice

Egon Bild <ebild@metronet.de> wrote in article
<3445200c.4725745@pop-news.metronet.de>...

> does somebody now the pinout of the Download Cable
> for In-System programming of LATTICE ispLSI? I have
> download the file "DLCABLE.PDF" from LATTICE ftp
> server, but there is no detailed pinout.

Article: 7805
Subject: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Fri, 17 Oct 1997 08:51:44 +0100
Links: << >>  << T >>  << A >>
Egon Bild wrote:
> 
>Ray Andraka  wrote:
> 
>>for the 8 pin Amp .100 SIP connector:
>>pin    description
>>1      VCC
>>2      SDO (from the device)
>>3      SDI (to the device)
>>4      /ispEN
>>5      Key (plugged hole in connector)
>>6      MODE
>>7      GND
>>8      SCLK
> 
>Thanks for your answer. The pinout for the 8 pin Amp .100 SIP
>connector is in the "dlcable.pdf" sheet to, but how does the
>25-pin parallel port adapter on the PC side look like ?

GIF emailed.  (This is a binary-free newsgroup!)

General comment for people considering using ipsLSI - I think the
Lattice starter kit is good value, particularly if you get it as part of
the deal for attending an introductory seminar/presentation.  I also
think Lattice pDS is lousy value.  Shame as I find the ICs useful.

Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions
Article: 7806
Subject: [Reposted due to Enlow UCE cancel]: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Fri, 17 Oct 1997 08:51:44 +0100
Links: << >>  << T >>  << A >>
Egon Bild wrote:
> 
>Ray Andraka  wrote:
> 
>>for the 8 pin Amp .100 SIP connector:
>>pin    description
>>1      VCC
>>2      SDO (from the device)
>>3      SDI (to the device)
>>4      /ispEN
>>5      Key (plugged hole in connector)
>>6      MODE
>>7      GND
>>8      SCLK
> 
>Thanks for your answer. The pinout for the 8 pin Amp .100 SIP
>connector is in the "dlcable.pdf" sheet to, but how does the
>25-pin parallel port adapter on the PC side look like ?

GIF emailed.  (This is a binary-free newsgroup!)

General comment for people considering using ipsLSI - I think the
Lattice starter kit is good value, particularly if you get it as part of
the deal for attending an introductory seminar/presentation.  I also
think Lattice pDS is lousy value.  Shame as I find the ICs useful.

Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions
========= WAS CANCELLED BY =======:

Rogue cancel from Michael Enlow, X-Cancelled-by etc. are forged.

Control: cancel <34471910.1240@ecs.soton.ac.uk.nojunk>
Article: 7807
Subject: Xilinx delay reports?
From: IJ.McCrum@ulst.ac.uk (I McCrum)
Date: Fri, 17 Oct 1997 08:56:15 GMT
Links: << >>  << T >>  << A >>
We are routing a largish design with a lot of buses and a high gate
usuage. The "highest clock Frequency" reported by the XACT system
seems to vary a lot depending on the original seed value, semmingly at
random!

1. Are the reported propagation delays accurate?
2. Is there any guidelines about choosing the seed apart from at
random?

TIA
Ian McCrum, lecturer University of Ulster, Northern Ireland
MAILTO:IJ.McCrum@ulst.ac.uk
-----------------------------------------------
Article: 7808
Subject: [Reposted due to Enlow UCE cancel]: Xilinx delay reports?
From: IJ.McCrum@ulst.ac.uk (I McCrum)
Date: Fri, 17 Oct 1997 08:56:15 GMT
Links: << >>  << T >>  << A >>
We are routing a largish design with a lot of buses and a high gate
usuage. The "highest clock Frequency" reported by the XACT system
seems to vary a lot depending on the original seed value, semmingly at
random!

1. Are the reported propagation delays accurate?
2. Is there any guidelines about choosing the seed apart from at
random?

TIA
Ian McCrum, lecturer University of Ulster, Northern Ireland
MAILTO:IJ.McCrum@ulst.ac.uk
-----------------------------------------------
========= WAS CANCELLED BY =======:

Rogue cancel from Michael Enlow, X-Cancelled-by etc. are forged.

Control: cancel <34472748.973586@news.u-net.com>
Article: 7809
Subject: PROM for FLEX10K
From: wehr@mikro.uni-stuttgart.de (Andreas Wehr)
Date: 17 Oct 1997 13:33:05 GMT
Links: << >>  << T >>  << A >>

Hi, 

can anybody tell me if there are serial EEPROMs available for 
ALTERA FLEX10K devices?

Thanks,
Andreas

Article: 7810
Subject: [Reposted due to Enlow UCE cancel]: PROM for FLEX10K
From: wehr@mikro.uni-stuttgart.de (Andreas Wehr)
Date: 17 Oct 1997 13:33:05 GMT
Links: << >>  << T >>  << A >>

Hi, 

can anybody tell me if there are serial EEPROMs available for 
ALTERA FLEX10K devices?

Thanks,
Andreas

========= WAS CANCELLED BY =======:

Rogue cancel from Michael Enlow, X-Cancelled-by etc. are forged.

Control: cancel <627peh$1vga@info4.rus.uni-stuttgart.de>
Article: 7811
Subject: Fast Fault Simulation
From: rcstwks@aol.com (RCSTWKS)
Date: 17 Oct 1997 18:31:49 GMT
Links: << >>  << T >>  << A >>
Fault-Simulation - Turbo Fault

High Performance Fault Simulator:

TurboFault combines high performance, versatility and accuracy. It is
highly competitive with hardware accelerators for classical test
fault grading. It supports synchronous and asynchronous designs at the
gate-level, including tri-state gates, latches, flip-flops, single and
multi-port RAMS, complex bus resolution functions, and USER Defined
primitives (UDPs). TurboFault reads Verilog gate-level netlists, and will
also read Standard Delay Format (SDF) timing files.

Advanced Cached-Concurrent Algorithm:

Turbofault utilizes a new algorithm optimed for today's computer
hardware that maximizes the simulation power of workstations. Syntest
Cached-Concurrent algorithm eliminates needless operations and with new
Fast Queque technology combines the best of unit delay and cycle-based
capabilities. No other fault simulator, hardware or software, matches the
performance of TurboFault.

TurboFault makes fault simulation an integral design tool for generating
a quality manufacturing test set. TurboFault supports single timing delay
for simulation accuracy and flexibility, without sacrificing speed.

TurboFault is the fastest concurrent fault simulator based on the latest
advances in cycle-based simulation technology. It simulates even *faster*
than existing expensive hardware accelerated fault simulators. Fault
simulation also consumes memory very quickly, so memory management is
critical. TurboFault combines efficient memory management with special
fault handling resulting in low memory consumption. 

To hear more of Turbo-Fault, please send an e-mail to
Suzanne@world.std.com, please send us your company name, your name 
and fax #. 

Thanks!

The staff at Syntest Technology.
Article: 7812
Subject: Re: Xilinx delay reports?
From: John McDougall <"john_mcdougall[no spam]"@geocities.com>
Date: Fri, 17 Oct 1997 15:01:45 -0400
Links: << >>  << T >>  << A >>
I McCrum wrote:
> 
> We are routing a largish design with a lot of buses and a high gate
> usuage. The "highest clock Frequency" reported by the XACT system
> seems to vary a lot depending on the original seed value, semmingly at
> random!
> 
> 1. Are the reported propagation delays accurate?
> 2. Is there any guidelines about choosing the seed apart from at
> random?
> 
> TIA
> Ian McCrum, lecturer University of Ulster, Northern Ireland
> MAILTO:IJ.McCrum@ulst.ac.uk
> -----------------------------------------------

The most acurate delays are reported by xdelay. It will be more acurate
than the values reported by ppr.

Random!!! You've got it. That seed is a seed to a random generation. 
************** Remove [ANTI_SPAM] to reply **************
Article: 7813
Subject: FREE APS EDA QUARTERLY NEWSLETTER END Q3 RELEASED
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 17 Oct 1997 17:57:56 -0400
Links: << >>  << T >>  << A >>
-----------------------------------------------------------------
           APS EDA NEWSLETTER RELEASE
-----------------------------------------------------------------

The APS EDA Quarterly Newsletter has been officially released.
You can see it at

 http://www.associatedpro.com/aps/NL_Q3_97.html.

Highlights from this quarters newsletter:

--The History of VHDL
--Using Named Associations in VHDL PORT MAPPING
--The Use Of FPGA Development Boards in the design process
--Undefined states in VHDL
--ATMELs new XILINX insertable FPGAs
--New LUCENT SHRINK WRAPPED FPGA DEVELOPMENT KITS
--NEW LOW COST VHDL SIMULATOR
--NEW LOW COSTS ON XILINX APSX84 BASE KITS
--Transitioning from 3V to 5V FPGAs
--Many links to new EDA tools and Products

As well as many other features and topics.

____________________________________________________________________________

In order to subscribe to the EDA newsletter, Please send an EMAIL to:
EDA@associatedpro.com with the words EDA SUBSCRIBE or EDA UNSUBSCRIBE
and you will be added or subtracted from our EDA list.

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7814
Subject: Re: Xilinx delay reports?
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 17 Oct 1997 18:13:35 -0400
Links: << >>  << T >>  << A >>
I McCrum wrote:
> 
> We are routing a largish design with a lot of buses and a high gate
> usuage. The "highest clock Frequency" reported by the XACT system
> seems to vary a lot depending on the original seed value, semmingly at
> random!
> 
> 1. Are the reported propagation delays accurate?
> 2. Is there any guidelines about choosing the seed apart from at
> random?
> 
> TIA
> Ian McCrum, lecturer University of Ulster, Northern Ireland
> MAILTO:IJ.McCrum@ulst.ac.uk
> -----------------------------------------------
The delays reported by xdelay are more accurate than those reported by
PPR.  The XDELAY values are quite accurate for worst case.  The seed
value is indeed a random number generator seed.  You can get more
consistent and generally better delays by floorplanning the design,
which can be done using RLOC attributes, by entering the placement in a
constraints file or by using the XACT 6 floorplanner (which creates a
constraints file).  Floorplanning takes the variability due to placement
out of the equation.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 7815
Subject: [Reposted due to Enlow UCE cancel]: Re: Xilinx delay reports?
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 17 Oct 1997 18:13:35 -0400
Links: << >>  << T >>  << A >>
I McCrum wrote:
> 
> We are routing a largish design with a lot of buses and a high gate
> usuage. The "highest clock Frequency" reported by the XACT system
> seems to vary a lot depending on the original seed value, semmingly at
> random!
> 
> 1. Are the reported propagation delays accurate?
> 2. Is there any guidelines about choosing the seed apart from at
> random?
> 
> TIA
> Ian McCrum, lecturer University of Ulster, Northern Ireland
> MAILTO:IJ.McCrum@ulst.ac.uk
> -----------------------------------------------
The delays reported by xdelay are more accurate than those reported by
PPR.  The XDELAY values are quite accurate for worst case.  The seed
value is indeed a random number generator seed.  You can get more
consistent and generally better delays by floorplanning the design,
which can be done using RLOC attributes, by entering the placement in a
constraints file or by using the XACT 6 floorplanner (which creates a
constraints file).  Floorplanning takes the variability due to placement
out of the equation.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
========= WAS CANCELLED BY =======:

Rogue cancel from Michael Enlow, X-Cancelled-by etc. are forged.

Control: cancel <3447E30F.5C64@ids.net>
Article: 7816
Subject: XILINX Severe Gate minimisation within XACT 6 problem/question?
From: Tony Cooper <tony.cooper@virgin.net>
Date: Sat, 18 Oct 1997 10:38:33 +0100
Links: << >>  << T >>  << A >>
Hi all,
Firstly you will have to excuse me if I make some newsgroup fopars, as
this is the first time I have used the news system....

Anyways, has anyone had a problem as follows.

AND2B1 gates wrongly being minimised out by XBLOX to be a connection to
ground rather than a bit of wire?

I have a medium design that uses a lot of busses between counters. Each
bit of every counter uses a block that I have designed which is
basically a T-Type ff with a MUX that allows either data to be loaded
into the ff or allows the ff to toggle. I have reported the problem to
XILINX UK, and they are having the same minimisation problem. It seems
that any AND2b1 used in this configuration gets removed.

Is it me or has any one else had this problem - as if it is a bug, then
it could prove problematic to fix.

If anyone is interested give me a shout and I will email them the
schematic (The schematic is only 4 gates, a ff, and a handfull of pins,
so it is quite small).

Look forward to a responce.

TOny
-- 
Sent By tony.cooper@virgin.net

Article: 7817
Subject: [Reposted due to Enlow UCE cancel]: XILINX Severe Gate minimisation within XACT 6 problem/question?
From: Tony Cooper <tony.cooper@virgin.net>
Date: Sat, 18 Oct 1997 10:38:33 +0100
Links: << >>  << T >>  << A >>
Hi all,
Firstly you will have to excuse me if I make some newsgroup fopars, as
this is the first time I have used the news system....

Anyways, has anyone had a problem as follows.

AND2B1 gates wrongly being minimised out by XBLOX to be a connection to
ground rather than a bit of wire?

I have a medium design that uses a lot of busses between counters. Each
bit of every counter uses a block that I have designed which is
basically a T-Type ff with a MUX that allows either data to be loaded
into the ff or allows the ff to toggle. I have reported the problem to
XILINX UK, and they are having the same minimisation problem. It seems
that any AND2b1 used in this configuration gets removed.

Is it me or has any one else had this problem - as if it is a bug, then
it could prove problematic to fix.

If anyone is interested give me a shout and I will email them the
schematic (The schematic is only 4 gates, a ff, and a handfull of pins,
so it is quite small).

Look forward to a responce.

TOny
-- 
Sent By tony.cooper@virgin.net

========= WAS CANCELLED BY =======:

Rogue cancel from Michael Enlow, X-Cancelled-by etc. are forged.

Control: cancel <34488399.25B2@virgin.net>
Article: 7818
Subject: Q: Clocking for address decode/chip select.
From: janovetz@ews.uiuc.edu (Jacob W Janovetz)
Date: 18 Oct 1997 16:43:33 GMT
Links: << >>  << T >>  << A >>
Hello.

   I am using a Xilinx 4008E on the address bus of a Motorola 68360.
I have some address pins and two chip selects from the 360 going to
the 4008E.  CS4 goes to a SGCK.  CS5 goes to an I/O pin.  I'm using
Exemplar Leonardo to do VHDL synthesis.

   When data is written to the 4008E, I have the VHDL look like:

if (cs5'event and cs5='1') then
 ...
end if

   This searches for the rising edge of CS5 to latch the data.
Leonardo wants to add a BUFG to port cs5 for (I guess) obvious
reasons.  This will not get placed & routed by Xilinx software
because I don't have CS5 routed to a GCK pin.  However, I can
modify the resulting XNF file and change the BUFG to a IBUF and
it will place & route and work fine.
   I can do the same thing for CS4, but keep the BUFG in place
and I get similar timing.  The code is very small and therefore,
CS5_INT (internal signal in the FPGA) is not routed to many 
logic blocks.  Therefore, its load is somewhat small.

   My question is this: Why does Leonardo add the BUFG to the 
pin?  It isn't necessary, right?  It just helps in making timing
a little better.  Because I don't have CS5 connected to a GCK,
how can I force Leonardo (through VHDL) to connect it to a 
standard IBUF?  Should I define the IBUF as a component in VHDL?

   Thanks for any notes on this.  Perhaps someone can recommend
a different way to handle this, too...

    Cheers,
    Jake

--
   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
 University of Illinois | your eyes turned skyward, for there you have been,
                        | there you long to return.     -- da Vinci
        PP-ASEL         | http://www.cen.uiuc.edu/~janovetz/index.html
Article: 7819
Subject: cmsg cancel <34488399.25B2@virgin.net>
From: rra@eyrie.org,sw@eyrie.org,rgm@eyrie.org
Date: Sun, 19 Oct 1997 07:43:41 GMT
Links: << >>  << T >>  << A >>

The article was canceled on 10/19/97 at 3:33:54 AM with the Usenet Cancel Engine (UCE).
Article: 7820
Subject: cmsg cancel <3447E30F.5C64@ids.net>
From: rra@eyrie.org,sw@eyrie.org,rgm@eyrie.org
Date: Sun, 19 Oct 1997 07:44:33 GMT
Links: << >>  << T >>  << A >>

The article was canceled on 10/19/97 at 3:34:33 AM with the Usenet Cancel Engine (UCE).
Article: 7821
Subject: cmsg cancel <627peh$1vga@info4.rus.uni-stuttgart.de>
From: rra@eyrie.org,sw@eyrie.org,rgm@eyrie.org
Date: Sun, 19 Oct 1997 07:44:53 GMT
Links: << >>  << T >>  << A >>

The article was canceled on 10/19/97 at 3:35:00 AM with the Usenet Cancel Engine (UCE).
Article: 7822
Subject: cmsg cancel <34472748.973586@news.u-net.com>
From: rra@eyrie.org,sw@eyrie.org,rgm@eyrie.org
Date: Sun, 19 Oct 1997 07:45:27 GMT
Links: << >>  << T >>  << A >>

The article was canceled on 10/19/97 at 3:35:31 AM with the Usenet Cancel Engine (UCE).
Article: 7823
Subject: cmsg cancel <34471910.1240@ecs.soton.ac.uk.nojunk>
From: rra@eyrie.org,sw@eyrie.org,rgm@eyrie.org
Date: Sun, 19 Oct 1997 07:45:59 GMT
Links: << >>  << T >>  << A >>

The article was canceled on 10/19/97 at 3:36:14 AM with the Usenet Cancel Engine (UCE).
Article: 7824
Subject: FPGA Answer to ci12103@mailbox.calypso.net
From: "Karl Andersson" <fd@ddd.com>
Date: Sun, 19 Oct 1997 21:25:00 +0100
Links: << >>  << T >>  << A >>
 Please Help..

We are working on a project whit the ALTERA Chips
But the we need more" Logic Blocks" i think we need 15 000 .
On each "Block" we only use very litle of the functions.

Is there some other way to do this?

(We will pay for help if you can design it for us)

Thanks..

 Per






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1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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