Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 6750

Article: 6750
Subject: Need Good IC Schematics to Chip Layout Engineer
From: Bharat Kurani <Bharat.Kurani@add.ssw.abbott.com>
Date: Mon, 23 Jun 1997 13:53:54 -0700
Links: << >>  << T >>  << A >>
Hello

I am looking for good IC Schematics to Chip Layout 
Engineer and am unable to find one.

Does any one know of good layout engineer in Silicon
Valley. San Francisco Area

Thanks

bharat
408 567 3435
Bharat.Kurani@add.ssw.abbott.com
Article: 6751
Subject: Query: Anyone ever install Xilinx Foundation on a Jaz drive? If so how?
From: vsrd@airmail.net (Stephen)
Date: Tue, 24 Jun 1997 06:07:40 GMT
Links: << >>  << T >>  << A >>
All attempts to install Foundation software to a Jaz drive
unsuccessful.  If anyone has ever succeeded in doing this I would
appreciate learning how it is done.  Thanks. 

Stephen Vale
vsrd@airmail.net
Article: 6752
Subject: Re: Help: Two's complement multiplier in ORCA FPGA
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Tue, 24 Jun 1997 12:53:00 GMT
Links: << >>  << T >>  << A >>
On Mon, 23 Jun 1997 17:56:09 +0200, Jonas Thor
<i93-jtr@jota.sm.luth.se> wrote:

>I guess this is becuase there are no ORCA macros for two's complement
>multipliers...- If so, could anyone please give me a hint how to best
>implement a two's complement multiplier in ORCA FPGA?

For large multipliers, modified booth triplet is probably the best,
with some induced parallalism. If a different multiplier &
multiplicand is required every cycle, then each partial double term
generated needs a 5 input, two output function, which is neatly done
in a single ORCA PFU. (5 input functions are pretty fast in ORCA).
This will give you the correct bit shift, and an add/sub decision
result. Booth triplet is nice, as it halves the maximum number of
additions required when compared with conventional add/pass/subtract
implementations, which is often what synthesis gives, although I
recall that Synplify does introduce some parallelism.

If a fixed value multiplier is used every time, on a varying
multiplicand, then pre-applying the booth triplet and creating your
own fixed multiplier is very efficient, just as it can be with
unsigned multipliers. Induced parallelism helps to reduce the critical
path, as of course will pipelining.

Stuart
Article: 6753
Subject: lattice / synario and smatmodels
From: david.surphlis@gecm.com
Date: 24 Jun 1997 14:03:37 GMT
Links: << >>  << T >>  << A >>
to whom it may concern.
	
	I have a problem attaching jedec files compiled from abel software 
on the synario package to the mentor system. 
	synopsys application hotline assisted me to some extent, but would 
like to hear from any-one else who had a simlar problem.




                                Thanks Davey


Article: 6754
Subject: ASIC/FPGA in Boston?
From: "Hakan Thyr" <hakan@ziplink.net>
Date: 24 Jun 1997 15:10:03 GMT
Links: << >>  << T >>  << A >>
Hello,

I am arranging a visit to the Boston area for an international group. They
are among other things interested in visiting companies involved in
ASIC/FPGA development. As this is not my field, I would like to ask this
group for ideas. What companies in the Boston area would be interesting to
visit? Any information is welcome. Please respond by email. Thanks in
advance.

Sincerely,

Hakan Thyr
hakan@worldknowledge.com
Article: 6755
Subject: universities offering real-time
From: deepu@fractal.ee.vill.edu (Deependra Talla)
Date: 24 Jun 1997 17:15:24 GMT
Links: << >>  << T >>  << A >>


--
--------------------------------------------------------------------------------
			Deependra Talla

Res:                                     Off:

Apt. # R - 635,                          Graduate Assistant
Sugartown Mews,                          Room. 426A, Tolentine Hall
Devon,                                   Dept. of Elec & Comp Engg.
PA 19333.                                Villanova University
                                         Villanova
                                         PA 19085   

Ph: (610) 225 - 0243                     Ph: (610) 519 - 4295

                       email: deepu@ece.vill.edu
--------------------------------------------------------------------------------
Article: 6756
Subject: Re: FPGA prototype board
From: aaps@erols.com
Date: Tue, 24 Jun 1997 22:05:48 -0400
Links: << >>  << T >>  << A >>
Steve,

APS makes a low cost board with just what you are asking. It can take
any of the XILINX 52xx and 40xx series chips and comes with an FPGA
installed. It can work both in a PC (ISA BUS) or stand alone. The board
has an on board 8255 IO chip, an oscillator socket, prom socket,  on
board timer chip,  status LEDs, and a through hole prototype area, as
well as 4 20 pin IDC connectors which bring all the useable pins of the
FPGA out to pins. 

The board comes with schematics, download software, VHDL examples, and C
code control program boilerplates. The board can also be purchased with
XILINX foundation software in four configurations at VERY LOW PRICES.

They can be seen at http://www.erols.com/aaps






Steve Martindell wrote:
> 
> I'm looking for a board that would have a Xilinx or Altera FPGA(either
> soldered or socketed) with all the FPGA I/O pins brought out to a
> connector(s). A board like this would allow me to quickly protype
> designs without having to send out to a board-shop. Does anyone
> know of a company that makes a product like this?
> 
>    thanks,
>           Steve Martindell
>           s-martindell@ti.com
Article: 6757
Subject: Asynchronous Peripheral Download Mode, Probs
From: Erik Lins <Erik.Lins@exp2.physik.uni-giessen.de>
Date: Wed, 25 Jun 1997 11:00:31 +0200
Links: << >>  << T >>  << A >>
Hi everyone,

I have some trouble with that asynchronous peripheral mode. I can
download the header and the first two frames, then within the third
byte  of the next frame /INIT goes low -> frameerror, I think. That
occurs always within the 74th byte transfer, independant of the design
file (I testet two completely different designs) and independant of the
length count (I modified the length count by hand, just for testing).
BTW: It's a 4013PQ208-6
The download of both files with the XChecker cable works well.
Usually the Xilinx should stop CCLK after detecting a frameerror and
forcing /INIT to go low, but CCLK continous after any following byte
transfer.
I don't use CRC-checking (normal 0110 at end of each frame).

Has anybody any idea ??? Or even had the same problem ?

Thanx,

Erik
Article: 6758
Subject: Info on VHDL
From: scassell@nospam.stud.unipg.it (Gianpaolo Scassellati)
Date: Wed, 25 Jun 1997 10:51:22 GMT
Links: << >>  << T >>  << A >>
Hi there,

	I am learning VHDL but I have some troubles. In particular, I
need to know where I can find a online manual on the net, and if there
are any specific newsgroups on VHDL.

Bye.
	Gianpaolo
Article: 6759
Subject: Re: Info on VHDL
From: David Bishop <dbishop@kodak.com>
Date: Wed, 25 Jun 1997 09:14:05 -0400
Links: << >>  << T >>  << A >>
Gianpaolo Scassellati wrote:

>         I am learning VHDL but I have some troubles. In particular, I
> need to know where I can find a online manual on the net, and if there
> are any specific newsgroups on VHDL.

On line manual?  Try the VHDL Cookbook
http://www.cs.adelaide.edu.au:80/~petera/designers-guide/DG.html
Newsgroup?
news:comp.lang.vhdl

-- 
                            David Bishop

INTERNET: dbishop@kodak.com                | The opinions voiced are
mine
US MAIL:  1194 West Ave, Hilton NY 14468   | and not my company's.
PHYSICAL: 43:17:17N 77:47:37E 281'         |
Article: 6760
Subject: Are Xilinx 4000XL I/O's truly 5V tolerant?
From: salix@clark.net (SALIX Technologies - Dan Simpkins)
Date: 25 Jun 1997 13:22:01 GMT
Links: << >>  << T >>  << A >>
 
Has anybody used Xilinx 3.3V XC4000XL devices in a mixed 5V/3V system?  
I am trying to find out if the "5V tolerant" I/O's on the XC4000XL 
devices can be driven from a low-impedance (i.e. CMOS) 5V source, or can 
only be driven from a higher-impedance TTL-style 5V source. 
 
The published information from Xilinx has been changing as the parts 
have gone from lab to production.  Here is a brief timeline: 
 
    - The 9/18/96 XC4000 family data sheet says the 4000XL inputs can be 
      driven from a CMOS 5V source "...if the dedicated 5-Volt supply
      pad(VTT) is tied to 5V." 
 
    - A "Technical Support Solutions Database" record at the Xilinx web
      site (record #1942, which Xilinx tech support told me was entered
      on 2/21/97) states that "VTT connections were anticipated 5 volt
      connections to allow the 3.3volt XL devices to properly interface
      the IO to other 5 volt devices. Later testing realized that these
      were not necessary so, the Pins marked VTT are currently not
      bonded N.C."  (All grammatical errors have been faithfully
      reproduced.) 
 
    - A 3/1/97 Xilinx app note entitled "3.3 V and Mixed Voltage
      Compatible Products" states that "The I/O structures of the
      XC4000XL FPGAs have been designed to tolerate being driven to a 5 
      V rail by a low-impedance source.  These 3.3V FPGAs can be
      directly driven by 5 V devices with either TTL or CMOS outputs." 
 
    - The "Features" section of the 3/25/97 XC4000XL data sheet says 
      the inputs are "5V tolerant", and makes no mention of a VTT pin. 
 
    - The 5/30/97 version of the XC4000XL data sheet lacks the 
      "Features" cover sheet of its predecessor, but in its absolute
      maximum ratings table gives VCC max as 4.0V, and VIN max as 5.5V.
      However, the VIN spec references a footnote that states "Maximum
      DC overshoot or undershoot above Vcc or below GND must be limited
      to either 0.5V or 10 mA..." 
 
While I suspect this last item was just a copy/paste mistake, it was 
troubling enough that I looked for some more information on the Xilinx 
web site.  Much of what I found stated that the XC4000XL inputs were TTL 
compatible, but there was nothing recent which said anything about true 
5V CMOS compatibility. 
 
I've been in touch with the Xilinx tech support hotline via email and 
telephone, and so far the information I have received has been ambiguous 
at best.  One of the tech support reps simply emailed back exactly what 
was written in the data book, despite my pointing out that this was 
contradicted by subsequent information.  Another told me that he asked 
the XC4000 product manager, who told him that they were truly 5V 
tolerant (not 3.7V tolerant), but he was unable to provide me with any 
written documentation or the name of the person to whom he spoke, only 
that it was the "product manager". 
 
So, my question is:  Has anybody actually used a 3.3V Xilinx XC4000XL 
part with true CMOS 5V drivers at the device inputs? 
 
Thanks in advance, 
Mike Coren 
Staff Engineer 
SALIX Technologies, Inc. 
 
_______________________________________________________________________ 
    =========    
   ===========   SALIX Technologies, Inc.    mailto:salix@clark.net 
  ============   9400 Key West Avenue        http://www.salixtech.com 
  ============   Suite 275                   TEL:  (301) 738-8284 
  ==  ==== ==    Rockville, MD  20850        FAX:  (301) 738-8289 
       ==         
       ===       "...Innovative technology for the 90s and beyond." 
 
         The statements contained herein are strictly those of  
         their author, and unless otherwise specifically indicated  
         should not be attributed to SALIX or its management. 

--
____________________________________________________________________________
    =========           SALIX Technologies, Inc.
   ===========          9400 Key West Avenue, Suite 275
  ============          Rockville, MD  20850
Article: 6761
Subject: Re: Asynchronous Peripheral Download Mode, Probs
From: Steve Gross <gross@pa.msu.edu>
Date: Wed, 25 Jun 1997 09:53:56 -0400
Links: << >>  << T >>  << A >>
Erik Lins wrote:
> 
> Hi everyone,
> 
> I have some trouble with that asynchronous peripheral mode. I can
> download the header and the first two frames, then within the third
> byte  of the next frame /INIT goes low -> frameerror, I think.

From my experience with XC4ke parts, there are two things to worry
about:

1. Byte download rate.  Watch the RDY/BUSY line, which tells you
   when byte "n" has been absorbed and the device is ready for
   byte "n+1."  I have found the byte download rate to be rather
   slow in these devices, down in the 100kBytes/second range.  
   There is a CCLK speed bit which can be set in the bitstream
   which should allow a higher byte download rate (for all bytes
   *following* this bit...)

   This is well documented in the Xilinx data books and I expect
   it is not your problem.

2. Timing of the PROG* pin.  There are 2 aspects of PROG* pin 
   timing.  First, how long should the pin remain LOW?  Next, how
   long after the rising edge of PROG* should one wait before writing
   the first byte of the header?  Neither of these times are specified
   in the Xilinx data book.  Worse, there is no handshaking to allow
   the device to inform the "master" that it is OK to take PROG*
   high or write the first byte of the header.  I had half expected
   the RDY/BUSY line to tell me when it was OK to write the first 
   byte of the header, but it doesn't.  

   I have used software delays on the order of milliseconds to 
   drive both of these times, following some trial-and-error
   experimentation.

   If I am wrong on the lack of specification or lack of handshaking
   on this issue, I would be glad to be corrected!  

Note that the only time INIT can go low is at a frame boundary.  If
you see INIT going low at a point other than a frame boundary, start
to suspect byte timing or PROG* timing.  

Good luck.

-Steve Gross
Article: 6762
Subject: Re: Java and Giga Ops FPGA Boards
From: Philip James-Roxby <P.B.James-Roxby@bham.ac.uk>
Date: Wed, 25 Jun 1997 16:09:38 +0100
Links: << >>  << T >>  << A >>
Steven Guccione wrote:

> See http://www.vcc.com/  They have a Xilinx 6200-based board that has
> full
> Java support and does remote access pretty painlessly.  Comes with
> WebScope, a remote debug tool, also  implemented in Java.
>

Also, I have Derek, a Java based tool for peering in at the 6200 when it
sits on VCCs HotWorks card.  Anyone is free to use that.  Derek lives at
http://www.eee.bham.ac.uk/James-RoxbyP/derek.htm

Phil



Article: 6763
Subject: Intel PLD programmer
From: "Anthony Marchini" <tonym@epix.net>
Date: 25 Jun 1997 16:14:35 GMT
Links: << >>  << T >>  << A >>
A while back ( 4 years?) intel was giving away
its PLD software for its line of programmable logic.
I was wondering if anyone still has the program set
and if they could sent it to me. 

-- 
Anthony Marchini
Electronic Design Engineer
American Locker Security Systems
www.americanlocker.com
Article: 6764
Subject: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
From: "Tom Burgess" <tburgess@drao.nrc.ca>
Date: 25 Jun 1997 17:07:43 GMT
Links: << >>  << T >>  << A >>


SALIX Technologies - Dan Simpkins <salix@clark.net> wrote in article
<5or61p$26a@clarknet.clark.net>...
>  
<deleted> 
>  
> So, my question is:  Has anybody actually used a 3.3V Xilinx XC4000XL 
> part with true CMOS 5V drivers at the device inputs? 
>  

The fact that someone has done this without disaster is necessary but not
sufficient proof that it is safe to do so. The latest
XCELL (#25, 2nd Q/97) contains an encouraging statement: (p. 21): "The I/O
structures of the XC4000XL FPGAs have been
designed to tolerate being driven to a 5V rail by a low-impedance source.
.. Power supply sequencing is not a problem; the
inputs can be driven to 5V either before or after the 3.3 Vcc power is
supplied without risking damage to the devices."
(another quote for your timeline :). Still would be nice to see this on the
data sheet, though.

	regards, tom
	tburgess@drao.nrc.ca

Article: 6765
Subject: FPGA prototype board
From: a840272@# Replace this line with your news domain (Steve Martindell)
Date: 25 Jun 1997 21:26:37 GMT
Links: << >>  << T >>  << A >>
I'm looking for a board that would have a Xilinx or Altera FPGA(either 
soldered or socketed) with all the FPGA I/O pins brought out to a
connector(s). A board like this would allow me to quickly protype 
designs without having to send out to a board-shop. Does anyone 
know of a company that makes a product like this?

   thanks,
          Steve Martindell
          s-martindell@ti.com
Article: 6766
Subject: Re: FPGA prototype board
From: janovetz@coewl.cen.uiuc.edu (Jacob W Janovetz)
Date: 25 Jun 1997 22:57:57 GMT
Links: << >>  << T >>  << A >>
a840272@# Replace this line with your news domain (Steve Martindell) writes:

>I'm looking for a board that would have a Xilinx or Altera FPGA(either 
>soldered or socketed) with all the FPGA I/O pins brought out to a
>connector(s). A board like this would allow me to quickly protype 
>designs without having to send out to a board-shop. Does anyone 
>know of a company that makes a product like this?


   Both companies make evaluation boards for a limited number of their
devices.  Altera just started making one for educational use that has
a CPLD and one of their FLEX 10K devices on it.  I've seen it, but 
haven't used it.  I have used the Xilinx ones, though.  They include
a download cable that attaches to a PC.

    Cheers,
    Jake

--
janovetz@coewl.cen.uiuc.edu| Once you have flown, you will walk the earth with
   University of Illinois  | your eyes turned skyward, for there you have been,
                           | there you long to return.     -- da Vinci
          PP-ASEL          | http://www.cen.uiuc.edu/~janovetz/index.html
Article: 6767
Subject: FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!
From: Karl Kristianson <KarlKristian@ntr.net>
Date: Wed, 25 Jun 1997 18:00:59 -0600
Links: << >>  << T >>  << A >>
FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!

A new copy of Cadkey '97 is selling on the street for $1,195. To 
guarantee updates for the next year costs $350 more, bringing it up to 
$1,545 total!

We have available over 100 NEW copies of Cadkey 6.0 on CD for DOS in  
unopened, shrinkwrapped boxes with all manuals & documentation; which can 
be upgraded to Cadkey '97, INCLUDING the year's worth of free updates, 
for the street price of $595.

That's $950 LESS than the normal street price!

Or, maybe Cadkey 6.0 has enough power for you with no upgrade at all! 
(Cadkey '97 is basically Cadkey 8.0)

We're selling these for $250 each, so you save $700 over the normal 
street price of Cadkey '97! ($1,545 minus $595 upgrade price minus our 
price of $250 equals $700 savings!)

If you would like more info on Cadkey 97, here's Cadkey 97's Web page: 
http://www.cadkey.com/cadkey/index.htm

Thanks!

Karl Kristianson
DreamQuest
Article: 6768
Subject: Re: Any designs to avoid in FPGAs
From: !@(nospam)@vcd.hp.com (J.Szamosfalvi)
Date: 26 Jun 1997 01:11:32 GMT
Links: << >>  << T >>  << A >>
Phani Putrevu (pputrevu@ececs.uc.edu) wrote:
: Hi,

: I was wondering if there are a class of circuits/systems that I should 
: not implement using FPGAs. 

If you can have the equivalent circuit for lot less (ie: an 8051, Z80, etc.)

: I am told that floating point units dont perform well when implemented 
: using FPGAs. In fact a multiplier that I had implemented required 200ns 
: (16 bit). Present day CPUs have much better FPUs/ALUs.

I'd say that's implementation dependent.  Did you use a Wallace tree 
for your multiplier?


---
#include <Standard.Disclaimer> about this post being a personal opinion
Article: 6769
Subject: Re: FPGA prototype board
From: jhallen@world.std.com (Joseph H Allen)
Date: Thu, 26 Jun 1997 04:45:19 GMT
Links: << >>  << T >>  << A >>
In article <5os7pl$247$1@vixen.cso.uiuc.edu>,
Jacob W Janovetz <janovetz@coewl.cen.uiuc.edu> wrote:
>a840272@# Replace this line with your news domain (Steve Martindell) writes:

>>I'm looking for a board that would have a Xilinx or Altera FPGA(either 
>>soldered or socketed) with all the FPGA I/O pins brought out to a
>>connector(s). A board like this would allow me to quickly protype 
>>designs without having to send out to a board-shop. Does anyone 
>>know of a company that makes a product like this?

>   Both companies make evaluation boards for a limited number of their
>devices.  Altera just started making one for educational use that has
>a CPLD and one of their FLEX 10K devices on it.  I've seen it, but 
>haven't used it.  I have used the Xilinx ones, though.  They include
>a download cable that attaches to a PC.

For a number of projects, I've hand wired boards which contain a PLCC Xilinx
and a timer circuit which allows the it to configured over a serial cable.
I've found this to be very useful: you first configure the Xilinx and then a
UART in the configuration can communicate with the computer over the serial
cable.  Of course the computer can be anything with an rs-232 port.

If there's interest, I'll run off a bunch of these off with a prototyping
area. I would like to do it, but I want to be able to sell enough of them to
pay the board house bill.  Basically, if I can sell at least 10 of them for
$100 each I'll do it.

A few other features might be:

 - able to power the FPGA with rs-232 signal lines as well as external power
   from a wall adaptor
 - led which indicates that the configuration has occured
 - can cause reconfiguration with change in DTR line status
 - Xilinx pins are on an IDC connector, which can be used for jumpers or
   cables as well as prototype wire-wraps.
 - cheap FPGA included
 - Socket for configuration prom and jumper option for master serial mode
   configuration.
 - Pads for a crystal and a socket for an oscillator can

 - I would include the board, software for PC and UNIX (including source) to
   download the configuration data, and a UART example in OrCAD, ActiveCAD
   and maybe Viewlogic formats (I have the OrCAD and Foundation devlopement
   systems, and 45 runs of Viewlogic left on my key :-)

Should I use the 68 pin or 84 pin PLCC socket?
How big should it be?

It would also be useful to make an ISA bus Xilinx prototype card, but that
interests me less at the moment.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 6770
Subject: Re: Any designs to avoid in FPGAs
From: Ray Andraka <randraka@ids.net>
Date: Thu, 26 Jun 1997 09:19:22 -0400
Links: << >>  << T >>  << A >>
nospam J.Szamosfalvi wrote:
> 
> Phani Putrevu (pputrevu@ececs.uc.edu) wrote:
> : Hi,
> 
> : I was wondering if there are a class of circuits/systems that I should
> : not implement using FPGAs.
> 
> If you can have the equivalent circuit for lot less (ie: an 8051, Z80, etc.)
> 
> : I am told that floating point units dont perform well when implemented
> : using FPGAs. In fact a multiplier that I had implemented required 200ns
> : (16 bit). Present day CPUs have much better FPUs/ALUs.
> 
> I'd say that's implementation dependent.  Did you use a Wallace tree
> for your multiplier?

Depending on the particular FPGA, there are better architectures than a
wallace tree for multipliers that take advantage of the architecture. 
Remember, the routing in an FPGA is a limiting factor for  speed.  For
example, a Xilinx 4K series -2 part can do 12 bit fixed point multiplies
at better than 40 MHz with a four clock latency.  A wallace tree design
is considerably slower and uses more area because of the poor
architectural fit.

Floating point is normally a poor fit for FPGAs, as the hardware is
considerably more complex than the equivalent fixed point hardware. 
Granted, a fixed point design requires the designer to do his homework
up front, but in my opinion the resulting performance and density is
worth it (and the results are potentially more accurate to boot).  

Generally speaking there are two limits to what can/should go in an
FPGA.  The lower limit is defined by the cost.  If there is a cheaper
solution that meets the required functionality and performance, it
doesn't make sense to use the FPGA.  An example of this is a design that
will run on a conventional microprocessor/DSP processor at the desired
data rate.  

The other end of the spectrum is defined by the clocking limits of the
FPGA.  Practically speaking, you are limited to clocks under about
100MHz for an FPGA design (certain carefully done designs can
significantly exceed 100 MHz, but for general stuff that is an upper
limit).  Now, an FPGA being clocked at say 30-40MHz can outperform a
microprocessor running at 200MHz, since the circuit can be designed to
handle the entire function on every clock cycle instead of one basic
function per instruction (ahh, the beauty of custom hardware).  

A third dimension that may come into play, is the somewhat limited
number of gates available for a design.  This can be alleviated somewhat
by using multiple devices and properly partitioning the design.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 6771
Subject: Re: FPGA prototype board
From: sds@cardinal.cs.wustl.edu (Stephen D. Scott)
Date: 26 Jun 1997 09:28:58 -0500
Links: << >>  << T >>  << A >>
Steve Martindell wrote:
> I'm looking for a board that would have a Xilinx or Altera FPGA(either
> soldered or socketed) with all the FPGA I/O pins brought out to a
> connector(s). A board like this would allow me to quickly protype
> designs without having to send out to a board-shop. Does anyone
> know of a company that makes a product like this?
> 
>    thanks,
>           Steve Martindell
>           s-martindell@ti.com

See http://www.io.com/~guccione/HW_list.html for a list of commercial and
university-based FPGA boards.

Stephen

--
Stephen D. Scott                                     sds@cs.wustl.edu
Department of Computer Science                        535 Jolley Hall
Washington University, Campus Box 1045          phone: (314) 935-4425
One Brookings Drive                               fax: (314) 935-7302
St. Louis, MO  63130-4899          URL: http://www.cs.wustl.edu/~sds/
Article: 6772
Subject: Re: Info on VHDL
From: sds@cardinal.cs.wustl.edu (Stephen D. Scott)
Date: 26 Jun 1997 09:33:42 -0500
Links: << >>  << T >>  << A >>
Gianpaolo Scassellati wrote:
>Hi there,
>
>        I am learning VHDL but I have some troubles. In particular, I
>need to know where I can find a online manual on the net, and if there
>are any specific newsgroups on VHDL.
>
>Bye.
>        Gianpaolo

http://server.vhdl.org/viuf/ is the home of the VHDL International
Users' Forum and has lots of good information, including an extensive
FAQ with a list of VHDL books.  http://www.erols.com/aaps/x84lab/ has a
VHDL tutorial, but I haven't tried it myself so I cannot vouch for it.
Finally, try the newsgroup comp.lang.vhdl.

Stephen

--
Stephen D. Scott                                     sds@cs.wustl.edu
Department of Computer Science                        535 Jolley Hall
Washington University, Campus Box 1045          phone: (314) 935-4425
One Brookings Drive                               fax: (314) 935-7302
St. Louis, MO  63130-4899          URL: http://www.cs.wustl.edu/~sds/
Article: 6773
Subject: Tight Teen Snatch * teen1.jpg
From: asd;ofj@alskdjf.com
Date: 26 Jun 1997 14:55:50 GMT
Links: << >>  << T >>  << A >>

Are you ready to look at pictures of Teens fucking and sucking?  


Then cum visit:





                http://www.sexy-girls.com






All models represented on Sexy-Girls are 18 years of Age or Older.



Article: 6774
Subject: Re: FPGA prototype board
From: Leon Heller <leon@lfheller.demon.co.uk>
Date: Thu, 26 Jun 1997 18:49:42 +0100
Links: << >>  << T >>  << A >>
In article <5os2ed$kk6@hammerhead.dadd.ti.com>, a840272@#.? writes
>I'm looking for a board that would have a Xilinx or Altera FPGA(either 
>soldered or socketed) with all the FPGA I/O pins brought out to a
>connector(s). A board like this would allow me to quickly protype 
>designs without having to send out to a board-shop. Does anyone 
>know of a company that makes a product like this?

I'm working on a low-cost reconfigurable computing module, with a Xilinx
XC6216 and four 1 MBit SRAMs. Some details are on my Web pages.

Leon
-- 
Leon Heller
Amateur radio callsign: G1HSM
Email: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk
Tel: +44 (0) 118 947 1424 (home) +44 (0) 1344 385556 (work)


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search