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Messages from 13550

Article: 13550
Subject: BCD 2 Binary
From: "Yong-il Yoon" <yiyoon@add.co.kr>
Date: Wed, 9 Dec 1998 16:16:49 +0900
Links: << >>  << T >>  << A >>
I have to implement 3 digit BCD(000-999,12bit) to binary(0x000-0x3E7)
conversion logic on Vantis CPLD(MACH???).
I need ABEL source code or Boolean Eq.
Anybody knows where I can get it?

Thanks..

Yoon.

Article: 13551
Subject: PhDs Needed @ Lucent <NJ>
From: ejob <engineer@ejob.com>
Date: Wed, 09 Dec 1998 01:34:50 -0800
Links: << >>  << T >>  << A >>

>>>>>>>>>  Lucent SPAM deleted by Archive Owner

Article: 13552
Subject: Re: ALTERA isp cable
From: Andrew Crosland <andrewcr@uk.sun.com>
Date: Wed, 09 Dec 1998 09:35:40 +0000
Links: << >>  << T >>  << A >>
Byte Blaster schematics are freely available from Altera on their web
site and on page 704 of the 1988 data book. This clearly shows which
parallel port pins correspond to which TAP pins. They use a 74LS244 and
a few series resistors. I didn't have access to such old technology <bg>
so used a faster buffer and had to include decoupling and slew rate
limiting capacitors. It worked with 2m of shielded ribbon cable between
the PC and the pod and a further 10cm unshielded from the pod to the
board.

Regards

Andrew Crosland
Hardware Design Engineer

Network Systems
Sun Microsystems Ltd
UK

Tim Forcer wrote:
> 
> 
> But Altera don't say what the relationship is between parallel port pins
> and the TAP, nor what circuitry is required to provide that
> relationship.  Anyone reverse-engineered an Altera unit to find out?
> 
> Why is it that some companies (eg Lattice) are so open about how to use
> their isp, providing lots of documentation including schematics of the
> "proper" units, while others keep the whole thing shrouded in secrecy?
> Particularly now that the majority have opted for JTAG TAP as the basis
> of isp, it seems really perverse to keep users in the dark.
> 
--

Article: 13553
Subject: Re: ALTERA isp cable
From: Andrew Crosland <andrewcr@uk.sun.com>
Date: Wed, 09 Dec 1998 09:40:56 +0000
Links: << >>  << T >>  << A >>
OOPS! obviously I meant 1998!

Andrew Crosland wrote:
> 
> Byte Blaster schematics are freely available from Altera on their web
> site and on page 704 of the 1988 data book. This clearly shows which

Article: 13554
Subject: Re: Verilog/FPGA Express Synth Problem
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Wed, 09 Dec 1998 10:43:08 +0000
Links: << >>  << T >>  << A >>
Mark Lancaster wrote:
> I would try removing the space between 6'b and 000001 in the reset
> portion of your code.

So would I, but I think it is a red herring.  Synplify gets it
right with or without the space.  And if the space _is_ a syntax
error, then it is inexcusable for FPGA Express to silently give
the wrong answer.  It's a nice small example: beat 'em up about it.
(But first, check that this code really is what you submitted to 
the synthesis tool!!!)

BTW: When using LFSRs I like to add some logic to catch the all-zero
state and automatically jam one of the flipflops to 1.  This is
usually very cheap, and protects against the LFSR locking-up
if it happens to get pushed into the all-zero state by a supply
transient or other act of Beelzebub. And it would obviate your
need for reset to a non-zero value....

> Brian Boorman wrote:
> > Code fragment [slightly edited in the interests of conciseness]
> > [problem: lfsr_reg is reset to 000000 by FPGA Express's logic]
> >   always @ ( posedge(reset) or posedge(mclk) )
> >     begin
> >      if (reset == 1)        // guarantee not all 0's on reset
> >       lfsr_reg <= 6'b 000001; 
> >      else if (load == 1)    // loading wins over shift enable
> >       lfsr_reg <= load_data;
> >      else if (enable == 1)  // shift right
> >       lfsr_reg <= { (lfsr_reg[5]^lfsr_reg[0]), lfsr_reg[5:1] };
> >     end

Jonathan Bromley

Article: 13555
Subject: Re: A short digression...
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 09 Dec 1998 09:16:24 -0500
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> You're welcome.  I think that is a funny name for the tools.  It just
> doesn't fit ;-)
> 
> Seriously, what do you think of the 'Foundation' tool set?  Have you used
> Viewlogic before?
> 
> Austin

I have been an occasional user of Xilinx. In the past I have done a
design once every two years or so. By the time I needed to do a new
design, the tools had changed a lot. As a result, I never became more
than just "familiar" with the tools. 

The first set of tools I used was Viewlogic under DOS. This was not a
bad tool (although the support at that time really sucked!) Since then I
have used Orcad (prior to the Alliance name) and again Orcad with
Alliance only to switch to Foundation because the Orcad tools were
unusable with VHDL. 

My opinion of Viewlogic is based on the state of the tools at that time
(and the support). So I am not especially impressed with it. 

But at least part of my opinion is based on having learned VHDL. I am
impressed with being able to write software to design hardware and being
able to write programs to test my design (although I can't do that with
Foundation alone.) So I am not so concerned with the schematic capture
portion of a system. 

Foundation as a schematic editor does s**k pretty badly. But it doesn't
get in the way of my work. Right now it is the best choice for me,
because of the integrated development and across the tools support
provided. Once I become more familiar with the methods to instantiate
designs I may branch out to use other tools. 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13556
Subject: Re: Verilog/FPGA Express Synth Problem
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 09 Dec 1998 09:47:18 -0500
Links: << >>  << T >>  << A >>
I am not a Verilog programmer, but looking at your code, I would guess
that the way it is written your reset is not an async reset, but rather
a sync reset. Perhaps the reset condition should be brought outside of
the clock domain? That is how it is done in VHDL. 

It is clear that the reset state that is shown below is an async one. Do
you have any other example circuits where this works correctly? 



Brian Boorman wrote:
> 
> I am having a problem with FPGA Express (bundled with Xilinx Student
> Edition) detecting my resets in my final project. Basically it doesn't.
> Even though I specify 0x01 as the reset value, it makes them all reset.
> Could someone please help me out? Thanks!
> 
> Code fragment....
> 
>     always @ ( posedge(reset) or posedge(mclk) )
>         begin
>             if (reset == 1)
>                 lfsr_reg <= 6'b 000001; // guarantee register doesn't
> load all 0's on reset
>             else
>                 if (load == 1) // loading takes precedence over shift
> enable
>                     lfsr_reg <= load_data;
>                 else if (enable == 1)
>                     lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
> lfsr_reg[5:1] }; // shift right
>         end
> 
> FPGA Express synthesis results....
> 
> ===============================================================================
> 
> |      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS
> | ST |
> ===============================================================================
> 
> |       lfsr_reg_reg       | Flip-flop |   6   |  N  | ?  | ?  | ?  | ?
> | ?  |
> ===============================================================================
> 
> lfsr_reg_reg<3>
> ---------------
>     Async-reset: reset
> 
> lfsr_reg_reg<1>
> ---------------
>     Async-reset: reset
> 
> lfsr_reg_reg<5>
> ---------------
>     Async-reset: reset
> 
> lfsr_reg_reg<0>
> ---------------
>     Async-reset: reset
> 
> lfsr_reg_reg<4>
> ---------------
>     Async-reset: reset
> 
> lfsr_reg_reg<2>
> ---------------
>     Async-reset: reset
> 
> --
> Brian C. Boorman
> Harris RF Communications
> Rochester, NY 14610
> XYZ.bboorman@harris.com
> <Remove the XYZ. for valid address>

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13557
Subject: Re: What are the 'rules' for assigning large buses to fpga's
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 09 Dec 1998 09:58:16 -0500
Links: << >>  << T >>  << A >>
I would second that vote. I am testing a design now that drives a two 32
bit data buses, a 12 bit address bus, and at least a dozen control
lines, all clocked off of a common edge. Also about half of these
devices are clocked in the IOB so there is no variation in timing due to
routing. I am not seeing any problems with ground bounce. 

This is likely due to the fact that each of the data buses are very
short and only have one or two devices on them. We also paid close
attention to the layout and decoupling of the power to the chip. Of
course, I don't use the FAST attribute for any of these signals. I find
that clocking in the IOB gets me where I need to be with plenty of
margin. 

It would appear that this is not such a major concern as long as you
don't ask the chip to drive heavy loads or a lot of capacitance. 


Ray Andraka wrote:
> 
> Depends on how good your PWB is and what kind of loads you are driving.
> The board should have at least four layers with dedicated ground and vcc
> planes.  Good decoupling is also a must.  The most important factor,
> however, is the loads on the pins you wish to switch.  If the load
> capacitance is small (one or two devices), the switching current will
> also be small.  If that is the case, you can drive all your data out the
> same edge.  I've done that in many designs where the pins connected only
> to another FPGA or to a small number of memories or to a bus via fet
> switches without problems (with the fast slew rate).  On the other hand,
> if you are driving a heavily loaded bus, you may want to stick with the
> slow slew rate.
> 
> Steve wrote:
> 
> > I have an XCS30XL-PQ240 driving a 32 bit data bus
> > and a 16 bit address bus.  Can I do this without going
> > to slow slew rate?  How should I distribute the pins?
> >
> > I am mainly concerned about ground bounce, but I
> > guess minimal internal routing could be a conflicting
> > requirement.
> >
> > Comments?
> >
> > Steve
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13558
Subject: Re: What are the 'rules' for assigning large buses to fpga's
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Wed, 09 Dec 1998 15:46:23 GMT
Links: << >>  << T >>  << A >>
Thanks for the feedback!

Ray Andraka wrote in message <366DC811.9422DEEC@ids.net>...
>Depends on how good your PWB is and what kind of loads you are driving.
>The board should have at least four layers with dedicated ground and vcc
>planes.  Good decoupling is also a must.  The most important factor,
>however, is the loads on the pins you wish to switch.  If the load
>capacitance is small (one or two devices), the switching current will
>also be small.

Fortunately my design falls into this category.


>If that is the case, you can drive all your data out the same edge.

I wasn't sure I could do this after reading the recommendations in Ap note
45.
They say to group 4 outputs per GND pin which means a max of 16 outputs
per side on a PQ240.

I also noticed in "PCI Master & Slave Interfaces Version 1.2.0" they seemed
to stretch that to a max of 6 I/O's between ground pins which would allow me
up to 24 outputs per side.

I guess I'll follow the Ap note only allow the 4 per GND pin to increase as
I
reduce loading up to a max of 8 per GND.


Also I've noticed that Xilinx seems to be a little sparser with their power
pins than
Altera.  I assume this would make Xilinx a little more prone to ground
bounce
problems.


Steve


Article: 13559
Subject: Lattice Pin Drive Capability
From: John Chambers <johnc@ihr.mrc.ac.uk>
Date: Wed, 09 Dec 1998 17:16:08 +0000
Links: << >>  << T >>  << A >>
I'm using a Lattice ispLSI2096-80 (PQFP package) to implement an EPP
Printer Port peripheral.  I connected the pins of the CPLD straight to
the printer cable through 30R resistors.  Does anyone have any
experience of the current drive capacity of these parts as I seem to be
getting unreliable data transfer and need to know whether to revise my
state machine or prototype a new board with bus drivers.  The manual
seems to indicate that there is plenty of current drive availavle.  Any
help appriciated

	John

johnc@ihr.mrc.ac.uk

Article: 13560
Subject: Abel 5 and Windows NT
From: "Austin Franklin" <darkroom@ix.net8com.com>
Date: 9 Dec 1998 17:52:15 GMT
Links: << >>  << T >>  << A >>
Hi,

Has anyone been able to run Abel 5 under Windows NT?

Thanks,

Austin

Article: 13561
Subject: Re: Verilog/FPGA Express Synth Problem
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Wed, 09 Dec 1998 18:16:11 +0000
Links: << >>  << T >>  << A >>
Rickman wrote:
> I am not a Verilog programmer, but looking at your code, I would guess
> that the way it is written your reset is not an async reset, but rather
> a sync reset. Perhaps the reset condition should be brought outside of
> the clock domain? That is how it is done in VHDL.

Rick, the example is classic textbook Verilog for synthesis of an
async resettable register.  Synthesis tools recognise it and
infer the appropriate flipflop(s).  The always block (=process)
executes every time one of the "or"-ed signals in its sensitivity
list changes.  The qualifier "posedge" restricts the sensitivity
to only rising transitions of the qualified signal. "or" is a magic
operator for sensitivity lists and is not the same as logical OR.

These RTL constructs are effectively identical:

// _________________________________________Verilog

always @(posedge clk or posedge rst)
  if (rst) begin
    // asynch reset actions like q <= 0;
  end else begin  // or, perhaps, "end else if (enable) begin"
    // actions on rising clock edge like q <= d;
  end

--_____________________________________________VHDL

process (clk, rst) 
begin
  if rst='1' then
    --asynch reset actions like q <= 0;
  elsif rising_edge(clk) then
    --actions on rising clock edge like q <= d;
  end if;
end process;

Aw, they even *look* about the same!  Putting both clk and rst
in the process sensitivity list is a clue to the synth tools
that they can use to infer a resettable FF, no?  And yes, I do know
that many VHDL programmers code their registers in a somewhat
different style, but most VHDL tools I've met will happily swallow
the process given above.

Jonathan Bromley

PS:  Am I right in thinking that the pattern hyphen/hyphen/space that
opens most VHDL comments is seen by newsreaders as the start of the .sig?
Or do the leading (indentation) spaces in the VHDL stop that being a
problem?

Article: 13562
Subject: Re: The best PLD?
From: Jeff Vallier <jeffrey.vallier@smi.siemens.com>
Date: Wed, 09 Dec 1998 10:47:47 -0800
Links: << >>  << T >>  << A >>
I am partial to the Vantis parts for PLDs, because they are relatively
simple to understand, have ISP, the PALASM/MACHXL and ISP software is
free, and the timing is predictable.

Once you have mastered that, you can move to FPGAs and cram tons of
stuff in a Xilinx or Altera part but then the timing issues become
really fun (NOT) and the software a bit more complex. I have always
regarded simplicity as a virtue....

Hope this helps.

Peff

Luis de Funes wrote:

> Hi!
> Wath's the best way to begin to work with PLD?
> I think to a 32 or 64 macrocells, ISP naturally.
> Some producers give free software, but I'm confused.
> Altera? Vantis? Lattice? Others?
> Please, advice me! Thanks...
>
> Luigi



Article: 13563
Subject: xilink Parallel cable III
From: "saffary" <saffary@club-internet.fr>
Date: Wed, 9 Dec 1998 20:48:22 +0100
Links: << >>  << T >>  << A >>
Somone know where i can find this cable.

Thanks.




Article: 13564
Subject: Re: Verilog/FPGA Express Synth Problem
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 09 Dec 1998 14:58:03 -0500
Links: << >>  << T >>  << A >>
I see now Jonathan. I missed the reset showing in the sensitivity list. 

Thanks for the help!

I know less about newsreaders and signatures than I do Verilog, so I
can't help you with that one.  ;^)


Jonathan Bromley wrote:
> 
> Rickman wrote:
> > I am not a Verilog programmer, but looking at your code, I would guess
> > that the way it is written your reset is not an async reset, but rather
> > a sync reset. Perhaps the reset condition should be brought outside of
> > the clock domain? That is how it is done in VHDL.
> 
> Rick, the example is classic textbook Verilog for synthesis of an
> async resettable register.  Synthesis tools recognise it and
> infer the appropriate flipflop(s).  The always block (=process)
> executes every time one of the "or"-ed signals in its sensitivity
> list changes.  The qualifier "posedge" restricts the sensitivity
> to only rising transitions of the qualified signal. "or" is a magic
> operator for sensitivity lists and is not the same as logical OR.
> 
> These RTL constructs are effectively identical:
> 
> // _________________________________________Verilog
> 
> always @(posedge clk or posedge rst)
>   if (rst) begin
>     // asynch reset actions like q <= 0;
>   end else begin  // or, perhaps, "end else if (enable) begin"
>     // actions on rising clock edge like q <= d;
>   end
> 
> --_____________________________________________VHDL
> 
> process (clk, rst)
> begin
>   if rst='1' then
>     --asynch reset actions like q <= 0;
>   elsif rising_edge(clk) then
>     --actions on rising clock edge like q <= d;
>   end if;
> end process;
> 
> Aw, they even *look* about the same!  Putting both clk and rst
> in the process sensitivity list is a clue to the synth tools
> that they can use to infer a resettable FF, no?  And yes, I do know
> that many VHDL programmers code their registers in a somewhat
> different style, but most VHDL tools I've met will happily swallow
> the process given above.
> 
> Jonathan Bromley
> 
> PS:  Am I right in thinking that the pattern hyphen/hyphen/space that
> opens most VHDL comments is seen by newsreaders as the start of the .sig?
> Or do the leading (indentation) spaces in the VHDL stop that being a
> problem?

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13565
Subject: Re: computer requirements for CAE systems
From: Greg Peek <sorry@no.spam>
Date: Wed, 09 Dec 1998 13:15:17 -0800
Links: << >>  << T >>  << A >>
ISD magazine recently ran a series of articles which compared Sun vs NT
running Synopsys synthesis and Verilog-XL simulation.  I suggest you
obtain copies of those articles, the most recent is "EDA Platform
Benchmark: Simulation and Synthesis at the Same Time" in the November
1998 issue.

Here are my 2-cents (not speaking for my employer, but as an engineer
that designs using FPGAs):
1. and  2.  Get a system with the 100MHz SDRAM memory bus (for example
the BX or GX chip sets).  Choose a system with a very high limit for
memory, 1G or more.  The amount of memory to actually get depends on how
big your designs are.  Start with 256MB of SDRAM.  My Model Tech
simulations run just fine in 256MB, but if I were running synthesis on
NT, I'd want to be able to add enough memory to avoid going to the hard
disk.  Dell, Compaq, HP, IBM all sell "PC Workstations" that can handle
this kind of memory.  Note that going from 128K SDRAM to 256K SDRAM
modules adds one wait state to RAM access.  So don't go above 512MB if
you don't need to.

3.  NT will make use of the second processor if you are running two jobs
at the same time, but it does not speed up a single simulation or
synthesis job.  The ISD article says that having a second processor can
actually slow down a single job. I would only run one job at a time at
any rate, to avoid running out of RAM and the huge performance penalty
that would create.  Spend the second processor money on a faster
processor and/or RAM.  Get a Pentium II Xeon(tm) with 1MB of L2 cache if
you can afford it - for that much RAM, I'd like a lot of cache.
Otherwise get the fastest Pentium II you can afford with 512MB of L2.
The ISD article seems to show about a 25% speed improvement by doubling
the cache size.  Going from a 300MHz Pentium II to a 450MHz Xeon
improved simulation speed 154% on their benchmark (8100 seconds reduced
to 3200 seconds).  That is a combination of processor MHz, cache, and
architecture, plus 66MHz EDO vs 100MHz SDRAM speeds.

4.  If you are only looking at a two-year timeframe, I wouldn't count on
EDA apps using two processors.

Greg Peek
Intel corp


rich katz wrote:

>  cae s/w we can expect to run is:
>
>     viewlogic
>     actel tools
>     atmel tools
>     xilinx tools
>     synopsys w/ libraries for fpgas, asics
>     synplicity
>     possibly exemplar
>
> anyways,
>
> here's the topics for discussion:
>
>     1. how much dram should be on the machine?
>
>     2. how much dram should the machine be capable of? a lot of pc's
> are
>         limited to 384 megabytes.
>
>     3. does any of the s/w make use of a second processor?
>
>     4. will it be expected that in the next few years s/w
>         will make use of a second processor?
>
> thanks,
>
> rk



Article: 13566
Subject: FAE Field ApplicationS Engineers
From: devlinsearchgroup@usa.net
Date: Wed, 09 Dec 1998 22:06:28 GMT
Links: << >>  << T >>  << A >>
Field Applications Engineers  ASIC/Field Programable Gate Arrays experienced
people are needed in Ottawa and Toronto Canada.  My client is a world leader
in this fast past world. Excellent product, and futures plus Customer pull
has recently opened these opportunities. My client wants only the experienced
and proven with at least 3+ years . . .  and is willing to pay for that. If
you can provide comprehensive customer technical support throughout
pre-sales, post sales, device and tool selection through customer circuit
evaluation and systems design, coupled with the ability to do competitive
analysis you are on your way. If you can support both sales and customers in
technical presentations, design reviews, do demos on workstations and PC
platforms and train those damn distributors to be self sufficient you are
golden. But first, apart from just 3+ years experience you will need to have
BSEE or better. Love bleeding edge logic and systems design. Ooooze in
application experience and/or exposure to the leading competitors in this
field. Have a very strong background in CAE design tools, excellent
communications and customers interface skills could put you to work in two
weeks if you are looking for change.

Happy Holidays and remember, if you are the is all sing and dancing FAE you
could be putting those company stock options that come with this positions
under the tree or in the those stockings hung by the chimney with care.
Interviews and selection will continue through the holiday season. Four week
Training BOOT CAMP will start the 2ndweek of the new year for those selected.

Please email responses only. Cover letter and CV/Resumes should be sent to
DevlinSearchGroup@usa.net.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    

Article: 13567
Subject: Documention AHDL?
From: lars.freund@leei.enseeiht.fr (Lars Freund)
Date: Thu, 10 Dec 1998 00:09:57 +0100
Links: << >>  << T >>  << A >>
Hi,

is there a good documentation about AHDL available on the net? I need to
understand written AHDL code. I searched with Altavista but  had no
success (only for "AHDL - Animal Health Database Library" or so).

Thanks for any help,

Lars

Article: 13568
Subject: Re: Add-in board with FPGA Secondary Processor
From: Steve Casselman <sc@vcc.com>
Date: Wed, 09 Dec 1998 15:30:58 -0800
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

> try virtual computer www.vcc.com.  You'll want the hotworks II board which sells
> for 995.  You can also look at annapolis computer  and associated pro.  Go to
> www.optimagic.com and hit the boards link.  THere are many boards listed there.
>

He wants the HOT II pci development kit board. It sells for $695 to
use it you can use the student edition (spartan 40) software and you
must sign an agreement which entitles you use our version of Xilinxs
PCI core (Xilinx LOGIC Core PCI macro with our wapper in netlist format)
http://www.vcc.com/Hotii.html


> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka



--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 13569
Subject: Re: Verilog/FPGA Express Synth Problem
From: spp@bob.eecs.berkeley.edu
Date: 10 Dec 1998 00:10:55 GMT
Links: << >>  << T >>  << A >>
Brian,

>From what you've given us this isn't necessarily a bug, since it is
possible the synthesizer inverted the sense of one of your register 
bits.

Trace through the synthesized output, and/or perform
a structural simulation, to see if this is the case.
Maybe it clears the entire register, and then inverts the
bit you wants to set.

Steve

Article: 13570
Subject: Re: Abel 5 and Windows NT
From: "Austin Franklin" <darkroom@ix.net8com.com>
Date: 10 Dec 1998 00:25:19 GMT
Links: << >>  << T >>  << A >>
Well, I tried it, and it's a bit slow, as most DOS based apps are under
NT...but everything works!

Since I use Viewlogic, which uses a Rainbow key, as does ABEL, I already
had the Rainport driver installed....  The only things I had to make sure
were right were the environment variables and the that Abel was before
Viewlogic in the path statement...

A $3 PAL (22V10) is much cheaper than a Xilinx configuration PROM.....and
we can now reconfigure the device without burning another Xilinx PROM for
field upgrades!

Austin Franklin <darkroom@ix.net8com.com> wrote in article
<01be239c$8fc75bf0$67205dcf@drt1>...
> Hi,
> 
> Has anyone been able to run Abel 5 under Windows NT?
> 
> Thanks,
> 
> Austin
> 
> 

Article: 13571
Subject: Re: A short digression...
From: "Austin Franklin" <darkroom8@ix.netcom.com>
Date: 10 Dec 1998 05:28:02 GMT
Links: << >>  << T >>  << A >>
>... By the time I needed to do a new
> design, the tools had changed a lot. As a result, I never became more
> than just "familiar" with the tools. 

I understand ;-)

My choice of Viewlogic for schematics is based on my need to do board level
designs too, and Viewlogic is a good schematic tool for that, interfaces
with PADS very well...and I can do board level simulation very easily. 
Overall, it is a pretty complete and robust tool.  I did like the DOS
version though....I don't believe there was a better x86 based tool
available....and I don't know if there is today.  Yes, on Unix
workstations, there were other better/comparable tools available... 
Viewlogic has come a long way...

It's user interface could really be improved (like using the page-up/down
keys, instead of F8 and F7, etc)...but all in all, it work pretty well.

If you only do chips, and never do board level stuff, then, I am sure, your
options are different...

Austin

Article: 13572
Subject: Re: HELP, Tool selection
From: David Pashley <David@edasource.com>
Date: Thu, 10 Dec 1998 09:23:24 +0000
Links: << >>  << T >>  << A >>
In article <367494f8.86764450@news.netcomuk.co.uk>, Peter <z80@ds2.com>
writes
>Can't see why. Does it matter whether your name is John Fitzpatrick or
>Patrick Fitzjohn?
>
>If you post trash time and time again, after a while nobody will read
>it because you will get in their killfiles :)
>

When you criticise a company's products or services, many readers assume
you are unbiased, and your comments consequently damage that company's
reputation.

Yet *for all we know*, you may be a competitor engaged in a cynical
attempt to damage your target's image.

Also, I note that the most vehement and ill-informed complainers are the
anonymous ones such as yourself (and e.g. the initiator of the "Will
Xilinx survive" thread"), who are willing to put their Usenet
reputation, but *not* their personal or professional reputation on the
line.

My company has declined to respond to your own past untrue criticisms
for these reasons, and I know many other vendors and VARs take the same
view of Usenet. Which is a shame.
-- 
David Pashley                    <
 ---------------------------  <  <  <  --- mailto:david@edasource.com
| Direct Insight Ltd       <  <  <  <  >   Tel: +44 1280 700262      |
| http://www.edasource.com    <  <  <      Fax: +44 1280 700577      |
 ------------------------------  <  ---------------------------------

Article: 13573
Subject: Re: The best PLD?
From: Alasdair MacLean <nojunk@gecm.com>
Date: Thu, 10 Dec 1998 09:58:21 +0000
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> Have a look at the Philips Cool-PLD devices. They are among the very
> very few PLDs which are full-CMOS; most "CMOS" PLDs draw 50-200mA even
> at 0 MHz. I use the Philips P3Z22V10 but they do bigger stuff too, and
> a relatively cheap programmer. But not ISP.
> 

Not true. Philips produce CoolRunner CPLDs which include ISP
capabilities.

> --
> Peter.
> 
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but
> remove the X and the Y.

-- 
Alasdair Maclean, Senior Development Engineer,
Marconi Electronic Systems,
Electro Optics Systems Division,
Building 1A, Room 1-11,
4 Ferry Road, Silverknowes,
Edinburgh, Scotland EH4 4AD
Tel: +44 (0)131 343 5711, Fax: +44 (0)131 343 5050
Email: <mailto:alasdair.maclean@gecm.com>

Article: 13574
Subject: Re: Why doesn't Xilinx's simulator work?
From: "Grzegorz Apczynski" <grzegorza@aldec.com>
Date: Thu, 10 Dec 1998 10:16:53 GMT
Links: << >>  << T >>  << A >>

khartman@conwin.com wrote in message <74eov4$uis$1@nnrp1.dejanews.com>...
>In article <725rjk$5m$1@ffx2nh2.uu.net>,
>  "Joel Kolstad" <JKolstad@Electroglas.Com> wrote:
>> Well, it's probably me... but damn it... I'm running Foundation 1.5 here,
>> and getting the schematic capture portion of the package to talk to the
>> simulator is nearly impossible.  I'll tell it to simulate a macro, it'll
>> open up the simulator, and then I'll start adding probe points.  The
>> simulator COMPLETELY IGNORES the probe points I'm clicking on, when it
>> should be adding them to its own list.  I'll click over on the simulator
and
>> add some signals, and schematic captures completely ignores what's been
>> added!  Better still, sometimes schematic capture won't even let me add
any
>> probe points at all, just completely ignoring mouse clicks!
>>
>> You go ahead and step time in the simulator, and the signals listed do
>> reasonable things, but schematic just sits there with its probe points
>> displaying nothing at all.
>>
>> !@$!@#%^^#$
>>
>> OK, this doesn't happen 100% of the time.  On VERY RARE occasion it
actually
>> works the way it should.  I can't believe this happens to all you other
>> people on a daily basis, or there'd be an angry mob outside of Xilinx HQ
>> threatening to burn the place down.  So what am I doing wrong?  The
concept
>> seems really simple -- add a probe in schematic, and the simulator picks
it
>> up, add a signal in simulator, and schematic should pick it up... right?
>>
>> ---Joel Kolstad


Do not use the Simulate Currrent Macro option from the schematic if
you want to use probes. You should load the project netlist - click the
SIM button in the schematic or Functional Simulation in the project manager.
Go down to your macro and add probes. Use overwrite (OV, red) stimulators
for
the input ports - you achieve the same result (as Simulate Currrent Macro )
and probes will work.


>>
>>
>
>Oh God! I am sitting here on a dreary Sunday afternoon, desparately looking
>for information describing a fix for EXACTLY THIS PROBLEM! However, I
believe
>that I can add a little twist to the puzzle.  In my case, however, the
>simulator works in the functional mode and does NOT WORK in the timing
mode.
>What is more remarkable is the fact that the simulator does not even see
the
>instance(s) that I am trying to probe in the timing mode.  What is MOST
>remarkable is the fact that no schematic implementation, no vhdl macro
>implementation, no nothing is either visible or simulatable (in the timing
>mode) for this section of the design! Joel? did you ever get an answer?


Notice that in the timing mode you are simulating a completely different
netlist.
It no longer uses the models you placed on the schematic - it is decomposed
and uses basic models from SIMPRIMS library.
The other thing is Xilinx backannotation tool changes signal names
e.g. your ADDER1 signal may become U1_H1_ADDER1 or something like that.
Only the interface signals (which goes in and out of your chip) are not
distorted and adding probes to them will work.
Other signals may be renamed or even trimmed from your design so
adding probes to them is useless - they no longer exist in the
backannoted netlist.


>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own




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