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Messages from 20150

Article: 20150
Subject: GLSVLSI-2000 Advance Registeration
From: afarrahi@my-deja.com
Date: Fri, 28 Jan 2000 18:23:17 GMT
Links: << >>  << T >>  << A >>
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
10-th Great Lakes symposium on VLSI Design
March 2-4, 2000,  Chicago, Illinois, U.S.A.
http://www.glsvlsi.com
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Dear Colleagues,

Please note that the advance registeration
deadline for
GLSVLSI-2000 is approaching (February 1, 2000).
Please refer to the *new* conference web-site at
URL:

    http://www.glsvlsi.com

for registeration procedure and latest updates.

Regards
Amir Farrahi
Publicity Chair

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
10-th Great Lakes symposium on VLSI Design
March 2-4, 2000,  Chicago, Illinois, U.S.A.
http://www.glsvlsi.com
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20151
Subject: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Jan 2000 10:46:58 -0800
Links: << >>  << T >>  << A >>
Ben,
thinking about your design with a fresh mind, I would suggest to derive the 60
MHz output clock directly by dividing the 120 MHz in a CLB flip-flop,
bypassing all DLLs.
That way you have the smallest possible jitter, but of course a certain delay.

You use the DLLs to eliminate the on-chip clock distribution delay, and you
accept the ~50 ps max jitter, but you then resynchronize with a half-frequency
version of your very clean 120 MHz input clock. The DLL jitter is thus
absorbed inside the chip, and you must do a careful timing analysis so that
the 60 MHz output clock has a safe phase relationship with the DLL-derived
clock.  At a leisurely 60 MHz, this should be easy. Interesting application.

Peter Alfke, Xilinx Applications

Ben Sanchez wrote:

> Peter,
>
> I'm designing a circuit that receives a copy of a 120 MHz sample clock
> (used in radio astronomy, and locked to an atomic standard at the
> observatory, typically an H Maser) along with the sample data.  The
> input samples and clock are fed to an XCV050 and the clock is passed
> through one of the DLL's and into the chip for use in the input side of
> a FIFO/Packer setup, the CLKDV output of that CLKDLLHF is passed to the
> two CLKDLLs on the other side of the chip, on of which redrives the now
> 60 MHz clock for the rest of the board's data path and the other passing
> it into the Virtex for the output side of the FIFO/Packer and other
> logic.
>
> The question is, with the extremely low jitter at the input, how much
> will be added by the two levels of CLKDLLHF and CLKDLL that it goes
> through?  I'm curious because at the board's final output I'm using that
> 60 MHz clock to drive a serializer, which multiplies it up to 1440 MHz
> internally, and has pretty tight jitter specs in order to maintain
> reliable lock at the Rx end and a low BER.  (It's an HP G-Link in case
> you're familiar with it)
>
> Is there a potential problem?  Until now I had been convinced that there
> was not going to be, which may even have been an idea I got from you
> when we discussed the subject during the break in one of the classes you
> guys hold there at Xilinx. (Can't remember why I thought that now,
> hoping I had a good reason)
>
> Thanks,
> Ben Sanchez
>
> Peter Alfke wrote:
> >
> > Magnus Homann wrote:
> >
> > >
> > >
> > > Yup, that's what Xilinx told me too. Altera has a different view on
> > > the subject, though...  :-)
> > >
> > > Who is right?
> >
> > It's an interesting battle. Here are my views:
> >
> > In an ideal world without any noise, ground bounce, and processing
> > problems, the PLL would have some advantages, since it can multiply the
> > incoming frequency by any factor, and it can suppress incoming jitter (
> > if that is desirable).
> >
> > Now let's leave the idealized world and enter the real world:
> >
> > Keeping the spontaneous jitter of an RC-based on-chip VCO under control
> > is a very difficult task. I know; I cut my teeth on TV-tuner and citizen
> > band analog PLLs many years ago, and there we had the luxury of using LC
> > oscillators, which I find easier to keep clean. Putting a sensitive and
> > delicate analog circuit onto any notoriously noisy digital chip is asking
> > for trouble. First, the analog parameters of the PLL transistors must be
> > controlled ( and what happens when the process migrates to smaller
> > geometries? ), and then you need separate ground/Vcc pins and decoupling,
> > and you still don't know how much spontaneous jitter is being generated.
> > Combining digital and analog is like moving a rock band into an old folks
> > home. They just don't like each other.
> >
> > The DLL is a 100% digital circuit; its output jitter has a well-defined
> > max value, and no extra supply connections are needed.
> >
> > I for one feel much more comfortable in the predictable digital world of
> > the DLL.
> >
> > Peter Alfke, Xilinx Applications

Article: 20152
Subject: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
From: Ben Sanchez <ben_sanchez@worldnet.att.net>
Date: Fri, 28 Jan 2000 13:50:18 -0800
Links: << >>  << T >>  << A >>
Peter,

That is a pretty good idea.  I like the simplicity.  The phase
relationship to the 120 MHz input is essentially unimportant, except
that it be exactly fixed.  The only reason for that is that with
hundreds, currently even thousands of feet of antenna diameter, we can
see even the weakest of our own emissions (data are FFT'd to ~1Hz
resolution @ 50% overlap and signal detection algorithms are then
employed on the freq. domain data that are sensitive to signals as weak
as 3 db below the noise floor), so in the even our shielding is not
perfect, any emissions we produce need to be exactly locked to the
observatory frequency standard.  That keeps then at a 0 Hz drift rate in
the data, making them easy to identify and remove, without having to
take out several consecutive channels.

So, with that said, it is my assumption, and perhaps you have insight,
that the delay produced by such a CLB divider would be fixed to within
say +/- a few percent of the path delay for that signal, say of order
1-2ns.  does that sound right?  If it is this is a wonderful idea!

Thanks for the help,
Ben Sanchez


Peter Alfke wrote:
> 
> Ben,
> thinking about your design with a fresh mind, I would suggest to derive the 60
> MHz output clock directly by dividing the 120 MHz in a CLB flip-flop,
> bypassing all DLLs.
> That way you have the smallest possible jitter, but of course a certain delay.
> 
> You use the DLLs to eliminate the on-chip clock distribution delay, and you
> accept the ~50 ps max jitter, but you then resynchronize with a half-frequency
> version of your very clean 120 MHz input clock. The DLL jitter is thus
> absorbed inside the chip, and you must do a careful timing analysis so that
> the 60 MHz output clock has a safe phase relationship with the DLL-derived
> clock.  At a leisurely 60 MHz, this should be easy. Interesting application.
> 
> Peter Alfke, Xilinx Applications
> 
> Ben Sanchez wrote:
> 
> > Peter,
> >
> > I'm designing a circuit that receives a copy of a 120 MHz sample clock
> > (used in radio astronomy, and locked to an atomic standard at the
> > observatory, typically an H Maser) along with the sample data.  The
> > input samples and clock are fed to an XCV050 and the clock is passed
> > through one of the DLL's and into the chip for use in the input side of
> > a FIFO/Packer setup, the CLKDV output of that CLKDLLHF is passed to the
> > two CLKDLLs on the other side of the chip, on of which redrives the now
> > 60 MHz clock for the rest of the board's data path and the other passing
> > it into the Virtex for the output side of the FIFO/Packer and other
> > logic.
> >
> > The question is, with the extremely low jitter at the input, how much
> > will be added by the two levels of CLKDLLHF and CLKDLL that it goes
> > through?  I'm curious because at the board's final output I'm using that
> > 60 MHz clock to drive a serializer, which multiplies it up to 1440 MHz
> > internally, and has pretty tight jitter specs in order to maintain
> > reliable lock at the Rx end and a low BER.  (It's an HP G-Link in case
> > you're familiar with it)
> >
> > Is there a potential problem?  Until now I had been convinced that there
> > was not going to be, which may even have been an idea I got from you
> > when we discussed the subject during the break in one of the classes you
> > guys hold there at Xilinx. (Can't remember why I thought that now,
> > hoping I had a good reason)
> >
> > Thanks,
> > Ben Sanchez
> >
> > Peter Alfke wrote:
> > >
> > > Magnus Homann wrote:
> > >
> > > >
> > > >
> > > > Yup, that's what Xilinx told me too. Altera has a different view on
> > > > the subject, though...  :-)
> > > >
> > > > Who is right?
> > >
> > > It's an interesting battle. Here are my views:
> > >
> > > In an ideal world without any noise, ground bounce, and processing
> > > problems, the PLL would have some advantages, since it can multiply the
> > > incoming frequency by any factor, and it can suppress incoming jitter (
> > > if that is desirable).
> > >
> > > Now let's leave the idealized world and enter the real world:
> > >
> > > Keeping the spontaneous jitter of an RC-based on-chip VCO under control
> > > is a very difficult task. I know; I cut my teeth on TV-tuner and citizen
> > > band analog PLLs many years ago, and there we had the luxury of using LC
> > > oscillators, which I find easier to keep clean. Putting a sensitive and
> > > delicate analog circuit onto any notoriously noisy digital chip is asking
> > > for trouble. First, the analog parameters of the PLL transistors must be
> > > controlled ( and what happens when the process migrates to smaller
> > > geometries? ), and then you need separate ground/Vcc pins and decoupling,
> > > and you still don't know how much spontaneous jitter is being generated.
> > > Combining digital and analog is like moving a rock band into an old folks
> > > home. They just don't like each other.
> > >
> > > The DLL is a 100% digital circuit; its output jitter has a well-defined
> > > max value, and no extra supply connections are needed.
> > >
> > > I for one feel much more comfortable in the predictable digital world of
> > > the DLL.
> > >
> > > Peter Alfke, Xilinx Applications
Article: 20153
Subject: Re: ADC to DSP... FIFO?
From: russell shaw <russell@webaxs.net>
Date: Sat, 29 Jan 2000 10:03:41 +1100
Links: << >>  << T >>  << A >>
But i hate limited time licences. You just start getting into some interesting
stuff and you have to go cap in hand for more licence:(

Jerry Avins wrote:
> 
> russell shaw wrote:
> >
> > Ah, but the bit that should be free is most expensive (the software that
> > gives you the privelidge of using said cheep chips).
> >
> >
> > Peter Alfke wrote:
> > >
> > > FPGAs offer you all the flexibility you could possibly ask for, and they
> > > are not expensive any more.
> > >


> Doesn't Altera let you have a limited-time license free?
> 
> Jerry
> --
> Engineering is the art of making what you want from things you can get.
> -----------------------------------------------------------------------

-- 
*******************************************
*   Russell Shaw, B.Eng, M.Eng(Research)  *
*   Electronics Consultant                *
*      email: russell@webaxs.net          *
*      Australia                          *
*******************************************
Article: 20154
Subject: Spartan II availability and pricing
From: ldoolitt@recycle (Larry Doolittle)
Date: 28 Jan 2000 23:26:53 GMT
Links: << >>  << T >>  << A >>
I have been scanning nuhorizons web site a couple times a week,
looking for real availability and pricing and the recently
announced Spartan II family.  Nothing.  Zip.  Nada.

I understand that samples are available "now" (at least for the
XC2S100, and maybe also the XC2S150 and XC2S50), and production
starts 1Q00 (which is also about now, by my watch).  Xilinx also
throws out oblique hints about pricing (ten dollars, over and
over again), which we all know need substantial adjustment to
line up with reality.

Can anyone add to this information?

Given that the best way to get information on usenet is to post
_incorrect_ information, and wait for people to jump all over you.
In that spirit, I present a table of prices (US$) for small quantities
(less than 25) of Spartan and Virtex devices, which is on-line at
Nu Horizons and Insight.  Along with that, I give my _guesses_ as
to how the new Spartan II will fit into the product lineup.  The
last column is "price per slice"; a Spartan has one slice per CLB,
the Virtex and Spartan II have two slices per CLB.  One slice has
two 4-in LUT's, two flip flops, and a variety of other cruft :-).

                  price  slice  price/slice
Spartan
XCS05   3PC84C    10.00   100  .1000
XCS10   3PC84C    18.10   196  .0923
XCS20   3PQ208C   40.40   400  .1010
XCS30   3PQ208C   45.35   576  .0787
XCS40   3PQ208C   49.15   784  .0627

Spartan II     (remember, these prices are GUESSES!)
XC2S15  5TQ144C   13      192  .0677
XC2S30  5PQ208C   23      432  .0532
XC2S50  5PQ208C   33      768  .0430
XC2S100 5PQ208C   46     1200  .0383
XC2S150 5PQ208C   68     1728  .0394

Virtex
XCV50   4PQ240C   55.40   768  .0721
XCV100  4PQ240C  104.00  1200  .0867
XCV150  4PQ240C  128.00  1728  .0741
XCV200  4PQ240C  157.00  2352  .0668
XCV300  4PQ240C  244.00  3072  .0794
XCV400  4HQ240C  344.00  4800  .0717
XCV600  4HQ240C  581.00  6912  .0841
XCV800  4HQ240C  860.00  9744  .0883

   - Larry Doolittle   <LRDoolittle@lbl.gov>
     (looking forward to the OR1K release at http://www.opencores.org)
Article: 20155
Subject: Re: ADC to DSP... FIFO?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Jan 2000 15:56:20 -0800
Links: << >>  << T >>  << A >>
Don't ventilate year-old stories about high-priced software. If you like a
certain architecture, approach the salesforce and tell them what you want to do,
and what you expect.
They can be very smart and very helpful.

Software has gotten much better, and also much more affordable.

Peter Alfke, Xilinx Applications.
===============================================
russell shaw wrote:

> But i hate limited time licences. You just start getting into some interesting
> stuff and you have to go cap in hand for more licence:(
>
> Jerry Avins wrote:
> >
> > russell shaw wrote:
> > >
> > > Ah, but the bit that should be free is most expensive (the software that
> > > gives you the privelidge of using said cheep chips).
> > >
> > >
> > > Peter Alfke wrote:
> > > >
> > > > FPGAs offer you all the flexibility you could possibly ask for, and they
> > > > are not expensive any more.
> > > >
>
> > Doesn't Altera let you have a limited-time license free?
> >
> > Jerry
> > --
> > Engineering is the art of making what you want from things you can get.
> > -----------------------------------------------------------------------
>
> --
> *******************************************
> *   Russell Shaw, B.Eng, M.Eng(Research)  *
> *   Electronics Consultant                *
> *      email: russell@webaxs.net          *
> *      Australia                          *
> *******************************************

Article: 20156
Subject: Re: Spartan XL
From: "Holger Kleinert" <Holger@hollgi.de.nuspam>
Date: Sat, 29 Jan 2000 01:06:50 +0100
Links: << >>  << T >>  << A >>

Rastislav Struharik <rasti74@iname.com> schrieb in im Newsbeitrag:
6aqRODv2kS2as4GOdStE92Yiubf+@4ax.com...
> Hi everyone,
>
> For my next project I am planing to use Xilinx SpartanXL in 240-pin or
> 208-pin PQFP package. For the prototyping phase I would like to use
> some kind of an adapter or even better socket that converts PQFP into
> thruhole type device for easier handling.
> I have found a company named NPLAS that offers PQFP sockets. As an
> answer to my enquiry they gave me these two part numbers:
> PQFP 208pin socket:  OTQ-208-0.5-01
> PQFP 240pin socket:  OTQ-240-0.5-01
> but in the following text they stated that they are uncertain that the
> sockets would fit Xilinx PQFP's.

Hi !

Try :
http://www.advintcorp.com/products.html


Holger


Article: 20157
Subject: Re: ADC to DSP... FIFO?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Jan 2000 18:09:18 -0800
Links: << >>  << T >>  << A >>


Larry Doolittle wrote:

> : Does this mean you can provide me with a name/e-mail/phone
> for someone to ask about Alliance support for Linux?
> Someone who will say something more concrete than
> "we're looking into it?"
>

I was addressing the complaint of "high software cost".

Now you ask for Linux support, and yes " we are looking into it".
That is an honest answer. It means we are aware of this version of
Unix, but we are not ready to announce that our software is
guaranteed, and has been thoroughly tested, to run under Linux. No
further comment, at least not from me.
We are just being honest.  You don't have to like the answer, but I
hope you appreciate the honesty.

Now back to the issue of cost and price...

Peter Alfke

Article: 20158
Subject: Re: Spartan II availability and pricing
From: Ray Andraka <randraka@ids.net>
Date: Sat, 29 Jan 2000 02:12:52 GMT
Links: << >>  << T >>  << A >>
Those look like very small quantity (onesy-twosy) prices.  The prices drop
fairly sharply with quantity.  About 10% off for orders as small as 100
pieces.  I think the avnet parts and availability lists an XCS05 at about
$10 for up to 24, and about $8.50 for up to 99 parts.  Given your price
scale though, You're probably not that far off on the X2S parts for
similar quantities.



Larry Doolittle wrote:

> I have been scanning nuhorizons web site a couple times a week,
> looking for real availability and pricing and the recently
> announced Spartan II family.  Nothing.  Zip.  Nada.
>
> I understand that samples are available "now" (at least for the
> XC2S100, and maybe also the XC2S150 and XC2S50), and production
> starts 1Q00 (which is also about now, by my watch).  Xilinx also
> throws out oblique hints about pricing (ten dollars, over and
> over again), which we all know need substantial adjustment to
> line up with reality.
>
> Can anyone add to this information?
>
> Given that the best way to get information on usenet is to post
> _incorrect_ information, and wait for people to jump all over you.
> In that spirit, I present a table of prices (US$) for small quantities
> (less than 25) of Spartan and Virtex devices, which is on-line at
> Nu Horizons and Insight.  Along with that, I give my _guesses_ as
> to how the new Spartan II will fit into the product lineup.  The
> last column is "price per slice"; a Spartan has one slice per CLB,
> the Virtex and Spartan II have two slices per CLB.  One slice has
> two 4-in LUT's, two flip flops, and a variety of other cruft :-).
>
>                   price  slice  price/slice
> Spartan
> XCS05   3PC84C    10.00   100  .1000
> XCS10   3PC84C    18.10   196  .0923
> XCS20   3PQ208C   40.40   400  .1010
> XCS30   3PQ208C   45.35   576  .0787
> XCS40   3PQ208C   49.15   784  .0627
>
> Spartan II     (remember, these prices are GUESSES!)
> XC2S15  5TQ144C   13      192  .0677
> XC2S30  5PQ208C   23      432  .0532
> XC2S50  5PQ208C   33      768  .0430
> XC2S100 5PQ208C   46     1200  .0383
> XC2S150 5PQ208C   68     1728  .0394
>
> Virtex
> XCV50   4PQ240C   55.40   768  .0721
> XCV100  4PQ240C  104.00  1200  .0867
> XCV150  4PQ240C  128.00  1728  .0741
> XCV200  4PQ240C  157.00  2352  .0668
> XCV300  4PQ240C  244.00  3072  .0794
> XCV400  4HQ240C  344.00  4800  .0717
> XCV600  4HQ240C  581.00  6912  .0841
> XCV800  4HQ240C  860.00  9744  .0883
>
>    - Larry Doolittle   <LRDoolittle@lbl.gov>
>      (looking forward to the OR1K release at http://www.opencores.org)

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20159
Subject: Testbenches
From: Madison <madisonfj@uswest.net>
Date: Fri, 28 Jan 2000 22:35:32 -0700
Links: << >>  << T >>  << A >>
I am seeking a source of comprehensive information on building
testbenches for programmable logic simulations.  The reference material
I presently have (both instructional texts and software documentation)
give this matter very light treatment.  Are there books which cover
testbenches exclusively or at least have thorough coverage of the topic?

Thanks and Best Regards,

Frank Madison

Article: 20160
Subject: Re: Testbenches
From: bobperl@best_no_spam_thanks.com (Bob Perlman)
Date: Sat, 29 Jan 2000 07:49:41 GMT
Links: << >>  << T >>  << A >>
Hi - 

On Fri, 28 Jan 2000 22:35:32 -0700, Madison <madisonfj@uswest.net>
wrote:

>I am seeking a source of comprehensive information on building
>testbenches for programmable logic simulations.  The reference material
>I presently have (both instructional texts and software documentation)
>give this matter very light treatment.  Are there books which cover
>testbenches exclusively or at least have thorough coverage of the topic?
>
>Thanks and Best Regards,
>
>Frank Madison

I haven't seen it yet, but I've heard good things about a brand-new
book called, "Writing Testbenches: Functional Verification of HDL
Models" by Janick Bergeron of Qualis; the publisher is Kluwer.  The
book has just shown up on the Computer Literacy web site, and you can
also find more information at:

http://www.janick.bergeron.com/

Bergeron has started a moderated mailing list that he calls the
Verification Guild (I just got the first mailing today).  You can sign
up on the web site.

Take care,
Bob Perlman

-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 20161
Subject: Re: ADC to DSP... FIFO?
From: "Ken Krabacher" <ken.krabacher@betalasermike.com>
Date: Sat, 29 Jan 2000 07:30:37 -0500
Links: << >>  << T >>  << A >>
I'm doing something similar with a c32-- I've 8 channels running through an
analog mux, then into a 12-bit A/D, then through a PLD which handles the
timing, tickles the mux, and reads from the A/D.  (I switch the mux channel
just after sampling so there's plenty of time to settle.)  I'm driving the
PLD with the serial clock of the c32, which allows me to control the
sampling rate really easily.  The PLD continually writes 16-bit data
serially to the DSP's serial port, and I have a DMA set up from the serial
port to a buffer in memory.  The DMA controller is set up to always read
from the serial port, and increment the write address, so it winds up
filling a buffer in memory without running any code so it hardly takes any
cpu time at all.  The controller interrupts when the end address is reached,
at which point I switch to a different buffer and start gnawing on the data
just received.  At a clock rate of 12.5MHz, I'm getting about 750k (16-bit)
words/second.  I think you can run the serial clock 2x as fast if you use an
external source.

Hope this is useful,
Ken Krabacher

Lee Cao <ligeng@NOSPAMleecao.com> wrote in message
news:MPG.12fa7a0ba5f0a8d898970f@news.erols.com...
>
> Help!!!
>
> I am looking for a way to acquire 11 channels of 12-bit data at 11kHz.
> The DSP I am using is a Texas Instrument TMS320C32, the 60MHz one.
>
> The DSP needs to do quite a bit of number crunching so I was hoping
> that there could be some way of automating/buffering the incomining
> data from the ADC at the rate of approximately 200kBytes/s.  I don't
> think that having the DSP interrupted 11,000 times per second to
> service the ADC is going to work.
>
> In the name of saving space and cost, I was looking for ADCs with
> buffering FIFO built into it.  So far, I found a Texas Instrument
> THS1206, which is a 4 channel 1.5Msps/channel 12-bit ADC with a
> 16-word FIFO built in.  This means I can take up to four samples
> before the ADC have to be serviced by the DSP.  But this chip is
> around $15.00 a piece, which means I would be spending $40+ on
> three of them just to cover 11 channels.
>
> Do I have any other options?  I don't need the 1.5Msps/channel
> rate of the THS1206.  Is there a less expensive ADC out there with
> multichannel input, built-in MUX, S&H, 12-bit resolution, FIFO,
> and at least 11ksps/channel?
>
> If not, what are my other options at interfacing the ADC front
> end circuitry to the DSP?  Would I need a PLD logic of some sort
> with enough flip-flops to act as a data buffer?
>
> Thanx
>
> --
> Lee Cao


Article: 20162
Subject: Re: LVPECL I/O interface
From: krw@attglobal.net (Keith R. Williams)
Date: 29 Jan 2000 15:36:00 GMT
Links: << >>  << T >>  << A >>
On Fri, 28 Jan 2000 14:58:16, Theron Hicks <hicksthe@egr.msu.edu>
wrote:

> 
> Having just completed a design with similar constraints (PECL signals into a 3.3
> volt FPGA) I can agree with this statement.  Actually there is a whole family of
> parts available depending on required speed, direction of signal flow, and number
> of channels.  

I'm using PECL clock generators into PECL programmable delay 
lines then translating to LVPECL to the FPGA. The FPGA in 
question is a Virtex/VirtexE.  I have the pinout set up for the 
VirtexE (when I can get them) differential pairs.  On the Virtex 
parts I'll have to make do with a single-ended clock and a 
reference voltage. This is just a temperary solution though. I 
know this doesn't answer the original question. 

A second vendor to consider is Micrel.  The positives are a 
slightly
> different product spectrum and lower cost (at least at the small purchase quantity
> level.)

I found Micrel parts to be much easier to find in small 
quantities. I found them in stock at Nu Horizons and ordered them
right along with the FPGAs.

> Motorola (now OnSemi) has the advantage of having a faster line of new
> products and generally better availability.  In general the two basic part
> numbering schemes are very similar and the pin-outs are identical.  Lately the
> OnSemi web site has been highly uncooperative as far as downloading data sheets.
> A possible alternative source might be Fairchild.  I don't know if they have any
> low voltage PECL translators.  (By the way, that is what these parts are listed
> as, LVPECL to LVTTL translators or vice versa).  The Fairchild parts are also
> second sourced by Micrel.  The best stocking distributor for Micrel ECL family
> parts that I have found is Future.  I don't work for them but I have been quite
> impressed with the assistance they are willing to give the little guy.

I've also found Nu Horizons to be very good.  They're on top of 
my order and have visited me a few times, though I don't exactly 
work for "a little guy". However, it is a small project with 
small quantities (of expen$ive FPGAs).

----
  
  Keith


Article: 20163
Subject: Re: ADC to DSP... FIFO?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 29 Jan 2000 10:57:13 -0500
Links: << >>  << T >>  << A >>
Russell,

I am not trying to push the Lucent stuff, but they do give away their
toolset which includes the front end (Viewlogic) and the back end tools
as well as VHDL support (or so I hear, I have not tried to use it). You
just have to ask your FAE to provide you with a copy. My FAE (Rick
Golabowski of Impact) has been very supportive (especially on snow days
;). Try your distributor based FAEs. 

I like the Xilinx tools which work well if they are a bit hard to learn.
But I have found the Lucent tools to be very useful as well and I am
getting decent support from my local FAE as well as some advice from Bob
Wagner via postings here. 

One common point to all of the FPGA tools I have looked at; they all
seem to be going in the direction of HDL support. Every time I ask
questions the responder seems to assume that I am using an HDL ignoring
the possibility of my entry method being schematic. I am using schematic
entry because I often have pieces of my design that need to be very
highly optimized which I just don't have enough control via VHDL to make
work. So rather than do a mixed design, I just use schematic capture. I
also have tight schedules which I have found fit better with predictable
schematic capture. 

My concern is that I may end up like the dodo bird when it comes to
support. A lot of the support engineers already don't use schematic
tools and so can't answer questions about them. So if you do any serious
design in FPGAs, you may want to go for the HDL tools and keep schematic
as an adjunct for the tough pieces. 



russell shaw wrote:
> 
> Been there, done that, they're neither smart or helpful. If you're trying to get
> fully familiar with using said devices and cad and tell them you wan't the
> software for free so you can get proficient with their system and parts,
> they'll say something like "we'll get back to you" etc (which they never do).
> 
> Xilinx is the first outfit i approached, and they did this. I no longer talk
> about xilinx unless asked.
> 
> Peter Alfke wrote:
> >
> > Don't ventilate year-old stories about high-priced software. If you like a
> > certain architecture, approach the salesforce and tell them what you want to do,
> > and what you expect.
> > They can be very smart and very helpful.
> >
> > Software has gotten much better, and also much more affordable.
> >
> > Peter Alfke, Xilinx Applications.
> > ===============================================
> > russell shaw wrote:
> >
> > > But i hate limited time licences. You just start getting into some interesting
> > > stuff and you have to go cap in hand for more licence:(
> > >
> > > Jerry Avins wrote:
> > > >
> > > > russell shaw wrote:
> > > > >
> > > > > Ah, but the bit that should be free is most expensive (the software that
> > > > > gives you the privelidge of using said cheep chips).
> > > > >
> > > > >
> > > > > Peter Alfke wrote:
> > > > > >
> > > > > > FPGAs offer you all the flexibility you could possibly ask for, and they
> > > > > > are not expensive any more.
> > > > > >
> > >
> > > > Doesn't Altera let you have a limited-time license free?
> > > >
> > > > Jerry
> > > > --
> > > > Engineering is the art of making what you want from things you can get.
> > > > -----------------------------------------------------------------------
> > >
> --
> *******************************************
> *   Russell Shaw, B.Eng, M.Eng(Research)  *
> *   Electronics Consultant                *
> *      email: russell@webaxs.net          *
> *      Australia                          *
> *******************************************


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20164
Subject: Re: ADC to DSP... FIFO?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 29 Jan 2000 11:42:17 -0500
Links: << >>  << T >>  << A >>
Opps, I somehow posted this to the wrong thread... sorry!


Rickman wrote:
> 
> Russell,
> 
> I am not trying to push the Lucent stuff, but they do give away their
> toolset which includes the front end (Viewlogic) and the back end tools
> as well as VHDL support (or so I hear, I have not tried to use it). You
> just have to ask your FAE to provide you with a copy. My FAE (Rick
> Golabowski of Impact) has been very supportive (especially on snow days
> ;). Try your distributor based FAEs.
> 
> I like the Xilinx tools which work well if they are a bit hard to learn.
> But I have found the Lucent tools to be very useful as well and I am
> getting decent support from my local FAE as well as some advice from Bob
> Wagner via postings here.
> 
> One common point to all of the FPGA tools I have looked at; they all
> seem to be going in the direction of HDL support. Every time I ask
> questions the responder seems to assume that I am using an HDL ignoring
> the possibility of my entry method being schematic. I am using schematic
> entry because I often have pieces of my design that need to be very
> highly optimized which I just don't have enough control via VHDL to make
> work. So rather than do a mixed design, I just use schematic capture. I
> also have tight schedules which I have found fit better with predictable
> schematic capture.
> 
> My concern is that I may end up like the dodo bird when it comes to
> support. A lot of the support engineers already don't use schematic
> tools and so can't answer questions about them. So if you do any serious
> design in FPGAs, you may want to go for the HDL tools and keep schematic
> as an adjunct for the tough pieces.
> 
> russell shaw wrote:
> >
> > Been there, done that, they're neither smart or helpful. If you're trying to get
> > fully familiar with using said devices and cad and tell them you wan't the
> > software for free so you can get proficient with their system and parts,
> > they'll say something like "we'll get back to you" etc (which they never do).
> >
> > Xilinx is the first outfit i approached, and they did this. I no longer talk
> > about xilinx unless asked.
> >
> > Peter Alfke wrote:
> > >
> > > Don't ventilate year-old stories about high-priced software. If you like a
> > > certain architecture, approach the salesforce and tell them what you want to do,
> > > and what you expect.
> > > They can be very smart and very helpful.
> > >
> > > Software has gotten much better, and also much more affordable.
> > >
> > > Peter Alfke, Xilinx Applications.
> > > ===============================================
> > > russell shaw wrote:
> > >
> > > > But i hate limited time licences. You just start getting into some interesting
> > > > stuff and you have to go cap in hand for more licence:(
> > > >
> > > > Jerry Avins wrote:
> > > > >
> > > > > russell shaw wrote:
> > > > > >
> > > > > > Ah, but the bit that should be free is most expensive (the software that
> > > > > > gives you the privelidge of using said cheep chips).
> > > > > >
> > > > > >
> > > > > > Peter Alfke wrote:
> > > > > > >
> > > > > > > FPGAs offer you all the flexibility you could possibly ask for, and they
> > > > > > > are not expensive any more.
> > > > > > >
> > > >
> > > > > Doesn't Altera let you have a limited-time license free?
> > > > >
> > > > > Jerry
> > > > > --
> > > > > Engineering is the art of making what you want from things you can get.
> > > > > -----------------------------------------------------------------------
> > > >
> > --
> > *******************************************
> > *   Russell Shaw, B.Eng, M.Eng(Research)  *
> > *   Electronics Consultant                *
> > *      email: russell@webaxs.net          *
> > *      Australia                          *
> > *******************************************
> 
> --
> 
> Rick Collins
> 
> rick.collins@XYarius.com
> 
> remove the XY to email me.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
> 
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
> 
> Internet URL http://www.arius.com


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20165
Subject: Re: ADC to DSP... FIFO?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 29 Jan 2000 11:44:49 -0500
Links: << >>  << T >>  << A >>
Opps again, I got my threads mixed up. This was to the right one after
all.


Rickman wrote:
> 
> Opps, I somehow posted this to the wrong thread... sorry!
> 
> Rickman wrote:
> >
> > Russell,
> >
> > I am not trying to push the Lucent stuff, but they do give away their
> > toolset which includes the front end (Viewlogic) and the back end tools
> > as well as VHDL support (or so I hear, I have not tried to use it). You
> > just have to ask your FAE to provide you with a copy. My FAE (Rick
> > Golabowski of Impact) has been very supportive (especially on snow days
> > ;). Try your distributor based FAEs.
> >
> > I like the Xilinx tools which work well if they are a bit hard to learn.
> > But I have found the Lucent tools to be very useful as well and I am
> > getting decent support from my local FAE as well as some advice from Bob
> > Wagner via postings here.
> >
> > One common point to all of the FPGA tools I have looked at; they all
> > seem to be going in the direction of HDL support. Every time I ask
> > questions the responder seems to assume that I am using an HDL ignoring
> > the possibility of my entry method being schematic. I am using schematic
> > entry because I often have pieces of my design that need to be very
> > highly optimized which I just don't have enough control via VHDL to make
> > work. So rather than do a mixed design, I just use schematic capture. I
> > also have tight schedules which I have found fit better with predictable
> > schematic capture.
> >
> > My concern is that I may end up like the dodo bird when it comes to
> > support. A lot of the support engineers already don't use schematic
> > tools and so can't answer questions about them. So if you do any serious
> > design in FPGAs, you may want to go for the HDL tools and keep schematic
> > as an adjunct for the tough pieces.
> >
> > russell shaw wrote:
> > >
> > > Been there, done that, they're neither smart or helpful. If you're trying to get
> > > fully familiar with using said devices and cad and tell them you wan't the
> > > software for free so you can get proficient with their system and parts,
> > > they'll say something like "we'll get back to you" etc (which they never do).
> > >
> > > Xilinx is the first outfit i approached, and they did this. I no longer talk
> > > about xilinx unless asked.
> > >
> > > Peter Alfke wrote:
> > > >
> > > > Don't ventilate year-old stories about high-priced software. If you like a
> > > > certain architecture, approach the salesforce and tell them what you want to do,
> > > > and what you expect.
> > > > They can be very smart and very helpful.
> > > >
> > > > Software has gotten much better, and also much more affordable.
> > > >
> > > > Peter Alfke, Xilinx Applications.
> > > > ===============================================
> > > > russell shaw wrote:
> > > >
> > > > > But i hate limited time licences. You just start getting into some interesting
> > > > > stuff and you have to go cap in hand for more licence:(
> > > > >
> > > > > Jerry Avins wrote:
> > > > > >
> > > > > > russell shaw wrote:
> > > > > > >
> > > > > > > Ah, but the bit that should be free is most expensive (the software that
> > > > > > > gives you the privelidge of using said cheep chips).
> > > > > > >
> > > > > > >
> > > > > > > Peter Alfke wrote:
> > > > > > > >
> > > > > > > > FPGAs offer you all the flexibility you could possibly ask for, and they
> > > > > > > > are not expensive any more.
> > > > > > > >
> > > > >
> > > > > > Doesn't Altera let you have a limited-time license free?
> > > > > >
> > > > > > Jerry
> > > > > > --
> > > > > > Engineering is the art of making what you want from things you can get.
> > > > > > -----------------------------------------------------------------------
> > > > >
> > > --
> > > *******************************************
> > > *   Russell Shaw, B.Eng, M.Eng(Research)  *
> > > *   Electronics Consultant                *
> > > *      email: russell@webaxs.net          *
> > > *      Australia                          *
> > > *******************************************
> >
> > --
> >
> > Rick Collins
> >
> > rick.collins@XYarius.com
> >
> > remove the XY to email me.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com
> 
> --
> 
> Rick Collins
> 
> rick.collins@XYarius.com
> 
> remove the XY to email me.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
> 
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
> 
> Internet URL http://www.arius.com


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20166
Subject: picoJava & Xilinx
From: "Anna Schmitt" <Anna.Schmitt@germanymail.com>
Date: Sat, 29 Jan 2000 19:53:48 +0100
Links: << >>  << T >>  << A >>
 Soon I'll start to work on implementing picoJava
processor in Xilinx FPGA (probably Virtex or Spartan).
If any of you has any experience with this (any useful
sugestions, information, web sites, literature,....) please
reply.

 Thanks.

 Anna Schmitt
------------------------------------
| Anna.Schmitt@germanymail.com |
------------------------------------


Article: 20167
Subject: Re: ADC to DSP... FIFO?
From: Ray Andraka <randraka@ids.net>
Date: Sat, 29 Jan 2000 19:00:00 GMT
Links: << >>  << T >>  << A >>


Rickman wrote:

> Russell,
>
> I am not trying to push the Lucent stuff, but they do give away their
> toolset which includes the front end (Viewlogic) and the back end tools
> as well as VHDL support (or so I hear, I have not tried to use it). You
> just have to ask your FAE to provide you with a copy. My FAE (Rick
> Golabowski of Impact) has been very supportive (especially on snow days
> ;). Try your distributor based FAEs.
>
> I like the Xilinx tools which work well if they are a bit hard to learn.
> But I have found the Lucent tools to be very useful as well and I am
> getting decent support from my local FAE as well as some advice from Bob
> Wagner via postings here.
>
> One common point to all of the FPGA tools I have looked at; they all
> seem to be going in the direction of HDL support. Every time I ask
> questions the responder seems to assume that I am using an HDL ignoring
> the possibility of my entry method being schematic. I am using schematic
> entry because I often have pieces of my design that need to be very
> highly optimized which I just don't have enough control via VHDL to make
> work.

> So rather than do a mixed design, I just use schematic capture. I
> also have tight schedules which I have found fit better with predictable
> schematic capture.

Amen to that.  I've been forced into VHDLs by a number of customers.  Problem is, when
pushing the performance/density, the HDLs become a nightmare and a time sink, not to
mention finding all the holes
in the corners of the tools where the average user doesn't venture.  Where many of my
jobs are fixed price,
this has just about nailed me to the wall.

I've gotten most of the things I could do in schematics working in VHDL, but the code is
hard to read and a pain in the tail to debug, and it's not portable across tools (then
again, neither was schematics).

>
>
> My concern is that I may end up like the dodo bird when it comes to
> support. A lot of the support engineers already don't use schematic
> tools and so can't answer questions about them. So if you do any serious
> design in FPGAs, you may want to go for the HDL tools and keep schematic
> as an adjunct for the tough pieces.
>
> russell shaw wrote:
> >
> > Been there, done that, they're neither smart or helpful. If you're trying to get
> > fully familiar with using said devices and cad and tell them you wan't the
> > software for free so you can get proficient with their system and parts,
> > they'll say something like "we'll get back to you" etc (which they never do).
> >
> > Xilinx is the first outfit i approached, and they did this. I no longer talk
> > about xilinx unless asked.
> >
> > Peter Alfke wrote:
> > >
> > > Don't ventilate year-old stories about high-priced software. If you like a
> > > certain architecture, approach the salesforce and tell them what you want to do,
> > > and what you expect.
> > > They can be very smart and very helpful.
> > >
> > > Software has gotten much better, and also much more affordable.
> > >
> > > Peter Alfke, Xilinx Applications.
> > > ===============================================
> > > russell shaw wrote:
> > >
> > > > But i hate limited time licences. You just start getting into some interesting
> > > > stuff and you have to go cap in hand for more licence:(
> > > >
> > > > Jerry Avins wrote:
> > > > >
> > > > > russell shaw wrote:
> > > > > >
> > > > > > Ah, but the bit that should be free is most expensive (the software that
> > > > > > gives you the privelidge of using said cheep chips).
> > > > > >
> > > > > >
> > > > > > Peter Alfke wrote:
> > > > > > >
> > > > > > > FPGAs offer you all the flexibility you could possibly ask for, and they
> > > > > > > are not expensive any more.
> > > > > > >
> > > >
> > > > > Doesn't Altera let you have a limited-time license free?
> > > > >
> > > > > Jerry
> > > > > --
> > > > > Engineering is the art of making what you want from things you can get.
> > > > > -----------------------------------------------------------------------
> > > >
> > --
> > *******************************************
> > *   Russell Shaw, B.Eng, M.Eng(Research)  *
> > *   Electronics Consultant                *
> > *      email: russell@webaxs.net          *
> > *      Australia                          *
> > *******************************************
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20168
Subject: Re: What has happened to freecore.com ?
From: "Rune Baeverrud" <fpga@iname.com>
Date: Sat, 29 Jan 2000 21:37:09 GMT
Links: << >>  << T >>  << A >>
Hello FPGA community,

freecore.com is not really gone - it's only been "away" for about two weeks
now. My service provider had a huge disk crash, and unfortunately their
backup didn't work either... It's quite a coincidence that about the same
time of the crash I was doing some household work on my harddrive and
deleted the mirror copy on my harddrive - in the belief that there were at
least two other copies availiable (the one on the server and it's backup).

I need some time to restructure the contents from older backups. I will let
you know here when I'm ready.

Regards,
Rune Baeverrud

"Steve Dewey" <steve@s-dewey123.demon.co.uk> wrote in message
news:LrrwXCAh41j4EwSn@s-dewey.demon.co.uk...
> Hi
>
> Does anyone know what has happened to the FreeCore Homepage
> (www.freecore.com)?
>
> I have not been able to get through since the start of this year.
>
> Cheers
> --
> Steve Dewey
> Remove 123 for email


Article: 20169
Subject: Re: looping FIFO?
From: "Douglas W. Olsen" <dwolsen@mediaone.net>
Date: Sun, 30 Jan 2000 00:13:38 GMT
Links: << >>  << T >>  << A >>
If you can't find an acceptable FIFO with a retransmit pin, which
"reactivates" the data that you've already accessed, you can design your
circuit to rewrite the data as you read it out.  I've used this technique
successfully; it was given to me by a FIFO vendor apps engineer.



Austin Franklin <austin@da33rkroom.com> wrote in message
news:01bf62cc$88db5830$207079c0@drt1...
> I know this isn't REALLY an FPGA question, but there are a LOT of bright
> people here..so I figured I'd ask.
>
> I am looking for an 8k x 32 FIFO (minimum) that I can load up with data of
> arbitrary length, then free-run it so it just keeps outputting data,
> looping on the data that is in it, without having to re-load it.
>
> Any ideas?
>


Article: 20170
Subject: Re: picoJava & Xilinx
From: "Steve Casselman" <sc@vcc.com>
Date: Sat, 29 Jan 2000 16:48:22 -0800
Links: << >>  << T >>  << A >>
There is an article in Integrated System Design (Jan 2000 page 45)
"The desktop FPGA design flow"
In it they compile the picojava downloaded straight from SUN.

Steve Casselman


Anna Schmitt <Anna.Schmitt@germanymail.com> wrote in message
news:86vd5v$5uu$1@bagan.srce.hr...
>


Article: 20171
Subject: Can Foundation import Viewlogic?
From: Chuck Carlson <chuck@sanna.com>
Date: Sat, 29 Jan 2000 19:59:35 -0800
Links: << >>  << T >>  << A >>

Hello all,

I found a viewlogic fifo project on the Xilinx site and would
like to import it into the Foundation system.  Is there a way
to do this?

Thanks,

Chuck Carlson


Article: 20172
Subject: Re: Xilinx programming from a Linux PC
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sat, 29 Jan 2000 23:01:37 -0500
Links: << >>  << T >>  << A >>
I've found that most of the Xilinx tools run under wine as long as you
don't use the GUIs. To run jtagprog the script would be:

#!/bin/csh -f
exec wine -winver win95 -dll shlwapi=b -managed
"$XILINX/bin/nt/jtagprog.exe $*"

Josh


Phil Endecott wrote:
> 
> Hi FPGA Experts,
> 
> I have a Virtex prototyping board from VCC (www.vcc.com) which I
> currently program from an NT PC running the Xilinx alliance tools.  The
> problem is that I run all of the other tools (VHDL simulation &
> synthesis, place & route) on a Sun; this machine is locked away in a
> machine room somewhere, and I have a Linux PC on my desk which I use as
> an X-terminal.  I'd like to be able to get rid of the NT PC and plug the
> VCC board directly into my Linux box, but I can't find a way to download
> the bit file.  What I need is either a utility that will download a bit
> file from Linux (I don't need anything like the hardware debugger), or
> alternatively a way to make the Sun version of the alliance tools talk
> to a serial port that's not on the local machine.  Xilinx support tell
> me that neither is possible.
> 
> I can't believe that I'm the only person ever to try to do this.  Does
> anyone have any experience to share?  If someone knows the protocol
> needed to talk to an X-checker or MultiLINX cable I'm happy to write my
> own tool.
> 
> Thanks in advance,
> 
> --Phil.
Article: 20173
Subject: Re: looping FIFO?
From: Ray Andraka <randraka@ids.net>
Date: Sun, 30 Jan 2000 06:10:22 GMT
Links: << >>  << T >>  << A >>
Feeding the data back into the FIFO works better than the retransmit pin for
cases where your start pointer is moving, but it does require more external
logic to make it go.  I did a FIR filter design many moons ago that used a
Weitek 1010 multiplier, two fifos, a couple of 22v10s and some bus drivers.  One
of the FIFOs held the coefficients, one had the data.  The coefficient fifo,
IIRC used the retransmit, while the data fifo used read and rewrite because it's
start point had to slide with respect to the coefficients.  All of the control
was in one 22V10, a second was for the system interface and there were a couple
that implemented saturating arithmetic at the output of the multiplier.

To use the read and rewrite, you need a set of tristateable bus drivers to
introduce your data to the FIFO.  Depending on the application (ie if you can
let the fifo output go off-line), you can use the FIFO OE in conjuction with the
tristates on your input data to make a wired OR data mux.  For the looping FIFO,
I think you can get away with a 32 bit wide set of tristate drivers, a 22v10 or
similar PLD and the FiFo

"Douglas W. Olsen" wrote:

> If you can't find an acceptable FIFO with a retransmit pin, which
> "reactivates" the data that you've already accessed, you can design your
> circuit to rewrite the data as you read it out.  I've used this technique
> successfully; it was given to me by a FIFO vendor apps engineer.
>
> Austin Franklin <austin@da33rkroom.com> wrote in message
> news:01bf62cc$88db5830$207079c0@drt1...
> > I know this isn't REALLY an FPGA question, but there are a LOT of bright
> > people here..so I figured I'd ask.
> >
> > I am looking for an 8k x 32 FIFO (minimum) that I can load up with data of
> > arbitrary length, then free-run it so it just keeps outputting data,
> > looping on the data that is in it, without having to re-load it.
> >
> > Any ideas?
> >

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20174
Subject: Re: Can Foundation import Viewlogic?
From: Ray Andraka <randraka@ids.net>
Date: Sun, 30 Jan 2000 06:16:10 GMT
Links: << >>  << T >>  << A >>
Get into the foundation schematic editor.  Under the file menu, there is
a selection for import viewlogic schematic.  The conversion is not
always clean, notably when the viewlogic design has a hierarchy that
draws from user libraries.  However, for the xilinx fifo schematics, I
think it will work fine.

Chuck Carlson wrote:

> Hello all,
>
> I found a viewlogic fifo project on the Xilinx site and would
> like to import it into the Foundation system.  Is there a way
> to do this?
>
> Thanks,
>
> Chuck Carlson

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




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