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Messages from 15375

Article: 15375
Subject: Re: FPGA vendor comparison
From: Ray Andraka <randraka@ids.net>
Date: Sun, 21 Mar 1999 13:22:10 -0500
Links: << >>  << T >>  << A >>

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I was short on time when I wrote this so I stuck to the two market leaders.

Actel has a cascaded mux structure and no carry chain, which makes it a bit
awkward for DSP applications.  With the exception of the SX (does anyone know if
that is shipping yet?) their parts are one time programmable anti-fuse.  They have
been pretty much the only contender in the Rad-hard market, so there is a niche
which only Actel fills.  Actel and Quicklogic also share the distinction of having
the program 'burned' into the device.  That of course can cut either way.  It can
be a benefit if the required function never changes, especially if the design
can't wait for configuration which can take several milliseconds.  The anti-fuse
technology also provides bitstream security that is not easily attained in the
SRAM devices like Xilinx and Altera 6K,10K,20K.  On the other hand, any design
changes require the part to be replaced, so you lose any field upgradability and
product life stretching that you get with SRAM fpgas.  The antifuse technology
does provide a denser logic array, so designs can be more routable.  Quicklogic's
'CLB' is sort of a gate tree that handles a subset of fairly wide functions quite
nicely.  To really optimize a quicklogic design, you should be aware of the cell
architecture and tailor your design to map into it.  The other long-time player is
Atmel, offering two families of SRAM based fpgas.  Both families support real
partial reconfiguration, which elevate the status of these parts above their
competition for that niche.  These devices also lack a carry chain, so their
performance suffers in DSP applications.  The 6K family is light on the routing
resource, and the cell architecture does not support the full set of 2 input logic
functions so considerable handcrafting is required to get the best performance.
That device was a wonderful device for its time (the architecture has been around
for about 10 years) as it had the highest flip-flop count and clock rates in the
industry for quite some time.  The 6K really shines with bit serial applications.
The 40K improves on the 6K archtiecture by using LUTs for the cell to obtain full
function coverage.  The 40 K also adds distributed dual port memories so that
applications requiring small amounts of memory are possible on-chip.  The
improvements however, did add delay to the cells, so the cell speeds are
comparable to the 6K speeds.  The biggest handicap of the 40K compared with the
brand X and big A competition is the lack of a fast carry chain.  By the way,
Xilinx Virtex claims to do partial reconfiguration, but it is broken.  The partial
configuration in xilinx requires you to reconfigure a whole column, which means
that any signals that cross over the column are potentially disrupted too.  The
current tools don't provide any hooks to lock routing (or for that matter even
restrict routing to an area) so that the unchanged part of a design can continue
to operate during a partial reconfiguration.  The block RAMs in Virtex are
arranged on the sides of the array, so they are more or less off-limits for a
partially configured design even if you get around the routing issues.  Atmel does
provide a true cell by cell partial reconfiguration so you can change one cell if
you want to (they also have working tools for locating and changing individual
cells).  Dynachip is a relatively new player in the market.  To be honest, I
haven't looked real hard at their chips yet.  There is also Lucent, whose
architecture is a cousin of the Xilinx architecture (they share a common ancestor)
with similar advantages as the xilinx parts.

So, in summary (from this post and last), Xilinx is a hands down winner for
arithmetic and dataflow designs and performs acceptably well with random logic.
Altera 10K is a winner for random logic and synthesis, as well as certain designs
fitting the EABs.  Actel's real niche is rad hard, although they also tout design
security.  Quicklogic also provides design security and I think the architecture
is a little easier to work with than Actel.  Atmel's niche is reconfigurable and
to some extent very fast bit serial.  Of course, there may some settling of
contents during shipping, YMMV, etc.

Richard Guerin wrote:

> Sounds like a comparison of Xilinx vs Altera !
>



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


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<HTML>
I was short on time when I wrote this so I stuck to the two market leaders.

<P>Actel has a cascaded mux structure and no carry chain, which makes it
a bit awkward for DSP applications.&nbsp; With the exception of the SX
(does anyone know if that is shipping yet?) their parts are one time programmable
anti-fuse.&nbsp; They have been pretty much the only contender in the Rad-hard
market, so there is a niche which only Actel fills.&nbsp; Actel and Quicklogic
also share the distinction of having the program 'burned' into the device.&nbsp;
That of course can cut either way.&nbsp; It can be a benefit if the required
function never changes, especially if the design can't wait for configuration
which can take several milliseconds.&nbsp; The anti-fuse technology also
provides bitstream security that is not easily attained in the SRAM devices
like Xilinx and Altera 6K,10K,20K.&nbsp; On the other hand, any design
changes require the part to be replaced, so you lose any field upgradability
and product life stretching that you get with SRAM fpgas.&nbsp; The antifuse
technology does provide a denser logic array, so designs can be more routable.&nbsp;
Quicklogic's 'CLB' is sort of a gate tree that handles a subset of fairly
wide functions quite nicely.&nbsp; To really optimize a quicklogic design,
you should be aware of the cell architecture and tailor your design to
map into it.&nbsp; The other long-time player is Atmel, offering two families
of SRAM based fpgas.&nbsp; Both families support real partial reconfiguration,
which elevate the status of these parts above their competition for that
niche.&nbsp; These devices also lack a carry chain, so their performance
suffers in DSP applications.&nbsp; The 6K family is light on the routing
resource, and the cell architecture does not support the full set of 2
input logic functions so considerable handcrafting is required to get the
best performance.&nbsp; That device was a wonderful device for its time
(the architecture has been around for about 10 years) as it had the highest
flip-flop count and clock rates in the industry for quite some time.&nbsp;
The 6K really shines with bit serial applications.&nbsp; The 40K improves
on the 6K archtiecture by using LUTs for the cell to obtain full function
coverage.&nbsp; The 40 K also adds distributed dual port memories so that
applications requiring small amounts of memory are possible on-chip.&nbsp;
The improvements however, did add delay to the cells, so the cell speeds
are comparable to the 6K speeds.&nbsp; The biggest handicap of the 40K
compared with the brand X and big A competition is the lack of a fast carry
chain.&nbsp; By the way, Xilinx Virtex claims to do partial reconfiguration,
but it is broken.&nbsp; The partial configuration in xilinx requires you
to reconfigure a whole column, which means that any signals that cross
over the column are potentially disrupted too.&nbsp; The current tools
don't provide any hooks to lock routing (or for that matter even restrict
routing to an area) so that the unchanged part of a design can continue
to operate during a partial reconfiguration.&nbsp; The block RAMs in Virtex
are arranged on the sides of the array, so they are more or less off-limits
for a partially configured design even if you get around the routing issues.&nbsp;
Atmel does provide a true cell by cell partial reconfiguration so you can
change one cell if you want to (they also have working tools for locating
and changing individual cells).&nbsp; Dynachip is a relatively new player
in the market.&nbsp; To be honest, I haven't looked real hard at their
chips yet.&nbsp; There is also Lucent, whose architecture is a cousin of
the Xilinx architecture (they share a common ancestor) with similar advantages
as the xilinx parts.

<P>So, in summary (from this post and last), Xilinx is a hands down winner
for arithmetic and dataflow designs and performs acceptably well with random
logic.&nbsp; Altera 10K is a winner for random logic and synthesis, as
well as certain designs fitting the EABs.&nbsp; Actel's real niche is rad
hard, although they also tout design security.&nbsp; Quicklogic also provides
design security and I think the architecture is a little easier to work
with than Actel.&nbsp; Atmel's niche is reconfigurable and to some extent
very fast bit serial.&nbsp; Of course, there may some settling of contents
during shipping, YMMV, etc.

<P>Richard Guerin wrote:
<BLOCKQUOTE TYPE=CITE>Sounds like a comparison of Xilinx vs Altera !
<BR><A HREF="http://users.ids.net/~randraka"></A>&nbsp;</BLOCKQUOTE>
&nbsp;

<P>--
<BR>-Ray Andraka, P.E.
<BR>President, the Andraka Consulting Group, Inc.
<BR>401/884-7930&nbsp;&nbsp;&nbsp;&nbsp; Fax 401/884-7950
<BR>email randraka@ids.net
<BR><A HREF="http://users.ids.net/~randraka">http://users.ids.net/~randraka</A>
<BR>&nbsp;</HTML>

--------------064BE1BC30DCE67050E458B5--

Article: 15376
Subject: Re: From VHDL to FPGA?
From: Richard Guerin <guerin2@home.com>
Date: Sun, 21 Mar 1999 18:36:35 GMT
Links: << >>  << T >>  << A >>
NO-SPAM damiano wrote:
<snip>
> Is there a free or low cost tool for circuit simulation starting from
> VHDL code?
<snip>

APS wrote: 
<snip>
>You may want to start out with SRAM based FPGAs.
>The two biggest vendors of these FPGAs are XILINX and Altera.

	Altera provides FREE development tools < back on my soapbox > ... See:

	http://www.altera.com/html/tools/baseline.html 

	Good Luck :-)
Article: 15377
Subject: Re: From VHDL to FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Sun, 21 Mar 1999 13:39:25 -0500
Links: << >>  << T >>  << A >>


NO-SPAM damiano wrote:

> Ok, I started looking at VHDL. Having a lot of experience with
> programming languages it does not seem too hard to manage.
> Now I need to know a few things.
>
> Is there a free or low cost tool for circuit simulation starting from
> VHDL code?
>
> Are there VHDL examples, expecially of RISC CPU cores availble for
> free, just to learn how they are coded.

You might check John McCluskey's VHDL function archive at Lucent.

>
>
> Starting from VHDL, which tools a and passes do I need to have a FPGA
> working chip (I plan to use one of the low cost PC programmers to
> begin).
>

You need a synthesis engine and the place and route tools from the
particular FPGA vendor.  While you might be able to slip by without it,
you will also want a simulator that can handle the pre-and post synthesis
design.

> (A question about FPGA, is it one time programmable or can it be
> re.programmed?)

Depends on the family.  Xilinx, Altera 6K,10K, Atmel are SRAM based..ie
infinitely reprogrammable, while Actel and QuickLogic are anti-fuse
one-time programmables.

> Having VHDL what changes do I need to go from FPGA to ASIC?
> I heard that Orbit accepts low volume orders, does someone know which
> is the minimal order and costs?

Depends on your required performance and to some degree on your synthesis
engine.  If your required performance is low, you will probably be able
to get away with the same code for both.  In higher performance designs,
you start to have to do some structural coding that may not map into an
ASIC in order to get acceptable performance in the FPGA.  Generally, a
design done for an FPGA is inefficient for an ASIC implementation, and
one designed for an ASIC will often have unsatisactory performance in an
FPGA.

>
>
> Thanks in advance,
>
> Damiano Rullo
> Trezzano S/N
> Milan, Italy
> http://members.it.tripod.de/Damianoux/index.html
> mailto: dmn@cheerful.com
> mailto: damiano@mclink.it



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15378
Subject: Re: From VHDL to FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Sun, 21 Mar 1999 13:44:47 -0500
Links: << >>  << T >>  << A >>
Austin brings up a good point.  To do well with an FPGA design, you really
need to understand the FPGA architecture and how your design should map into
it.  Without that knowledge and experience, you are likely to get very
dissappointing results.  I find the most capable FPGA designers have pretty
much all worked or are still working with schematic entry for FPGAs.  HDLs
raise the level of abstraction, and in the process it can be hard to see what
needs to be done to obtain a good FPGA implementation.

Austin Franklin wrote:

> Hi,
>
> > Ok, I started looking at VHDL. Having a lot of experience with
> > programming languages it does not seem too hard to manage.
> > Now I need to know a few things.
>
> Please don't take this as a criticism, but do you have any hardware design
> experience?  I ask because you said you have a lot of programming
> experience.  With hardware, the mindset and engineering disciplines are
> very different.
>
> Austin Franklin
> austin@darkroom.com



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15379
Subject: Re: Reconfigurable computing thesis on the web
From: zik@zikzak.net (Zik Saleeba)
Date: 22 Mar 1999 08:31:07 +1100
Links: << >>  << T >>  << A >>
Tim Tyler <tt@cryogen.com> writes:

>The most optomistic estimate I've encountered for the progress of
>FPGA-based systems into more mainstream applications envisages that a
>corner of conventional CPUs gets devoted to programable logic activities,

As you say, these estimates are for FPGA-based systems. The system
described in my thesis is not an FPGA-based system. While it evolved
from FPGA architectures it has _many_ architectural features which
divorce it from its FPGA heritage. While in common with FPGAs it uses
reconfigurable logic it operates in a very different way from FPGAs
because it was specifically designed to operate as a pure computing
device. For that matter it isn't even usable as a "field-programmable
gate array" - it's sufficiently far removed from FPGAs that it can't
really be called an FPGA any more. So as you can see performance
estimates for FPGAs do not directly apply to this new system.

I'd expect significantly better performance in computing applications
than FPGAs can achieve because the system was designed from the
ground up as a standalone computing device.

>too quickly - or, to put it another way, I wonder if it will be too
>expensive...?

This may well be - it's hard to say at this stage. Keep in mind that
this thesis was purely theoretical and sought mainly to explore if
the concept was possible. A great deal more work needs to be done
before such a system could be realised.

Zik Saleeba
Article: 15380
Subject: Re: From VHDL to FPGA?
From: (NO-SPAM)md7114@mclink.it (damiano)
Date: 21 Mar 1999 22:24:03 GMT
Links: << >>  << T >>  << A >>
On Sat, 20 Mar 1999 17:03:23, "Austin Franklin" <austin@dark8room.com>
wrote:

> Hi,
> 
> > Ok, I started looking at VHDL. Having a lot of experience with 
> > programming languages it does not seem too hard to manage.
> > Now I need to know a few things.
> 
> Please don't take this as a criticism, but do you have any hardware design
> experience?  I ask because you said you have a lot of programming
> experience.  With hardware, the mindset and engineering disciplines are
> very different.

Yes, :-)
I created a few small robots in the past, but it's not so much as my 
coding experience so I did not mark it :-)
Of course if you need to eat something you must choose what brings you
food, so I discontinued my electonic projects and went to work as a 
coder. But I did not discontinue electronic at all. While working I 
got the degree as electonic engineer.
If for HW design you mean creating PCBs and soldering I don't think 
I'll have problems, if you mean project, I have also a few experience 
with both analog and digital design, but I want to learn more and this
is the reason I'm starting with VHDL now, having a system on a chip is
just what I was searching for and developing it using a programming 
language, I think, is just the job for me. I have no problem to manage
many thousand lines of code.
And this should also increase my probabilities of finding a job as 
alectronic designer. ;-)

Damiano Rullo
Trezzano S/N
Milan, Italy
http://members.it.tripod.de/Damianoux/index.html
mailto: dmn@cheerful.com
mailto: damiano@mclink.it

Article: 15381
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Bob Efram <efram@divide.net>
Date: Sun, 21 Mar 1999 15:33:19 -0700
Links: << >>  << T >>  << A >>

There is a definite trend for FPGA/CPLD vendors to offer free software
tools.

Since these vendors have often hundreds of software engineers working on
these
tools, I suspect the cost is rolled into the FPGA itself. 

This has forced certain companies who have offered device independent
software tools out of 
business because they did not have IC's to make up the cost.

Two FPGA companies dominate the market today. They can afford to make up
software costs
by the volume of IC's they sell. 

In my humble opinion, I worry that the smaller players will be forced
out of business
the same as the device independent software companies. 

We've seen it in action with Microsoft and Internet Explorer. 
A bigger company can recover costs in other ways. 

It's good for designers to have a choice of IC's and not trend toward a
monopoly.

Personally, I favor open source software, but in that case, the entire
industry contributes
and no monopolies are created. 

There is a definite cost to these FPGA companies for creating this
software. It has to be paid by someone somehow.

Now I am off my soapbox... :-)

Bob  


Richard Guerin wrote:
> 
> Would anyone care comment on why Xilinx doesn't offer some type of free
> PC based vendor tools  ? ... it seems like every other FPGA/CPLD vendor
> does :-)
Article: 15382
Subject: Re: From VHDL to FPGA?
From: "emanuel stiebler" <emu@ecubics.com>
Date: 21 Mar 1999 23:09:53 GMT
Links: << >>  << T >>  << A >>
Hi,

Ray Andraka <randraka@ids.net> wrote in article
<36F53CDC.892B9E40@ids.net>...

> > Are there VHDL examples, expecially of RISC CPU cores availble for
> > free, just to learn how they are coded.
> 
> You might check John McCluskey's VHDL function archive at Lucent.

Any pointers ?


thanks,
emanuel
Article: 15383
Subject: Re: Bit Error Rate Test
From: Dan Dietrich <dpd@enteract.com>
Date: Sun, 21 Mar 1999 17:38:50 -0600
Links: << >>  << T >>  << A >>
Dan wrote:

> I am looking for information on building a small Bit Error Rate Tester
> inside a Xilinx.
>
> I have a Xilinx FPGA controlling a communications channel between a PCI card
> and an external cage.  I am thinking it would be useful to place a Bit Error
> Rate Tester in the Xilinx to test the link and to determine its maximum
> transfer rate.
>
> It would be simple to generate a pseudo-random pattern to transmit down the
> link, but I cannot think of an easy way to sync back up to the received
> data, and count errors.  I know this has been done before, I am just trying
> to avoid reinventing the wheel.
>
> Thanks
>
> Dan

Dan,
This might fit your needs:   http://www.enteract.com/~dpd/bertcore.html
I am not quite finished with it yet but I expect it to be ready soon.
If this looks like an option for you, let me know...
--
Dan Dietrich            Electronic Systems Development
dpd@esysdev.com
http://www.enteract.com/~dpd/esd.html


Article: 15384
Subject: Re: Bit Error Rate Test
From: jhirbawi@yahoo.com
Date: Mon, 22 Mar 1999 01:19:10 GMT
Links: << >>  << T >>  << A >>
In article <qAwI2.361$UK6.4862@news.connectnet.com>,
  "Dan" <dan@kvdco.com> wrote:
> I am looking for information on building a small Bit Error Rate Tester
> inside a Xilinx.
>
> I have a Xilinx FPGA controlling a communications channel between a PCI card
> and an external cage.  I am thinking it would be useful to place a Bit Error
> Rate Tester in the Xilinx to test the link and to determine its maximum
> transfer rate.
>
> It would be simple to generate a pseudo-random pattern to transmit down the
> link, but I cannot think of an easy way to sync back up to the received
> data, and count errors.  I know this has been done before, I am just trying
> to avoid reinventing the wheel.
>

You can sync the two by opening the feedback path in the receive lfsr and
letting the received bits (the output of the transmit lfsr) ripple into the
receive lfsr registers. If the lfsr are n-registers long, you need to let
in at least n bits; you then close the feedback path and let the receive lfsr
run on its own to give you predicted data; you can then xor the two streams
(received and predicted) to detect and count errors. This won't work if the
n bits used to sync have an error, but it's not too hard to detect that and
just try again with another n bits; if the error rate is reasonably low one
or two trials should be enough.

Jacob Hirbawi

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Article: 15385
Subject: MIL-STD-1553 implementation
From: pault888@my-dejanews.com
Date: Mon, 22 Mar 1999 01:21:03 GMT
Links: << >>  << T >>  << A >>
Hi all,

we are in the first stages of looking at a task involving the 1553 bus. Has
anyone implemented some or all of this interface (master or RT) in a PLD
(Altera 10K, AHDL or VHDL), and are willing to comment on the ease of
implementation, gotchas, amount of logic required, comparison with existing
chipsets, etc ?

Any information (or designs :-) ) would be appreciated !

Paul Teagle
CAE MRad




-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15386
Subject: Re: From VHDL to FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Sun, 21 Mar 1999 22:37:01 -0500
Links: << >>  << T >>  << A >>
emanuel stiebler wrote:

> Hi,
>
> > You might check John McCluskey's VHDL function archive at Lucent.
>
> Any pointers ?
>

took me a while to find it.  Here it is:  http://www.lucent.ca/fpga/


--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15387
Subject: Re: Xilinx Batchfile?
From: "Bruce Nepple" <brucen@imagenation.extra_words.com>
Date: Mon, 22 Mar 1999 06:05:01 GMT
Links: << >>  << T >>  << A >>
Do you have a batchfile that will work with Foundation Express HDL flow? 
Is there a sample batchfile in that mess somewhere that I've missed?

bruce

Peter <z80@ds2.com> wrote in article
<36f54871.333079883@news.netcomuk.co.uk>...
| I can't agree more, especially for projects which one needs to revisit
| years later.
| 
| However, most of the time-advantage of a makefile is that it rebuilds
| only the parts that need it. With the Xilinx tools I have used, 90+%
| of the time is spent in place&route. So a simple batch file is just as
| good.
| 
| >I miss the old makefile days.  Type one command and come back later.  No
| >fear as to whether the software will decide to consider your latest
changes
| >or not!
| 
| 
| --
| Peter.
| 
| Return address is invalid to help stop junk mail.
| E-mail replies to zX80@digiYserve.com but remove the X and the Y.
| Please do NOT copy usenet posts to email - it is NOT necessary.
| 
Article: 15388
Subject: Re: FPGA Express FSM Synthesis Concern
From: "Bruce Nepple" <brucen@imagenation.extra_words.com>
Date: Mon, 22 Mar 1999 06:08:37 GMT
Links: << >>  << T >>  << A >>
I don't think that can be done.  If you have 1 output that is the OR of two
states, then you need a comb. output.  If you are inferring flip-fops in a
process you can't have comb. outputs.

bruce

Tim Davis <timdavis@tdcon.com> wrote in article
<36F31A4A.6D6D5F48@tdcon.com>...
| Mike,
| 
| I've heard of this before. Contact Synopsys for the exact fix but I
believe you have to combine the
| state flip flops and the next state logic into one process. Then it will
work.
| 
| michaellewis@my-dejanews.com wrote:
| 
| > Hi:
| >
| > I have a concern about the synthesis of a state machine.  I
| > am implementing a 16-bit mealy state machine using the
| > "One Hot" and "fastest & smallest" options for compliling
| > in FPGA Express. It turns out that one of the outputs of
| > the state machine is functionally set when one of two
| > (logical OR) of these states is set.  However, the EDIF
| > netlist out of the tool gives 6 levels of logic to implement
| > this 2-input OR gate. In fact, it is a function of nearly all
| > (14 to be precise) state signals, as opposed to the 2 I would
| > expect.
| 
| --
| 
| Tim Davis
| Timothy Davis Consulting
| 
| TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023
| 
| 
| 
| 
Article: 15389
Subject: HDL-307 error
From: Jamie Morken <foster@uvic.ca>
Date: Sun, 21 Mar 1999 23:05:57 -0800
Links: << >>  << T >>  << A >>
Hi,

    I am having a problem with my VHDL code.  I get: "Warning: Latch
inferred in design "pc.vhd" read with hdlin_check_no_latch (HDL-307)".
    The component will synthesize with this warning.  When I make a
macro from the vhdl code, an input pin (inc_pc) that uses 'event is
missing.   I use "elsif (inc_pc'event AND inc_pc ='0')" in the code.  Is
it illegal to use 'event in an elsif?  Thanks for your time.

Jamie Morkn

Article: 15390
Subject: FLEX 10K question
From: Bill Moffitt <compass@connect.net>
Date: Mon, 22 Mar 1999 01:51:52 -0600
Links: << >>  << T >>  << A >>
Can anyone help me with an Altera 10k design?  I'm going to be
configuring a 10k device with the passive serial method (PS).  The data
book nor the app note "configuring flex 10k devices" describe what to do
with the tms, tdo, tdi, tck signals that are used for the jtag port.  Do
I need to pull these up or leave them untied?

TIA

--
Bill Moffitt


Article: 15391
Subject: Frequency synthesis techniques?
From: tommy <fu_hsuan@usa.net>
Date: Mon, 22 Mar 1999 16:43:54 +0800
Links: << >>  << T >>  << A >>
  Hi!everybody:
      I needed a DDFS(Direct Digital Frequency Synthesis) range 64KHz to
2.048MHz by using FPGA.I had two referrence frequency is 32.768MHz and
2.048MHz now.How could I to synthesis 64K,128k,192k,256k,320k..,2.048MHz
(N x 64k) frequency?Please help me.thanks.

Article: 15392
Subject: Re: FLEX 10K question
From: "Henning Trispel" <htrispel@lange-electronic.de>
Date: Mon, 22 Mar 1999 10:17:19 +0100
Links: << >>  << T >>  << A >>
I connect tdi, tck and tms to GND and that worked fine all times.

Henning


Bill Moffitt schrieb in Nachricht <36F5F698.36B77598@connect.net>...
>Can anyone help me with an Altera 10k design?  I'm going to be
>configuring a 10k device with the passive serial method (PS).  The data
>book nor the app note "configuring flex 10k devices" describe what to do
>with the tms, tdo, tdi, tck signals that are used for the jtag port.  Do
>I need to pull these up or leave them untied?
>
>TIA
>
>--
>Bill Moffitt
>
>


Article: 15393
Subject: Re: From VHDL to FPGA?
From: (NO-SPAM)md7114@mclink.it (damiano)
Date: 22 Mar 1999 10:06:33 GMT
Links: << >>  << T >>  << A >>
Ok, thanks to everybody for help.
Last few questions about FPGA:
How many gates can I get on an FPGA chip.
How many gates can I manage with an entry level tool.
Which is the lowest pin number package available.
What's the highest speed (Mhz) I can run FPGAs?

Thanks again.


Article: 15394
Subject: Re: Frequency synthesis techniques?
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Mon, 22 Mar 1999 13:23:21 +0000
Links: << >>  << T >>  << A >>
tommy wrote:
> I needed a DDFS(Direct Digital Frequency Synthesis) range 64KHz to
> 2.048MHz by using FPGA.I had two referrence frequency is 32.768MHz and
> 2.048MHz now.How could I to synthesis 64K,128k,192k,256k,320k..,2.048MHz
> (N x 64k) frequency?

The killer question is: what sort of phase resolution do you need?
or, put another way: if you want square wave output, how much jitter
in the edge timing can you tolerate?

The guts of a DDS is an accumulator register which is, let's say, 
N bits wide.  So it accumulates modulo 2^N.  Every tick of your 
32.768MHz clock, you add a constant to the accumulator.  
Call that constant M.  And to save typing we say the master 
clock frequency (32.768MHz) is Fc.

Now you can see that the accumulator is getting larger at a 
rate M.Fc per second.  So it will wrap-around modulo 2^N at a
frequency (the synthesised frequency):

Fdds = (M.Fc)/(2^N)

If you pick up the most significant bit of the accumulator, you have
a square wave at Fdds with its edges jittering by up to one cycle of 
the Fc clock.  If you want a sine wave, you can use the accumulator 
contents as the address into a lookup table, where 0 corresponds 
to zero degrees, 2^(N-1) corresponds to 180 deg.  and 2^N takes you
back to 360 degrees (zero).  When the output of this table is fed
to a DAC you wukk get a sinewave (or other, depending on your table
contents) output, but it will have a staircase appearance, which 
can be improved with a little analog filtering, and by various other 
cunning interpolation tricks which are known as error diffusion, 
noise shaping or anti-aliasing depending on which field of 
electronics/software endeavour you happen to inhabit.

Now, let's arrange that M is configurable (from a bunch of input 
pins, maybe).  Given that M is obviously an integer, you can easily
see that the increase in frequency as M increases by one is

dF = Fc/(2^N)

which tells you what N must be since you know Fc=32.768MHz and
dF=64kHz  (sounds like N=9 to me).  It's then easy to determine
what your largest M will need to be,

Mmax = Fmax/dF = 2048kHz/64kHz = 32

NB:  The adder which adds M to the current accumulator contents
will almost certainly have a carry input.  If you force that
carry input to 1, it's like M being one bigger than you thought
it was - so you need to supply (M-1) which is in the range 0-31:
only five bits needed as input to that adder, then!

Now I've done your homework, can I lay claim to the marks please?

Extension activities:
(1) optimise the accumulator by using only a 5-bit adder and
    a counter macro from your chosen FPGA
(2) design an appropriate analog output filter
(3) investigate how to get a sinewave output from this
    type of DDS when only a 1-bit D/A converter is available
(4) show how the sinewave output from this kind of DDS can
    be processed (analog circuitry) to develop a square wave
    with edge jitter much less than the period of Fc
(5) use piecewise linear approximations to obtain sinewave
    output when using an FPGA architecture like QuickLogic
    that cannot easily support ROM lookup tables
(6) show how operation could be pushed to Fc=150MHz in a
    non-Xilinx device (with no carry chains) by using
    (a) conditional-sum adder, (b) pipelined adder

But above all, have fun.

Jonathan Bromley
Article: 15395
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Mon, 22 Mar 1999 13:35:07 +0000
Links: << >>  << T >>  << A >>
Richard Guerin wrote:
> IMHO, an example of one vendor (out of several) that has done an
> exemplary job in offering FREE tools is QuickLogic.  Their QuickChip
> product is a comprehensive & quality vendor specific tool (I really love
> SpDE's colorful post layout physical view) .... and it is totally FREE

Nice to hear someone else supporting QuickLogic's tools.  For those
of us not as lucky as you, Richard, QuickLogic's policy of packaging
good quality design entry tools (Silos, Synplify, Synario) as a 
very well-integrated kit at a reasonable price has won them at 
least one avid fan.  QL were offering this sort of stuff way back in the
early 90s when X***'s and A***'s tools were still in the flint-axe class.

As far as SpDE's physical view is concerned, I remember Bruce Kleinman
from QL saying that it let FPGA designers put die-shots on their walls
like the macho ASCI brigade;  yes, it's pretty! - but it isn't much
use for anything else, is it?  Do you remember the delights of discovering
that a QuickLogic device, 100% utilised, would route EVERY TIME with NO
TWEAKING even when you screwed down the pins according to some daffy 
PCB layout?  Seems like X***** have just about caught up with that now.

Jonathan Bromley
Article: 15396
Subject: Re: From VHDL to FPGA?
From: "emanuel stiebler" <emu@ecubics.com>
Date: 22 Mar 1999 14:43:49 GMT
Links: << >>  << T >>  << A >>
Hi,

Ray Andraka <randraka@ids.net> wrote in article
<36F5BADC.1A64C86A@ids.net>...

> took me a while to find it.  Here it is:  http://www.lucent.ca/fpga/

Thanks a lot. I found nothing with the US lucent search engines :-((

emanuel
Article: 15397
Subject: Re: From VHDL to FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Mon, 22 Mar 1999 10:38:11 -0500
Links: << >>  << T >>  << A >>


NO-SPAM damiano wrote:

> Ok, thanks to everybody for help.
> Last few questions about FPGA:
> How many gates can I get on an FPGA chip.

Depends on the size of the FPGA, your definition of a 'gate', and the
circuit you are putting in.  FPGA sizes range from around 2K to a
million marketing gates.  Marketing gates are a vendor's claimed gate
count and vary from vendor to vendor.  Personally, I find it more useful
to count CLBs.

> How many gates can I manage with an entry level tool.

Depends on the vendor.  They are usually limited to under 10K gates.

> Which is the lowest pin number package available.

I'm not sure any more on the low end. 84 pin PLCC's and 100 pin TQFPs
are close

> What's the highest speed (Mhz) I can run FPGAs?

Depends on the speed grade of the device, and your design.  Peter Alfke
has demonstrated a 400MHz frequency counter in a 4000XL part.  For data
path stuff, if you do the floorplanning and are careful in the
implementation, you can get over 100 MHz for 16 bit arithmetic.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15398
Subject: ALTERA Byteblaster configuration for DOS and LINUX
From: danger <danger@enst.fr>
Date: Mon, 22 Mar 1999 15:44:15 +0000
Links: << >>  << T >>  << A >>
Has anybody a small routine to configure ALTERA devices via the
Byteblaster from a DOS and and LINUX system ?

Thank you

--
Jean-Luc DANGER                       email : danger@enst.fr
ENST/dpt ComElec   46 rue Barrault               75013 PARIS
Phone : 01 45 81 81 17                  Fax : 01 45 80 40 36


Article: 15399
Subject: UPDATE: The Programmable Logic Jump Station (www.optimagic.com)
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 22 Mar 1999 07:46:55 -0800
Links: << >>  << T >>  << A >>
There's been an update!  See what's new on The Programmable
Logic Jump Station at


                   http://www.optimagic.com/
             http://www.optimagic.com/whatsnew.html


The Programmable Logic Jump Station is a comprehensive set of
links to nearly all matters related to programmable logic.



Featuring:
---------


          --- Frequently-Asked Questions (FAQ) ---


Programmable Logic FAQ - http://www.optimagic.com/faq.html
A great resource for designers new to programmable logic.



          --- FPGAs, CPLDs, FPICs, etc. ---


Recent Developments - http://www.optimagic.com
Find out the latest news about programmable logic.


Device Vendors - http://www.optimagic.com/companies.html
FPGA, CPLD, SPLD, and FPIC manufacturers.


Device Summary - http://www.optimagic.com/summary.html
Who makes what and where to find out more.


Market Statistics - http://www.optimagic.com/market.html
Total high-density programmable logic sales and market share.



            --- Development Software ---


Free and Low-Cost Software - http://www.optimagic.com/lowcost.shtml
Free, downloadable demos and evaluation versions from all the major
suppliers.


Design Software - http://www.optimagic.com/software.html
Find the right tool for building your programmable logic design.


Synthesis Tutorials - http://www.optimagic.com/tutorials.html
How to use VHDL or Verilog.



              --- Related Topics ---


FPGA Boards - http://www.optimagic.com/boards.html
See the latest FPGA boards and reconfigurable computers.


Design Consultants - http://www.optimagic.com/consultants.html
Find a programmable logic expert in your area of the world.


Research Groups - http://www.optimagic.com/research.html
The latest developments from universities, industry, and
government R&D facilities covering FPGA and CPLD devices,
applications, and reconfigurable computing.


News Groups - http://www.optimagic.com/newsgroups.html
Information on useful newsgroups.


Related Conferences - http://www.optimagic.com/conferences.html
Conferences and seminars on programmable logic.


Information Search - http://www.optimagic.com/search.html
Pre-built queries for popular search engines plus other
information resources.


The Programmable Logic Bookstore - http://www.optimagic.com/books.html
Books on programmable logic, VHDL, and Verilog.  Most can be
ordered on-line, in association with Amazon.com



            . . . and much, much more.


Bookmark it today!







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