Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 15425

Article: 15425
Subject: Re: viterbi coder/decoder
From: Ray Andraka <randraka@ids.net>
Date: Tue, 23 Mar 1999 17:42:03 -0500
Links: << >>  << T >>  << A >>
I know Greg Goslin formerly of Xilinx and Diablo Research did a viterbi decoder in xilinx.  There is a
little info in one of the conference papers that he did (look in the xilinx app notes for that).

Andres David Garcia Garcia wrote:

> HI,
>
> I'd like to know if anybody is or was working on a design of a viterbi
> coder/decoder
> or a treillis application using FPGAs.
>
> thank you
>
> Andres David
>
>   ------------------------------------------------------------------------
>
>   Andres David Garcia Garcia <garcia@elec.enst.fr>
>   PhD Student on Electronics and Communications
>   Ecole Nationale Superieure des Telecommunications
>   Dept. Communications et Electronique
>
>   Andres David Garcia Garcia
>   PhD Student on Electronics and Communications      <garcia@elec.enst.fr>
>   Ecole Nationale Superieure des Telecommunications  HTML Mail
>   Dept. Communications et Electronique
>   46, rue Barrault ;Paris;;75634;France              Pager: http://www-elec.enst.fr/~garcia/index.html
>                                                      Fax: (33-1)-45-80-40-36
>                                                      Home: (33-1)-44-16-18-90
>                                                      Work: (33-1)-45-81-78-03
>   Additional Information:
>   Last Name Garcia Garcia
>   First NameAndres David
>   Version   2.1



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15426
Subject: Re: FPGA vendor comparison
From: "Daniel K. Elftmann" <dan.elftmann@actel.com>
Date: Tue, 23 Mar 1999 19:01:07 -0500
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

>  I was short on time when I wrote this so I stuck to the two market
> leaders.
>
> Actel has a cascaded mux structure and no carry chain, which makes it
> a bit awkward for DSP applications.  With the exception of the SX
> (does anyone know if that is shipping yet?)

Qualified devices for A54SX08, A54SX16, A54SX16P, and A54SX32 are all
shipping in commercial and industrial grades.

Daniel K. Elftmann
Actel Northeast Field Applications Engineer
Email: dan.elftmann@actel.com
Phone: 978-244-3827
Fax: 978-244-3820


> <snip>

Article: 15427
Subject: AnyVoltage Altera ByteBlaster 1.8V-5.5V
From: eugenef@jps.net
Date: Wed, 24 Mar 1999 01:31:34 GMT
Links: << >>  << T >>  << A >>
FPGA Downloader for Altera FPGA/EPLD - ONLY $75.00

Works with any voltage from target board 1.8 V  - 5.5 V
Replaces Altera ByteBlaster and ByteBlaster MV downloader

You will never need another downloader

Please visit us at:  http://welcome.to/nefdesign.com

Sincerely,

NEF Design, Inc.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15428
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Joel.Kolstad@USA.Net
Date: Wed, 24 Mar 1999 01:39:01 GMT
Links: << >>  << T >>  << A >>
In article <36F53552.AAD35162@home.com>,
  Richard Guerin <guerin2@home.com> wrote:
> APS wrote:
> >
> > They get pretty close with the Foundation Base Tools at $99.00.
>
> That's not FREE !

Yeah, but if you can't afford $99 for the tools, I doubt you can afford to
purchase enough chips to ever offset the cost of of the real development price
of the tools (well over $99 per copy, I'd think) minus that initial $99.

It's nice that other vendors give away their lower ends tools for free -- I've
certainly taken advantage of this myself, and encourage others to do so.
However, I don't begrude Xilinx their $99 at all, when I do think it costs far
more than that for the tools be be produced.

If you have volume, a distributor will be more than happy to hand you the
tools for free.  Heck, I bet most distributors will gladly give you a copy of
the $99 package if you're buying 100 parts per month on a continuous basis. 
If it's more like 10K a month, you'll have Xilinx, Altera, Vantis, and
everybody else offering to give you their high end (~$5-$10K) tools if you
commit to using their parts.

There's probably something to be said for the argument that handing out
unsupported tools for free doesn't really cost Xilinx anything and may gain
them some customers.  Perhaps they figure that, for $99, you'll at least
spend some time to fully evaluate their tool set and get to know its power --
despite its quirks -- instead of just grabbing the nice free piece of P&R
software that you can get your hands on?

> Why do the do this when "these tools are costly to keep up and
> keep current" ?  Simple .... they want you to use their products and
> providing FREE tools helps enable designers to do so ... in fact, for
> some, the FREE tools could become the differentiator in selecting their
> products over a competitor's.

For low volumes, maybe.  For high volumes, anyone who doesn't consider the
overall cost of commiting to a particular vendor needs to be fired.  Companies
like Cisco spend millions of dollars per year with Xilinx, and I can't imagine
that $5K for the tools was at all a high priority in their selection criteria.

---Joel Kolstad

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15429
Subject: VHDL source code
From: David Braendler <dbraendler@swin.edu.au>
Date: Wed, 24 Mar 1999 12:28:40 +1000
Links: << >>  << T >>  << A >>
Can anyone provide some pointers to free/shareware VHDL code which is
available for Active-VHDL / XILINX ?

Cheers.

Dave Breandler
Swinburne University of Technology

Article: 15430
Subject: Re: HDL-307 error
From: Jamie Morken <foster@uvic.ca>
Date: Tue, 23 Mar 1999 23:51:49 -0800
Links: << >>  << T >>  << A >>
Ya, that looks familiar all right :)  What is the best way you found to fix
this $%^&% error?  I have tried 20 different ways to load increment and
reset a single register with no luck yet.   Thanks for your time.
Jamie Morken

Article: 15431
Subject: big/little endian mishap
From: Jamie Morken <foster@uvic.ca>
Date: Tue, 23 Mar 1999 23:57:53 -0800
Links: << >>  << T >>  << A >>
Hi,

I am using the Xilinx simulator for VHDL macro's.  When I was simulating, I
noticed that an 8 bit input bus was being inverted before storing in an
internal register.  The code is supposed to store the value off the bus
without inverting it.  Any help?  Thanks.

Jamie Morken

Article: 15432
Subject: Re: Jedec programming standard?
From: Chip Willman <XchipX@zip.com.auX>
Date: Wed, 24 Mar 1999 18:29:03 +1000
Links: << >>  << T >>  << A >>
Hi Peter

Despite what people may tell you about the programming voltages difference
between A & B parts and different manufacturers, the programming algorithm is
the same on all 16V8's and the difference in programming voltages is usually 1-4
volts.  The reason most old device programmers will not program newer devices is
because the device ID is not recognized.  Most 16V8's are very robust and will
be placed in program mode with a 16.5 Volt edit signal applied to pin 2.

Because of this problem (It was the weekend and the new devices I got wouldn't
work on my Allpro 88 universal programmer) , I designed a simple GAL16V8
programmer with information I remembered from Logical Devices (my former
employer who also designed the Allpro 88). The example files were added to the
ProtelWeb site at http://www.protel.com/library/app_galprog.htm .

It does require an Windows 95/NT computer and the Advanced Schematic 98 from
Protel to read the schematic.  A 30 day trial version of Protel 98 is available
free to download at Protel's website http://www.protel.com .  The Gal
Programmer.exe is a very simplistic interface which requires the Port95nt
Parallel Port Drivers to be installed on the machine.  Also included is the
Delphi Source code used to create the program, and it definately could use a
touch up in several places.

This project was originally designed for students and hobbyists as a low cost
alternative to a device programmer.  Without the ZIFF socket, the parts cost
less than $20 most people probably already have all the parts.  Instead of a
ZIFF socket, I actually used a Perf-Board to do the programming.  Out of the 50
times I used it to program 16V8's that weekend, I only destroyed 1 device when I
turned the Voltage Knob instead of the Current Knob and send 25 Volts to the
Power Pin of the 16V8.

Cheers
Chip Willman




Peter Hiscocks wrote:

> Hi all -
>
> We're finding it a constrant struggle to keep our programmers up to date in
> programming small scale programmable logic devices: 16V8's. Every
> manufacturer has a different algorithm, and every revision of the device
> seems to change the algorithm too.
>
> One of my older programmers can still do EPROMs but is completely
> non-functional for reading and writing 16V8's. And, of course as has been
> explained here before, the manufacturers are very reluctant to give out the
> programming information.
>
> The result is that the big guys in the logic progammer business, and only
> the big guys, have the resources to keep their logic device programmers up
> to date. This is in contrast to the EPROM programming business, which is
> more or less standardized, and as a consequence one can buy an EPROM
> programmer at a reasonable price and be confident it will not be a boat
> anchor in 5 years.
>
> For example, it is completely within reason for a student to purchase an
> EPROM programmer, but a logic progammer is far too expensive.
>
> In circuit progammable devices are an attractive alternative to this mess,
> and the somewhat higher price is not a major problem to the student or small
> quantity user. Unfortunately, these devices do not seem to be second-sourced
> and of course they are not nearly as readily available as the 16V8. For
> example, in Toronto, Active Surplus, notable by the animated gorilla on the
> doorstep, has Lattice 16V8's for $3, which is unlikely to be the case for
> ISP devices for the forseeable future.
>
> I would argue that a standard programming algorithm will entice new, low
> cost programmers into the market and open up larger markets for the devices
> themselves. After all, it's clear that 7400 bubblegum logic is on the way
> out.
>
> There are no villains in this case that I can see, but surely there needs to
> be some sort of JEDEC standard for programming these very common,
> second-sourced devices. So, why can't we have a standard for this?
>
> Peter
>
> --
> Peter Hiscocks                            Phone: (416) 979-5000 Ext 6109
> Department of Electrical Engineering      Fax:   (416) 979-5280
> Ryerson Polytechnic University,           Email: phiscock@ee.ryerson.ca
> Toronto, Ontario, M5B 2K3, Canada
>
>    *******************************************************************
>    *    There are worse things than being wrong, and being           *
>    *       dull and pedantic are surely among them.                  *
>    *                                                                 *
>    *    Mark Kac, in 'Discrete Thoughts:                             *
>    *     Essays on Mathematics, Science and Technology'              *
>    *******************************************************************

Article: 15433
Subject: Re: HDL-307 error
From: Nicolas Matringe <nicolas@dot.com.fr>
Date: Wed, 24 Mar 1999 09:40:43 +0100
Links: << >>  << T >>  << A >>
Jamie Morken wrote:
> 
> Ya, that looks familiar all right :)  What is the best way you found
> to fix this $%^&% error?  I have tried 20 different ways to load
> increment and reset a single register with no luck yet.

Apart from doing a synchronous load (see below), I don't know

IF reset...
ELSIF clk...
  IF load = '1' THEN
    reg <= value;
  ELSE
    reg <= reg + 1;
  END IF;
END IF;


Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
mail reply : remove one dot from my address (guess which :o)
Article: 15434
Subject: Re: HELP ME : About JTAG on Altera Flex 10k
From: Steve@XXX_REMOVE_XXXrsn-tech.demon.co.uk (Steve Rencontre)
Date: Wed, 24 Mar 1999 09:48:10 GMT
Links: << >>  << T >>  << A >>
On Tue, 23 Mar 1999 21:01:35 +0900, "Honey News"
<honey@hyowon.pusan.ac.kr> wrote:

>Can anybody announce me about Sequence of JTAG execution?

Sorry, don't understand exactly what you're asking.

>And, What is BSDL(Boundary-Scan Description Language)?

It's the formal description of the chip features that can be accessed
via the JTAG port. It tells you what control you have over which pins,
what the instructions are to put the chip into each test mode, stuff
like that.

>Is BSDL essential to JTAG?

Not in principle, but in practice, yes.

>Please, Help me.
>
>Young Han Kim

For an excellent hands-on simulator, try the Texas "Scan Educator",
which runs under DOS or an NT/9x DOS box (maybe even a Unix DOS
emulation - dunno!) available at
http://www.ti.com/sc/docs/jtag/educ.htm

After that, you might like to check out my web site for a beta-test
product you can use to talk to real hardware with the Altera
ByteBlaster or similar. http://www.rsn-tech.demon.co.uk/pjtag
--
Steve Rencontre, Design Consultant
http://www.rsn-tech.demon.co.uk/  --  remember to despam return address
Article: 15435
Subject: Xilinx Programming ?
From: roman pollak <roman.pollak@swiss.sun.com>
Date: Wed, 24 Mar 1999 11:00:31 +0100
Links: << >>  << T >>  << A >>
Hi,

I know this question was asked maybe many times here.
But which part of the .bit file is actualy downloaded to the
device self ?
Does anybody may have an C example ?

thanks roman
Article: 15436
Subject: Synplify -> MaxPlus II
From: Markus Michel <mmichel@kius.ch>
Date: Wed, 24 Mar 1999 12:18:28 +0100
Links: << >>  << T >>  << A >>
Hello,

I synthesize VHDL code with Synplify 5.0.8 for Altera Flex10K into an
EDIF file.
MaxPlus II then reports
"Error: can't find design file 'inv1'"
"Error: can't find design file 'S_DFFE'".
Does anybody know what's wrong?

thanks and regards,
Markus


Article: 15437
Subject: Re: Reconfigurable computing thesis on the web
From: mikesw@whiterose.net (M Sweger)
Date: 24 Mar 1999 11:26:08 GMT
Links: << >>  << T >>  << A >>
Stephen Maudsley (Stephen.Maudsley@esgem.com) wrote:
: Zik Saleeba wrote:

: > I've put together an online version of my recent thesis on
: > reconfigurable computing for people to view on the web or download as
: > postscript.
: >
: > The idea behind the thesis was to create a new kind of computer
: > architecture based around reconfigurable logic which was effective
: > not only for the rarified set of problems current FPGA systems are
: > applicable to - but could also be applied to the same sorts of
: > problems as conventional general-purpose processors.
: >
: > Enjoy!
: >
: > http://www.cs.monash.edu.au/~zik/thesis.html
: >
: > ---------------------------------------------------------------------
: > Abstract
: >
: > In the fast-paced field of computing new technologies appear, are
: > developed and then become outdated all within a few years. The
: > underlying architectural precepts on the other hand remain relatively
: > constant. Modern CPUs use the same sequential execution model which
: > has been with us since Von Neumann. The latest processors use
: > performance features such as caching, deep pipelining and register
: > scoreboarding which are really only minor adaptations of techniques
: > which have been used for twenty years.
: >
: > Reconfigurable logic arrays give us the opportunity to embrace an
: > entirely new approach to computing. The technology is still young so
: > there is a great deal to be done before this new medium reaches the
: > maturity of conventional processors. Current reconfigurable logic
: > arrays are limited to specialised custom computing tasks and are not
: > suitable for the wide variety of tasks which general purpose
: > computers tackle.
: >

Question: I haven't read the paper yet, but how does this differ from the
 fault tolerant computers from a few years back? And if the paper describes
the methods to dynamically change the hardware for a specific application, do
you take into account the capability to dynamically isolate a bad logic
cell? This is an algorithm too, although not a computational one per se.
There has been some work in this area whereby one creates hardware *rings*
of different levels so that one can isolate the bad hardware. The generic
logic that is used to build all higher level logic is the T-cell (flip-flop).
The "T" standing I guess for test. 

So I guess what I'm saying, is that hopefully it is a general solution from
an application point of view and also a testing and reliability point of view.
I believe the same algorithm concepts can drive both situations. The hardware
dynamically reconfigures to optimize for the best performance that can be
achieved (since any particular algorithm in parallel processing has a specific
hardware architecture that is optimal for it - no general solution) and also 
has the capability to run a *test* algorithm so that it can dynamically
reconfigure around and or isolate a hardware fault. This
test reconfiguration can switch out bad processors, functional units (i.e.
ALUs), chips, and lastely gates on the chip. 

Conclusion: 

Need a dynamic hardware solution for the specific application
alogrithm and one for fault isolation and testing to maintain optimal
performance and reliability. Otherwise, it isn't a total solution but
falls into the realm of an application specific or maintainability and
reliability problem.






--
	Mike,
	mikesw@whiterose.net

Article: 15438
Subject: DIY Xilinx Download Cable
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Wed, 24 Mar 1999 11:27:33 -0000
Links: << >>  << T >>  << A >>
Having just attended a Xilinx symposium, and now being the proud owner of
the Software Sampler CD-ROM, which includes development tools for some of
the Spartan range, I need a download cable. On the Xilinx web site I found a
schematic of what appears to be a suitable cable:

    www.xilinx.com/support/programr/jtag_cable.pdf

Can anyone confirm that this is the correct cable for these devices?

Leon

leon_heller@hotmail.com


Article: 15439
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: z80@ds2.com (Peter)
Date: Wed, 24 Mar 1999 11:32:19 GMT
Links: << >>  << T >>  << A >>

I paid $15,000 for Xilinx tools of similar capability, in 1991 and
1996. :)

>Yeah, but if you can't afford $99 for the tools, I doubt you can afford to
>purchase enough chips to ever offset the cost of of the real development price
>of the tools (well over $99 per copy, I'd think) minus that initial $99.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 15440
Subject: Info about FPGA/PLD
From: "FFabio" <filippa@tekel.it>
Date: Wed, 24 Mar 1999 13:42:03 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm a joung electronic engineer (MT), my work is on
power electronics, but for teoretical study the
control can be feed on FPGA or PLD device.

Could you please send me some information about this?
What is the adavantage of one type of device instead of the
other one?

Obviously the FPGA is more flexible than PLD, but is cost expensive.


Best regards
Fabio



Article: 15441
Subject: Re: HDL-307 error
From: mench@mench.com
Date: 24 Mar 1999 09:01:50 -0500
Links: << >>  << T >>  << A >>
Jamie Morken <foster@uvic.ca> wrote:
> Ya, that looks familiar all right :) What is the best way you found
> to fix this $%^&% error?  I have tried 20 different ways to load
> increment and reset a single register with no luck yet.  Thanks for
> your time.  Jamie Morken

Remember, this is a *warning*, not an error.

If you're creating a register, then you *want* a latch, as you're
trying to store a value!

Paul


-- 
Paul Menchini          | mench@mench.com | "Non si vive se non il
OrCAD                  | www.orcad.com   |  tempo che si ama."
P.O. Box 71767         | 919-479-1670[v] |  --Claude Adrien Helvetius
Durham, NC  27722-1767 | 919-479-1671[f] |
Article: 15442
Subject: Re: big/little endian mishap
From: mench@mench.com
Date: 24 Mar 1999 09:02:53 -0500
Links: << >>  << T >>  << A >>
Jamie Morken <foster@uvic.ca> wrote:
> I am using the Xilinx simulator for VHDL macro's.  When I was
> simulating, I noticed that an 8 bit input bus was being inverted
> before storing in an internal register.  The code is supposed to
> store the value off the bus without inverting it.  Any help?

Perhaps if you post the code, we can get a better idea.

Paul

-- 
Paul Menchini          | mench@mench.com | "Non si vive se non il
OrCAD                  | www.orcad.com   |  tempo che si ama."
P.O. Box 71767         | 919-479-1670[v] |  --Claude Adrien Helvetius
Durham, NC  27722-1767 | 919-479-1671[f] |
Article: 15443
Subject: Booth or Wallace Trees Multipliers
From: Dennis Garcia <d_garcia@routes.com>
Date: Wed, 24 Mar 1999 10:30:56 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0F0D53693C1533755CB90EFE
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi

I working on a design where I'm implementing some DSP function i.e.
multipliers
I would like to get information on how to design  mutilpliers  using
Booth or Wallace Trees algorithms for implementation in Xilinx or Actel
fpga.
any reference on  schematic or VHDL are appreciated.

thanks
Dennis


--------------0F0D53693C1533755CB90EFE
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dennis  Garcia
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             Dennis  Garcia
n:              Garcia;Dennis 
org:            Routes Inc.
adr:            ;;303 Legget Dr.;Kanata;Ontario;K2K 2B1;Canada
email;internet: d_garcia@routes.com
title:          Electronics Technologist
tel;work:       (613) 592-0748
tel;fax:        (613) 592-6553
x-mozilla-cpt:  ;0
x-mozilla-html: FALSE
version:        2.1
end:            vcard


--------------0F0D53693C1533755CB90EFE--

Article: 15444
Subject: Re:Synplify -> MaxPlus II
From: yves@px.uk.com (Yves Tchapda)
Date: Wed, 24 Mar 1999 15:46:07 GMT
Links: << >>  << T >>  << A >>


Hi Markus,

Make sure in MAXPLUS II, you  set the Library Mapping File or LMF in
short  in the EDIF Netlist Reader settings to <<Synplicity>>.

I hope this helps

DR Yves Tchapda
Design Engineer
Power X, England

Article: 15445
Subject: Re:JTAG on Altera Flex 10k (Yves Tchapda)
From: yves@px.uk.com (Yves Tchapda)
Date: Wed, 24 Mar 1999 16:01:44 GMT
Links: << >>  << T >>  << A >>
Hi Young,
1- BSDL is a VHDL-like language which defines the boundary scan ports
as well as the code for the boundary scan instructions (SAMPLE/LOAD,
EXTEST, IDCODE). Note that the bypass instruction is defined by IEEE
1149.1 as all 1's.

2-The sequence is as follows: At power up, the TAP controller state
machine goes to the reset state and the inital instruction in the
instruction register depends on the device ( could be BYPASS or
IDCODE). To load an instruction, you move the TAP controller state
machine to the instruction scan mode and shift the instruction. The
data phase is then entered by moving the the TAP controller to the
data scan mode where the data can also be shifted.
For instance, testing for PCB interconnect would involve loading the
following instructions SAMPLE/PRELOAD followed by EXTEST in the
instruction register Remember the data is loaded or sampled during
data scan mode.

Altera defines different instruction codes across different devices.

I hope this helps

DR Yves Tchapda
ASIC Design Engineer
Power X, England
Article: 15446
Subject: Re: Current State of FPGA-based PCI Interfaces?
From: Tim Davis <timdavis@tdcon.com>
Date: Wed, 24 Mar 1999 09:16:18 -0700
Links: << >>  << T >>  << A >>
Bob Bauman wrote:

> Wiggo,
>
> Aren't the Lucent devices with hardcoded PCI interface logic fairly pricey?
>
>

I checked. The lucent device is roughly $125/ea. I'm considering using it in a design. I'd much
rather use the Xilinx core because the virtex 300 part is much larger than the 3TP12 from Lucent. I
suspect the Xilinx support is going to be about 100 times better also. (I think they have the best
support of any EDA vendor out there). Other factors may prevent the Xilinx choice unfortunately.


--

Tim Davis
Timothy Davis Consulting

TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023


Article: 15447
Subject: Re: Booth or Wallace Trees Multipliers
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 24 Mar 1999 08:56:17 -0800
Links: << >>  << T >>  << A >>
Ray Andraka of the Andraka Consulting Group has some useful material at

http://users.ids.net/~randraka/multipli.htm.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


Dennis Garcia wrote in message <36F90530.2C63F151@routes.com>...
>Hi
>
>I working on a design where I'm implementing some DSP function i.e.
>multipliers
>I would like to get information on how to design  mutilpliers  using
>Booth or Wallace Trees algorithms for implementation in Xilinx or Actel
>fpga.
>any reference on  schematic or VHDL are appreciated.
>
>thanks
>Dennis
>
>


Article: 15448
Subject: Re: Info about FPGA/PLD
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 24 Mar 1999 09:02:24 -0800
Links: << >>  << T >>  << A >>
You can find lots of information about FPGAs and CPLDs on The Programmable
Logic Jump Station at http://www.optimagic.com.  In specific, you may be
interested in the Frequently-Asked Questions (FAQ) at
http://www.optimagic.com/faq.html and the FPGA/CPLD comparison at
http://www.optimagic.com/comparison.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

FFabio wrote in message <922279251.521866@claudia.ihnet.it>...
>Hi,
>
>I'm a joung electronic engineer (MT), my work is on
>power electronics, but for teoretical study the
>control can be feed on FPGA or PLD device.
>
>Could you please send me some information about this?
>What is the adavantage of one type of device instead of the
>other one?
>
>Obviously the FPGA is more flexible than PLD, but is cost expensive.
>
>
>Best regards
>Fabio
>
>
>


Article: 15449
Subject: Has anyone used Virtex DLLs for multiple clocks.
From: David Reid <dreid@corp.atl.com>
Date: Wed, 24 Mar 1999 09:22:02 -0800
Links: << >>  << T >>  << A >>
Has anyone successfully used the Virtex DLL to generate and deskew
multiple clocks internal and external to the chip. I am planning to use
the DLL to generate a 2x clock which will be used internal and external
and which must be deskewed with the 1x used internally. Clocks are 48M
and 96M.

I've read all the application notes and data sheets, was just wondering
if anyone actually got it to work well. I'm apprehensive about doing
this for the first time.


Dave Reid



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search