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Messages from 18700

Article: 18700
Subject: Re: Downloading Xilinx FPGA with just .bit file???
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 08 Nov 1999 19:10:16 +0000
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> Ray, thanks.
>
> So now I have to go setup every guy in the lab and the production floor,
> who used to be able to just use a little 486 notebook w/ a 20M disk and
> DOS, with some version of Windoze, a mouse, and a project
> directory...instead of just XChecker and a .bit file on a floppy...  To me,
> this seems silly to have made it 'so' complicated when it used to be so
> easy.
>
> Also, is there a way of doing it from the command line, as opposed to
> having to bring up the GIU, select 'stuff' etc.?
>
> Austin
>

I'm not sure about the h/w debugger but you can run the JTAG programmer tool
from the command line. However I had problems gettingthe 1.5i version to run
under Win95. Works o.k from the NT machine even though this needs 2 extender
cables to reach the lab bench.

Article: 18701
Subject: Need a good Pullup for a VHDL Test Bench
From: "Chris" <csbeasley@nospworldnet.att.net>
Date: 8 Nov 1999 20:17:06 GMT
Links: << >>  << T >>  << A >>
Hello, I am hoping that someone has a really good model for a pullup in a
VHDL test bench that can convert a bidirectional signal between an 'H' and
a '1'.

I realize that I can just assign and 'H' to a signal in the test bench to
pull up the signal when not driven by my device under test (DUT).  The
problem is that the DUT has a state machine that looks for the
bidirectional signal (that is its input and output pin) to be a '1' during
certain states.  As you could guess, the state machine never progresses in
simulation due to the 'H' on the signal.  The device performs well
in-circuit because the resistor on the circuit board pulls the signal to a
logic 1 on the board.

The issue is pulling up the bidirectional signal with something like an 'H'
and converting that to a logic '1' in simulation so that the internal DUT
"sees" a '1' when just pulled up by the test bench pullup.

Any help is greatly appreciated.  Please post the response on the newsgroup
so that it may help others, rather than replying by email.


Article: 18702
Subject: Altera Releases First in New Line of PLDs
From: tgallati@hotmail.com
Date: Mon, 08 Nov 1999 20:39:38 GMT
Links: << >>  << T >>  << A >>

Altera Corporation (San Jose, CA) has begun to ship the first in its
20KE line of programmable logic devices (PLDs): the EP20K400E.

The device implements 400,000 gates (one million maximum system
gates), and is based on the 0.18 micron, six-layer-metal, 1.8-V
process. It features on-chip content-addressable memory (CAM),
low-voltage differential signaling (LVDS), and phase locked loops
(PLLs), which allows designers to create System-on-a-Programmable-Chip
silicon (SOPC) silicon for applications like Layer 3 routers and
switches, wideband CDMA baseband signal processing, and ATM cell
processing and traffic management.

http://www2.embeddedtechnology.com/welcome/ngck
Article: 18703
Subject: Re: ROM or SRAM !? - who really cares?
From: rk <stellare@NOSPAM.erols.com>
Date: Mon, 08 Nov 1999 16:42:00 -0500
Links: << >>  << T >>  << A >>
hi ray,

Ray Andraka wrote:

> Rich,
>
> I'm pretty sure the current crop of xilinx and altera parts could handle this data rate
> with minimal pipelining. I've done an FIR filter in xilinx with 16 bit wide parallel
> arithmetic that runs at around 150 MHz in a Virtex -4 (slowest speed grade).  I've also
> done 16 bit arithmetic designs in 4000XLA-07's that run in the high 140 MHz range.  His
> input is 155Mb/s and it is paralleled down to a maximum data rate of 78 MHz.  The
> encoder output is 10 bits, so a reasonable guess is any arithmetic inside is likely to
> be less than 10 bits. The maximum width into the encoder is 4 bits, so if it is
> combinatorial, the logic is one LUT deep in both Altera and Xilinx.  Obviously, not
> knowing the details of the encoder blocks, we can't really tell how complicated they
> are, but based on the observations of the input and output widths a first guess
> indicates that it is possible.

the original poster seems to want a non-volatile solution for the lab ... i'm not sure
exactly why ... but i believe that most modern fpgas could probably handle this without too
much trouble.  i haven't run timing analyses yet on the new sx-a stuff, which would be the
latest actel part, and a bit fresher than the q-logic devices which is a few years old, at
least with respect to technology  (almost two years ago, with non-speed graded devices, i
was able to get 500 MHz+ ripple counter performance, so they're not exactly slow pokes).
they seem to be spending more time on hard-wired cores, adding value that way, a bit
different approach then the actelians.  i do know from some lab experiments on early sx-a
prototypes [day job] that they are quite fast.  i think that, if i get some time, i will
download the software for sx-a (a 3 hour download here so not at the top of my list of
things to do today) and perhaps run some analyses to see how fast a circuit like this could
run, making some assumptions for the encoder.  architecturally, they don't have the carry
chain like the xilinx 4k and virtex devices, which is fast, since it's hardwired.  for
those not familiar with the devices, starting in sx, and continuing in sx-a, they have some
higher speed routing resources, direct connect (no antifuses) and fast connect (one
antifuse) in addition to the regular routing - note that starting in sx they changed
antifuse structure, cutting the antifuse resistance by approximately 1 order of magnitude
while moving away from the channelled architecture.  however, without the carry chain, a
ripple adder will be relatively slow and a look ahead technique would be needed. of course,
i'm not sure exactly what's in his encoder, perhaps not even math.  now there were some
talks talking about speed/power vs. different devices at mapld '99, i'll have to get those
proceedings (a few papers still in need of finalization) out so i can look at what they
came up with :-)

-----------------------------------------------------

> I haven't looked at the Actel selection lately, so I don't know what kinds of speed you
> can expect there.  I do know there is no carry chain, so you have to be careful in the
> selection of the logic used in artihmetic.

your're right, in sx and sx-a there is no carry chain.  i don't believe there is one in
their gatefield-designed devices either (someone yell if i got that wrong).  for their sram
devices, (not yet released), there's a description in the following architecture paper (
http://rk.gsfc.nasa.gov/richcontent/papers/actel_sram_architecture99.pdf  ).  they moved to
lut's, although at a different size then the xilinx guys, using a mixture of 2 and 3-input
luts.  they also have different types of routing, but it's been a while since i've read
that paper closely.  if only i had more time ... :(

-------------------------------------------------------------------------------

> A possibility might be to use a CPLD for this.  Most of the CPLDs are non-volatile, and
> many support in system reprogrammability.  If the system is as simple as represented
> here, I see no reason it wouldn't fit into one of the many CPLDs out there.  Again, the
> data rates are within the realm of possibility for the currently available devices with
> careful design.

again, this shouldn't be hard to fit into a number of different devices.  for a lab
instrument, not sure why one would have a preference for a "rom" or "ram" types, unless
they want to keep the design secure with minimum hassle <rk carefully avoids the long
design security thread>

well,

back to work,

rk

Article: 18704
Subject: Re: Need a good Pullup for a VHDL Test Bench
From: "peter dudley" <padudle@worldnet.att.net>
Date: Mon, 8 Nov 1999 17:45:28 -0700
Links: << >>  << T >>  << A >>
You can modify your vhdl to check if the signal in question is equal to an
'H' or a '1'.

if ( ( sig1 = '1' ) or ( sig1 = 'H' ) ) then

Not too elegant, but that's how I do it. It will synthesize the same but it
will simulate the way you want.

    Pete Dudley


Chris <csbeasley@nospworldnet.att.net> wrote in message
news:01bf2a26$35b8f1a0$0a24450c@c1...
> Hello, I am hoping that someone has a really good model for a pullup in a
> VHDL test bench that can convert a bidirectional signal between an 'H' and
> a '1'.
>
> I realize that I can just assign and 'H' to a signal in the test bench to
> pull up the signal when not driven by my device under test (DUT).  The
> problem is that the DUT has a state machine that looks for the
> bidirectional signal (that is its input and output pin) to be a '1' during
> certain states.  As you could guess, the state machine never progresses in
> simulation due to the 'H' on the signal.  The device performs well
> in-circuit because the resistor on the circuit board pulls the signal to a
> logic 1 on the board.
>
> The issue is pulling up the bidirectional signal with something like an
'H'
> and converting that to a logic '1' in simulation so that the internal DUT
> "sees" a '1' when just pulled up by the test bench pullup.
>
> Any help is greatly appreciated.  Please post the response on the
newsgroup
> so that it may help others, rather than replying by email.
>
>


Article: 18705
Subject: Re: Need a good Pullup for a VHDL Test Bench
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Tue, 09 Nov 1999 01:48:43 GMT
Links: << >>  << T >>  << A >>
On 8 Nov 1999 20:17:06 GMT, "Chris" <csbeasley@nospworldnet.att.net>
wrote:

>Hello, I am hoping that someone has a really good model for a pullup in a
>VHDL test bench that can convert a bidirectional signal between an 'H' and
>a '1'.
>
>I realize that I can just assign and 'H' to a signal in the test bench to
>pull up the signal when not driven by my device under test (DUT).  The
>problem is that the DUT has a state machine that looks for the
>bidirectional signal (that is its input and output pin) to be a '1' during
>certain states.  As you could guess, the state machine never progresses in
>simulation due to the 'H' on the signal.  The device performs well
>in-circuit because the resistor on the circuit board pulls the signal to a
>logic 1 on the board.
>
>The issue is pulling up the bidirectional signal with something like an 'H'
>and converting that to a logic '1' in simulation so that the internal DUT
>"sees" a '1' when just pulled up by the test bench pullup.
>
>Any help is greatly appreciated.  Please post the response on the newsgroup
>so that it may help others, rather than replying by email.

Look at the to_X01() function in ieee.std_logic_1164.  It converts '1'
and 'H' to '1'; '0' and 'L' to '0' and the rest get converted to 'X'.

Regards,
Allan.
Article: 18706
Subject: Re: PLD Quesiton
From: "Adam J. Elbirt" <aelbirt@nac.net>
Date: Mon, 08 Nov 1999 21:38:55 -0500
Links: << >>  << T >>  << A >>
Viewlogic provides a jed2ahdl utility though I don't know if it's reliable
or if it's still available given the developments of AMD -> Vantis ->
Lattice.

Adam

Michael Ayton wrote:

> Is it possible to read back the contents of an older 16L8 pld and make a
> schematic from the jedec ???

--
"Sometimes I think the surest sign that there's intelligent life on
other planets is that none of it has tried to contact us."
                                      - Calvin, "Calvin and Hobbes"


Article: 18707
Subject: PLD Quesiton
From: "Michael Ayton" <mayton@gnt.com>
Date: Mon, 8 Nov 1999 19:46:43 -0800
Links: << >>  << T >>  << A >>
Is it possible to read back the contents of an older 16L8 pld and make a
schematic from the jedec ???




Article: 18708
Subject: Reverse Engineering a 16L8
From: "Michael Ayton" <mayton@gnt.com>
Date: Mon, 8 Nov 1999 20:09:44 -0800
Links: << >>  << T >>  << A >>
Anyone know if it is possible to reverse engineer a 16L8???  and get some
sort of code from it other than the JEDEC?

Thanks


Article: 18709
Subject: Problems in Viewlogic's Workview office
From: Leslie Yip (/ Loui) <leslie.yip@asmpt.com>
Date: Tue, 09 Nov 1999 04:13:34 GMT
Links: << >>  << T >>  << A >>
 Hello all

Can anyone solve the two problems found in ViewLogic's Workview office
7.5:

(1) When I use FPGA Express (included in WVOffice 7.5)
 to synthesize my design, it generates the EDIF file
for Altera's MAXplus to fit into the device.
The generated EDIF file flattens my bus (defined in VHDL)
, so when I do backannotation (post simulation), I have
to re-define my test bench in Speedwave (a VHDL simulator) for doing
backannotation.

For example, I defined in VHDL:
FREQ:in	std_logic_vector(35 downto 0);

Then in the backannotation file, it becomes
FREQ35: in std_logic;
FREQ34: in std_logic;
FREQ33: in std_logic;
FREQ32: in std_logic;
FREQ31: in std_logic;
..
FREQ1: in std_logic;
FREQ0: in std_logic;

It will make every designer very upset to do much typing.
I have checked the files, it is the problem in EDIF file generated by
FPGA Express.

Can you solve the bug?

(2) Besides, FPGA Express can't synthesize the VHDL LPM generated
files, which are generated from Altera's MaxPlus.

The error message is: (access violation)
FEXP caused an invalid page fault in
module DPMW.DLL at 0137:1005eec7.
Registers:
EAX=02d0c074 CS=0137 EIP=1005eec7 EFLGS=00010206
EBX=00000000 SS=013f ESP=0269fad0 EBP=00000000
ECX=02eb8d78 DS=013f ESI=02dbfe08 FS=3977
EDX=02f0c770 ES=013f EDI=02eb8d8c GS=0000
Bytes at CS:EIP:
8b 3b 52 e8 81 6b fb ff 83 c4 04 89 30 8b 44 24
Stack dump:
02ec6158 02ca1c08 02feaa08 00780d08 02d0c4ac 02eb8d78 02eb8d50 02f0c770
02f0c790 02eb8d78 00000000 02f0c750 02f0c820 02ca1c08 0000001c 00780d08


Below is the VHDL file (multip.vhd)

-- megafunction wizard: %LPM_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_mult

-- ============================================================
-- File Name: multip.vhd
-- Megafunction Name(s):
-- 			lpm_mult
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************


--	Copyright (C) 1988-1999 Altera Corporation

--	Any megafunction design, and related net list (encrypted or
decrypted),
--	support information, device programming or simulation file, and
any other
--	associated documentation or information provided by Altera or a
partner
--	under Altera's Megafunction Partnership Program may be used only
to
--	program PLD devices (but not masked PLD devices) from Altera.
Any other
--	use of such megafunction design, net list, support information,
device
--	programming or simulation file, or any other related
documentation or
--	information is prohibited for any other purpose, including, but
not
--	limited to modification, reverse engineering, de-compiling, or
use with
--	any other silicon devices, unless such use is explicitly
licensed under
--	a separate agreement with Altera or a megafunction partner.
Title to
--	the intellectual property, including patents, copyrights,
trademarks,
--	trade secrets, or maskworks, embodied in any such megafunction
design,
--	net list, support information, device programming or simulation
file, or
--	any other related documentation or information provided by
Altera or a
--	megafunction partner, remains with Altera, the megafunction
partner, or
--	their respective licensors.  No other licenses, including any
licenses
--	needed under any third party's intellectual property, are
provided herein.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY multip IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END multip;


ARCHITECTURE SYN OF multip IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);



	COMPONENT lpm_mult
	GENERIC (
		LPM_WIDTHA		: NATURAL;
		LPM_WIDTHB		: NATURAL;
		LPM_WIDTHP		: NATURAL;
		LPM_WIDTHS		: NATURAL;
		INPUT_B_IS_CONSTANT		: STRING;
		LPM_REPRESENTATION		: STRING;
		USE_EAB		: STRING;
		LPM_PIPELINE		: NATURAL
	);
	PORT (
			dataa	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
			datab	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
			clock	: IN STD_LOGIC ;
			result	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	result    <= sub_wire0(31 DOWNTO 0);

	lpm_mult_component : lpm_mult
	GENERIC MAP (
		LPM_WIDTHA => 16,
		LPM_WIDTHB => 16,
		LPM_WIDTHP => 32,
		LPM_WIDTHS => 32,
		INPUT_B_IS_CONSTANT => "NO",
		LPM_REPRESENTATION => "SIGNED",
		USE_EAB => "OFF",
		LPM_PIPELINE => 1
	)
	PORT MAP (
		dataa => dataa,
		datab => datab,
		clock => clock,
		result => sub_wire0
	);



END SYN;

-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: WidthA NUMERIC "16"
-- Retrieval info: PRIVATE: WidthB NUMERIC "16"
-- Retrieval info: PRIVATE: WidthS NUMERIC "32"
-- Retrieval info: PRIVATE: WidthP NUMERIC "32"
-- Retrieval info: PRIVATE: OptionalSum NUMERIC "0"
-- Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
-- Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
-- Retrieval info: PRIVATE: SignedMult NUMERIC "1"
-- Retrieval info: PRIVATE: USE_EAB NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
-- Retrieval info: PRIVATE: Latency NUMERIC "1"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: PRIVATE: optimize NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "32"
-- Retrieval info: CONSTANT: INPUT_B_IS_CONSTANT STRING "NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: USE_EAB STRING "OFF"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL
result[31..0]
-- Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0




--
Hong Kong


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18710
Subject: Re: Problems in Viewlogic's Workview office
From: Alan Fitch <alan.fitch@doulos.com>
Date: Tue, 9 Nov 1999 09:09:31 +0000
Links: << >>  << T >>  << A >>
In article <80871c$58t$1@nnrp1.deja.com>, Leslie Yip
<leslie.yip@asmpt.com> writes
> Hello all
>
>Can anyone solve the two problems found in ViewLogic's Workview office
>7.5:
>
>(1) When I use FPGA Express (included in WVOffice 7.5)
> to synthesize my design, it generates the EDIF file
>for Altera's MAXplus to fit into the device.
>The generated EDIF file flattens my bus (defined in VHDL)
>, so when I do backannotation (post simulation), I have
>to re-define my test bench in Speedwave (a VHDL simulator) for doing
>backannotation.
>
>For example, I defined in VHDL:
>FREQ:in        std_logic_vector(35 downto 0);
>
>Then in the backannotation file, it becomes
>FREQ35: in std_logic;
>FREQ34: in std_logic;
>FREQ33: in std_logic;
>FREQ32: in std_logic;
>FREQ31: in std_logic;
>..
>FREQ1: in std_logic;
>FREQ0: in std_logic;
>
>It will make every designer very upset to do much typing.
>I have checked the files, it is the problem in EDIF file generated by
>FPGA Express.
>
>Can you solve the bug?
>

This isn't a bug, it's a feature! (Sorry). You can try changing the bus
style in the VHDL output settings of FPGA Express, but my experience was
that it did not help. Also, I found that the latest version of FPGA
Express (3.3) is better at getting busses right.

To fix it in VHDL, you can write a configuration. Here is an example
from our Comprehensive VHDL course design flow exercise.

--
-- exflow/src/cfgxilinx_synopsysfe3.vhd
--
-- Configuration for gate level simulation with output from Synopsys
-- FPGA Express Version 3 (Viewlogic).
--
-- Rev  Author  Date    Comment
-- ====================================================================
-- 001  APF     990219  Created                               ISSUE1.43
-- 
use work.all;
configuration CfgGate of chiptb is
  for Bench                           -- test bench architecture name
    for all : chip
      use entity work.chip(Structure) -- (gate level architecture name)
        port map
        (nReset    => nReset,
         Enable    => Enable,
         Load      => Load,
         UpDn      => UpDn,
         Data0     => Data(0),
         Data1     => Data(1),
         Data2     => Data(2),
         Data3     => Data(3),
         Data4     => Data(4),
         Clk25M    => Clk25M,
         TestClk   => TestClk,
         nTestMode => nTestMode,
         nDispA0   => nDispA(0),
         nDispA1   => nDispA(1),
         nDispA2   => nDispA(2),
         nDispA3   => nDispA(3),
         nDispA4   => nDispA(4),
         nDispA5   => nDispA(5),
         nDispA6   => nDispA(6),
         nDispB0   => nDispB(0),
         nDispB1   => nDispB(1),
         nDispB2   => nDispB(2),
         nDispB3   => nDispB(3),
         nDispB4   => nDispB(4),
         nDispB5   => nDispB(5),
         nDispB6   => nDispB(6),
         nLed0     => nLed(0),
         nLed1     => nLed(1),
         nLed2     => nLed(2),
         nLed3     => nLed(3),
         nLed4     => nLed(4),
         nLed5     => nLed(5),
         nLed6     => nLed(6),
         nLed7     => nLed(7)
         );
    end for;
  end for;
end;


As you can see, this one was actually written for Viewlogic! 
As I say, with the later versions, I didn't need it any more.

Also, if your circuit changes too much, you may have to write a new
configuration.

>(2) Besides, FPGA Express can't synthesize the VHDL LPM generated
>files, which are generated from Altera's MaxPlus.
>
>The error message is: (access violation)
>FEXP caused an invalid page fault in
>module DPMW.DLL at 0137:1005eec7.
>Registers:
This is one for Viewlogic - I have found them very helpful fixing bugs.

kind regards

Alan


-- 
Alan Fitch
DOULOS Ltd. 
        Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK
Tel: +44 (0)1425 471 223                    Email: alan.fitch@doulos.com
Fax: +44 (0)1425 471 573             
**               Visit THE WINNING EDGE  www.doulos.com               **

Article: 18711
Subject: Re: Virtex Board
From: NOJUNK@gecm.com (Graham Millar)
Date: Tue, 09 Nov 1999 09:36:40 GMT
Links: << >>  << T >>  << A >>
On Thu, 14 Oct 1999 01:31:17 -0400, "abdulqadir alaqeeli"
<alaqeeli@bobcat.ent.ohiou.edu> wrote:

>Hi,
>Does anyone know where I find a PCI Board with a Virtex Chip?
>I found the following two companies:
>Avnet:  http://www.em.avnet.com/semi/marketing/xlx-19990526semw.html
>Embedded Solutions Ltd  ( RC1000-PP)
>
>I need any helpful information so I can choose a good board.
>
>Abdul
>
>
>
Try the company call NallaTech  whose web site is
http:/www.nallatech.com

-- 
Replace NOJUNK with graham.millar to reply.
Article: 18712
Subject: Re: AMCC 5933 Woes
From: deroberts@my-deja.com
Date: Tue, 09 Nov 1999 10:11:32 GMT
Links: << >>  << T >>  << A >>
In article <7vum2f$lji$1@lure.pipex.net>,
  "david garnett" <dave.garnett@metapurple.co.uk> wrote:
> I'm trying to make a bus master PCI interface with an AMCC5933 and a
> Coolrunner PLD, and I'm having real problems getting dma transfers to
work
> for more than a few words - specifically, transfers of greater than
about 16
> words usually hang the pci bus after a few (or many) transfers. Any
help,
> information or suggestions of a suitable ng would be very welcome !
>
Personally, I wouldn't bother.

I worked on a 5933 design 3 years ago. Several bugs in the 5933 resulted
in the entire project being aborted.

The most serious of these is that when operating in master mode, if the
PCI target happens to request a retry on the last item of your burst
then the following events happen.

1) Your FIFO is marked empty (which it is)

2) You load the next target address (because your're ready to do the
next DMA and you think your FIFO is empty)

3) The 5933 uses THIS NEW ADDRESS to write the retried item which is
sitting in an undocumented 'holding' register off the end of the FIFO -
i.e. writes the last item of data for your last DMA burst to the first
address of your new DMA.

4) The 5933 then goes and increments the target address register and
delivers the rest of your DMA data to addr+4 etc.

It is not possible to work around this bug without snooping the PCI bus
(and consequently breaking the loading rules) to determine that retry
has happened at the end of your DMA.  I have not seen this bug either
acknowledged by AMCC or reported fixed. I'd also be happy to see AMCC
say that this bug has been found and fixed, but unless it has, your
design will be doomed so far as DMA mastering is concerned.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18713
Subject: Re: Problems in Viewlogic's Workview office
From: Michael Schmid <mlschmid@iis.fhg.de>
Date: Tue, 09 Nov 1999 11:11:49 +0000
Links: << >>  << T >>  << A >>
"Leslie Yip (/ Loui)" wrote:
> 
>  Hello all
> 
> Can anyone solve the two problems found in ViewLogic's Workview office
> 7.5:
> 
> (1) When I use FPGA Express (included in WVOffice 7.5)
>  to synthesize my design, it generates the EDIF file
> for Altera's MAXplus to fit into the device.
> The generated EDIF file flattens my bus (defined in VHDL)
> , so when I do backannotation (post simulation), I have
> to re-define my test bench in Speedwave (a VHDL simulator) for doing
> backannotation.
> 
> For example, I defined in VHDL:
> FREQ:in std_logic_vector(35 downto 0);
> 
> Then in the backannotation file, it becomes
> FREQ35: in std_logic;
> FREQ34: in std_logic;
> FREQ33: in std_logic;
> FREQ32: in std_logic;
> FREQ31: in std_logic;
> ..
> FREQ1: in std_logic;
> FREQ0: in std_logic;
> 
> It will make every designer very upset to do much typing.
> I have checked the files, it is the problem in EDIF file generated by
> FPGA Express.
> 
> Can you solve the bug?
> 
> (2) Besides, FPGA Express can't synthesize the VHDL LPM generated
> files, which are generated from Altera's MaxPlus.
> 
> The error message is: (access violation)
> FEXP caused an invalid page fault in
> module DPMW.DLL at 0137:1005eec7.
> Registers:
> EAX=02d0c074 CS=0137 EIP=1005eec7 EFLGS=00010206
> EBX=00000000 SS=013f ESP=0269fad0 EBP=00000000
> ECX=02eb8d78 DS=013f ESI=02dbfe08 FS=3977
> EDX=02f0c770 ES=013f EDI=02eb8d8c GS=0000
> Bytes at CS:EIP:
> 8b 3b 52 e8 81 6b fb ff 83 c4 04 89 30 8b 44 24
> Stack dump:
> 02ec6158 02ca1c08 02feaa08 00780d08 02d0c4ac 02eb8d78 02eb8d50 02f0c770
> 02f0c790 02eb8d78 00000000 02f0c750 02f0c820 02ca1c08 0000001c 00780d08
> 
> Below is the VHDL file (multip.vhd)
> 
> -- megafunction wizard: %LPM_MULT%
> -- GENERATION: STANDARD
> -- VERSION: WM1.0
> -- MODULE: lpm_mult
> 
> -- ============================================================
> -- File Name: multip.vhd
> -- Megafunction Name(s):
> --                      lpm_mult
> -- ============================================================
> -- ************************************************************
> -- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
> -- ************************************************************
> 
> --      Copyright (C) 1988-1999 Altera Corporation
> 
> --      Any megafunction design, and related net list (encrypted or
> decrypted),
> --      support information, device programming or simulation file, and
> any other
> --      associated documentation or information provided by Altera or a
> partner
> --      under Altera's Megafunction Partnership Program may be used only
> to
> --      program PLD devices (but not masked PLD devices) from Altera.
> Any other
> --      use of such megafunction design, net list, support information,
> device
> --      programming or simulation file, or any other related
> documentation or
> --      information is prohibited for any other purpose, including, but
> not
> --      limited to modification, reverse engineering, de-compiling, or
> use with
> --      any other silicon devices, unless such use is explicitly
> licensed under
> --      a separate agreement with Altera or a megafunction partner.
> Title to
> --      the intellectual property, including patents, copyrights,
> trademarks,
> --      trade secrets, or maskworks, embodied in any such megafunction
> design,
> --      net list, support information, device programming or simulation
> file, or
> --      any other related documentation or information provided by
> Altera or a
> --      megafunction partner, remains with Altera, the megafunction
> partner, or
> --      their respective licensors.  No other licenses, including any
> licenses
> --      needed under any third party's intellectual property, are
> provided herein.
> 
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> LIBRARY lpm;
> USE lpm.lpm_components.all;
> 
> ENTITY multip IS
>         PORT
>         (
>                 dataa           : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
>                 datab           : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
>                 clock           : IN STD_LOGIC ;
>                 result          : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
>         );
> END multip;
> 
> ARCHITECTURE SYN OF multip IS
> 
>         SIGNAL sub_wire0        : STD_LOGIC_VECTOR (31 DOWNTO 0);
> 
>         COMPONENT lpm_mult
>         GENERIC (
>                 LPM_WIDTHA              : NATURAL;
>                 LPM_WIDTHB              : NATURAL;
>                 LPM_WIDTHP              : NATURAL;
>                 LPM_WIDTHS              : NATURAL;
>                 INPUT_B_IS_CONSTANT             : STRING;
>                 LPM_REPRESENTATION              : STRING;
>                 USE_EAB         : STRING;
>                 LPM_PIPELINE            : NATURAL
>         );
>         PORT (
>                         dataa   : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
>                         datab   : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
>                         clock   : IN STD_LOGIC ;
>                         result  : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
>         );
>         END COMPONENT;
> 
> BEGIN
>         result    <= sub_wire0(31 DOWNTO 0);
> 
>         lpm_mult_component : lpm_mult
>         GENERIC MAP (
>                 LPM_WIDTHA => 16,
>                 LPM_WIDTHB => 16,
>                 LPM_WIDTHP => 32,
>                 LPM_WIDTHS => 32,
>                 INPUT_B_IS_CONSTANT => "NO",
>                 LPM_REPRESENTATION => "SIGNED",
>                 USE_EAB => "OFF",
>                 LPM_PIPELINE => 1
>         )
>         PORT MAP (
>                 dataa => dataa,
>                 datab => datab,
>                 clock => clock,
>                 result => sub_wire0
>         );
> 
> END SYN;
> 
> -- ============================================================
> -- CNX file retrieval info
> -- ============================================================
> -- Retrieval info: PRIVATE: WidthA NUMERIC "16"
> -- Retrieval info: PRIVATE: WidthB NUMERIC "16"
> -- Retrieval info: PRIVATE: WidthS NUMERIC "32"
> -- Retrieval info: PRIVATE: WidthP NUMERIC "32"
> -- Retrieval info: PRIVATE: OptionalSum NUMERIC "0"
> -- Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
> -- Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
> -- Retrieval info: PRIVATE: SignedMult NUMERIC "1"
> -- Retrieval info: PRIVATE: USE_EAB NUMERIC "0"
> -- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
> -- Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
> -- Retrieval info: PRIVATE: Latency NUMERIC "1"
> -- Retrieval info: PRIVATE: aclr NUMERIC "0"
> -- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
> -- Retrieval info: PRIVATE: optimize NUMERIC "0"
> -- Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
> -- Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
> -- Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
> -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "32"
> -- Retrieval info: CONSTANT: INPUT_B_IS_CONSTANT STRING "NO"
> -- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
> -- Retrieval info: CONSTANT: USE_EAB STRING "OFF"
> -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
> -- Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
> -- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL
> result[31..0]
> -- Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
> -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
> -- Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
> -- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
> -- Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
> -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
> 
> --
> Hong Kong
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Hi,


I think I can help you with your
Netlist. After Chip-Optimization with
FPGA-Express you can mark the optimized
chip and push the right mouse button.
There you find 'export netlist'. A
window pops up where you can define the
bus style of the exported netlist.
Actually You have 'EXPAND'. Try another
one which is appropriate to Max-Plus.
Now press OK and the netlist is written
once again but this time with the
selected bus notation. After every
synthesis you will have to do this step
by yourself. I think there was a way to
change the default settings but i don't
know it anymore. Maybe another one knows
about this.


Bye,

Michael 


mlschmid@iis.fhg.de
Article: 18714
Subject: Re: Frequency Division in Altera AHDL ?
From: jessiek@polbox.com
Date: Tue, 09 Nov 1999 12:42:23 GMT
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hello Anton,
<br>there are a few solutions in my opinion. You can solve this task using
<br>both gdf&amp;tdf and tdf only based design entry. You wrote about AHDL
<br>implementation only, but this is not the easiest way.
<br>However, in fact, what you look for is a frequency divider with 2/3
<br>ratio.
<br>My proposition is: build&nbsp; a frequency divider with 1/3 ratio and
then
<br>multiply it by 2 (or vice versa).
<br>Another way is to create a special synchronous machine based on counter
<br>with combinatorial feed-back circuitry forcing the counter to work
with
<br>an appropriated cycle.
<br>Contact me if you are still interested in the solution.
<p>PS. You send a question with no more details (e.g. there is no
<br>information about duty cycle), so real solution will be the best when
<br>design's constraints are fully defined. What is it to be, your design
I
<br>mean? Which and what version of Altera's software do you use?
<p>Regards,
<br>Jessie
<p>Anton Erasmus wrote:
<blockquote TYPE=CITE>Hi,
<p>I am trying to get a 16MHz Frequency from a 24MHz Clock on a Altera
<br>EPM7128. The 24MHz Clock is connected to one of the global clock
<br>inputs. Can anyone help me in doing this in AHDL ?
<p>Regards
<br>&nbsp;&nbsp; Anton Erasmus</blockquote>
</html>

Article: 18715
Subject: Sample Rate Conversion.
From: Srikanth Gurrapu <gurrapu@ti.com>
Date: Tue, 09 Nov 1999 10:21:32 -0600
Links: << >>  << T >>  << A >>
Hello all,

I'm looking for a VHDL/verilog model for a sample rate converter,
probably for FPGA implementations. For e.g., I want to design
a module for upconverting 44.1kHz/22.05kHz/11.025kHz audio samples to
48kHz.

Could somebody help me in getting some pointers for this.
Thanks in advance,

--
Regards,
-Srikanth.
Texas Instruments, Inc.
gurrapu@ti.com
972-480-2318



Article: 18716
Subject: Re: Virtex Board
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 9 Nov 1999 08:51:44 -0800
Links: << >>  << T >>  << A >>
You can find a fairly comprehensive list of Virtex boards on The
Programmable Logic Jump Station at http://www.optimagic.com/boards.html.


--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Graham Millar <NOJUNK@gecm.com> wrote in message
news:3827e9f4.437697816@news.geccs.gecm.com...
> On Thu, 14 Oct 1999 01:31:17 -0400, "abdulqadir alaqeeli"
> <alaqeeli@bobcat.ent.ohiou.edu> wrote:
>
> >Hi,
> >Does anyone know where I find a PCI Board with a Virtex Chip?
> >I found the following two companies:
> >Avnet:  http://www.em.avnet.com/semi/marketing/xlx-19990526semw.html
> >Embedded Solutions Ltd  ( RC1000-PP)
> >
> >I need any helpful information so I can choose a good board.
> >
> >Abdul
> >
> >
> >
> Try the company call NallaTech  whose web site is
> http:/www.nallatech.com
>
> --
> Replace NOJUNK with graham.millar to reply.


Article: 18717
Subject: Re: Need a good Pullup for a VHDL Test Bench
From: "Chris" <csbeasley@nospworldnet.att.net>
Date: 9 Nov 1999 17:41:53 GMT
Links: << >>  << T >>  << A >>
Thanks to all who have replied, or may still reply to my post.
Article: 18718
Subject: orcad synthesis for simplepld
From: seamang@westminster.ac.uk (Graham Seaman)
Date: 9 Nov 1999 17:55:08 GMT
Links: << >>  << T >>  << A >>
I'm new to using ORCAD (I have tried mailing them/using their notice board
with no response so far) - does anyone have any experience of using
the Express synthesis for simpleplds (actually GAL22V10)?
I have a little behavioural VHDL FSM which analyzes ok; when I try to build
it Express generates an error message telling me I have too many
product terms for a couple of rows. On inspecting the vhdl netlist
its generated, there are actually not many PTs in the expressions
its complaining about - well within the powers of a 22V10!
Is there a common user error which could generate this? Or is this
a known problem for which a patch is available?  (I have v. 7.1)


Thanks for any advice,

Graham Seaman
Article: 18719
Subject: Re: Simulation of FPGA design. Please Help!
From: Brian Philofsky <brianp@xilinx.com>
Date: Tue, 09 Nov 1999 10:08:18 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------DED6A3B2420B0CAB7336F407
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Rick Filipkiewicz wrote:

> Brian Philofsky wrote:
>
> >
> >
> >
> > If you wish to simulate the design with logic level delays but not
> > wire delays, this is possible if you run the synthesized netlist
> > through the Xilinx M1 tools to the Map stage.  Run the ncd file that
> > Map outputs through ngdanno and then run the nga file from ngdanno
> > through ngd2vhdl.  The command sequence will look like:
> >
> > ngdbuild <design_netlist>
> > map -o logic_sim.ncd <design>.ngd
> > ngdanno logic_sim.ncd
> > ngd2vhdl logic_sim.nga
> >
> >
> > The output of ngd2vhdl will be a structual VHDL file and an SDF file
> > containing only logic delays.
> >
> >
> >
> >> Hi,
> >>
> >> we would like to simulate an FPGA design after logic synthesis (for
> >> Xilinx XC4036) but before doing any place and route. I.e. we want to
> >>
> >> simulate the delays of the logic, but not of the wires.
> >>
> >> Is there a way to do this (with design compiler and vss)?
> >>
> >> I understand that we can write a vhdl netlist from design compiler
> >> after
> >> synthesis. But this netlist is not simulatable, e.g. it contains
> >> iob_4000 components for which we do not have simulation models.
> >>
> >> Any help on this would be appreciated,
> >>
> >> Joe
> >>
> >
>
> If you want to go via the MAP route you will have to compile & use the
> Xilinx simulation primitive library ``simprims''. I don't know the state
> of the VHDL one but I've found a fair number of problems with the
> Verilog ones. At least in 2.1i the Verilog LUT models work but there are
> still errors & issues in some of the others.
>
> For the other alternative of going via an FPGA Express netlist might
> mean using the ``unisims'' library which, as far as I can see from my
> Verilog experiance, is much cruder than the simprims one.

The reason I suggested the Map route is because the original request was to
simulate the logic delays but not routing delays.  Most netlists produced
by synthesis tools do not have any delay information therefore only a unit
delay simulation would be possible.  By processing the design through map,
you will get true logic level delays but not routing delays.  Performing a
post-synthesis simulation is fine if you are interested in only a unit
delay simulation and will save you a few steps through our tools although
in general the netlist translation and map stage do not take too much CPU
time.

True you will have to use the SIMPRIM libraries with this approach rather
than the UNISIM libraries however I don't understand the problems you
mention.  I successfully use both types of simulation models all the time
for both VHDL and Verilog simulations.  The only major things that come to
mind that you may be referring to are in the 1.5 release of the LUT models
(for Verilog), you must drive all design inputs or sourced LUTs will go to
a simulation value of X.  All that was needed to be done is to tie undriven
design inputs to a known value.  With the 2.1 release, that requirement has
been lifted and you should only see X's on the outputs of undriven LUTs
when that input has a direct correlation to the result.  The only other
problems I generally see when a global reset is not performed on the design
before beginning simulation.  The methodology for global reset has been
changed for Verilog in the 2.1 release so that it will work better with
pre-compiled libraries which seems to be the trend of most Verilog
simulators today.  This methodology is explained in our documentation.
Without this global reset, it is possible the design might come up in a
unknown state.

I am not trying to say the Xilinx libraries are without fault however they
should work with most simulation/design scenarios.  There are always going
to be corner cases which can not be easily accounted for and as those are
encountered, we will try to fix them.

If you would like to go into more detail as to the problems you mention, I
would like to hear them.  Although I am not directly involved with the
simulation group, I can pass on any comments/experiences you or anyone else
might have about the simulation libraries.  I would like to change this
perception that they are error-prone.

Thanks,


--  Brian Philofsky
--  Xilinx Design Engineer



--
-------------------------------------------------------------------
 / 7\'7 Brian Philofsky   (brian.philofsky@xilinx.com)
 \ \ `  Xilinx Design Engineer                   hotline@xilinx.com
 / /    2100 Logic Drive                         1-800-255-7778
 \_\/.\ San Jose, California 95124-3450          1-408-879-5199
-------------------------------------------------------------------



--------------7FB0D021144509B516D3919E
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Rick Filipkiewicz wrote:
<blockquote TYPE=CITE>Brian Philofsky wrote:
<p>>
<br>>
<br>>
<br>> If you wish to simulate the design with logic level delays but not
<br>> wire delays, this is possible if you run the synthesized netlist
<br>> through the Xilinx M1 tools to the Map stage.&nbsp; Run the ncd file
that
<br>> Map outputs through ngdanno and then run the nga file from ngdanno
<br>> through ngd2vhdl.&nbsp; The command sequence will look like:
<br>>
<br>> ngdbuild &lt;design_netlist>
<br>> map -o logic_sim.ncd &lt;design>.ngd
<br>> ngdanno logic_sim.ncd
<br>> ngd2vhdl logic_sim.nga
<br>>
<br>>
<br>> The output of ngd2vhdl will be a structual VHDL file and an SDF file
<br>> containing only logic delays.
<br>>
<br>>
<br>>
<br>>> Hi,
<br>>>
<br>>> we would like to simulate an FPGA design after logic synthesis (for
<br>>> Xilinx XC4036) but before doing any place and route. I.e. we want
to
<br>>>
<br>>> simulate the delays of the logic, but not of the wires.
<br>>>
<br>>> Is there a way to do this (with design compiler and vss)?
<br>>>
<br>>> I understand that we can write a vhdl netlist from design compiler
<br>>> after
<br>>> synthesis. But this netlist is not simulatable, e.g. it contains
<br>>> iob_4000 components for which we do not have simulation models.
<br>>>
<br>>> Any help on this would be appreciated,
<br>>>
<br>>> Joe
<br>>>
<br>>
<p>If you want to go via the MAP route you will have to compile &amp; use
the
<br>Xilinx simulation primitive library ``simprims''. I don't know the
state
<br>of the VHDL one but I've found a fair number of problems with the
<br>Verilog ones. At least in 2.1i the Verilog LUT models work but there
are
<br>still errors &amp; issues in some of the others.
<p>For the other alternative of going via an FPGA Express netlist might
<br>mean using the ``unisims'' library which, as far as I can see from
my
<br>Verilog experiance, is much cruder than the simprims one.</blockquote>

<p>The reason I suggested the Map route is because the original request
was to simulate the logic delays but not routing delays.&nbsp; Most netlists
produced by synthesis tools do not have any delay information therefore
only a unit delay simulation would be possible.&nbsp; By processing the
design through map, you will get true logic level delays but not routing
delays.&nbsp; Performing a post-synthesis simulation is fine if you are
interested in only a unit delay simulation and will save you a few steps
through our tools although in general the netlist translation and map stage
do not take too much CPU time.
<p>True you will have to use the SIMPRIM libraries with this approach rather
than the UNISIM libraries however I don't understand the problems you mention.&nbsp;
I successfully use both types of simulation models all the time for both
VHDL and Verilog simulations.&nbsp; The only major things that come to
mind that you may be referring to are in the 1.5 release of the LUT models
(for Verilog), you must drive all design inputs or sourced LUTs will go
to a simulation value of X.&nbsp; All that was needed to be done is to
tie undriven design inputs to a known value.&nbsp; With the 2.1 release,
that requirement has been lifted and you should only see X's on the outputs
of undriven LUTs when that input has a direct correlation to the result.&nbsp;
The only other problems I generally see when a global reset is not performed
on the design before beginning simulation.&nbsp; The methodology for global
reset has been changed for Verilog in the 2.1 release so that it will work
better with pre-compiled libraries which seems to be the trend of most
Verilog simulators today.&nbsp; This methodology is explained in our documentation.&nbsp;
Without this global reset, it is possible the design might come up in a
unknown state.
<p>I am not trying to say the Xilinx libraries are without fault however
they should work with most simulation/design scenarios.&nbsp; There are
always going to be corner cases which can not be easily accounted for and
as those are encountered, we will try to fix them.
<p>If you would like to go into more detail as to the problems you mention,
I would like to hear them.&nbsp; Although I am not directly involved with
the simulation group, I can pass on any comments/experiences you or anyone
else might have about the simulation libraries.&nbsp; I would like to change
this perception that they are error-prone.
<p>Thanks,
<br>&nbsp;
<p>--&nbsp; Brian Philofsky
<br>--&nbsp; Xilinx Design Engineer
<br>&nbsp;
<br>&nbsp;
<pre>--&nbsp;
-------------------------------------------------------------------
&nbsp;/ 7\'7 Brian Philofsky&nbsp;&nbsp; (brian.philofsky@xilinx.com)
&nbsp;\ \ `&nbsp; Xilinx Design Engineer&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; hotline@xilinx.com
&nbsp;/ /&nbsp;&nbsp;&nbsp; 2100 Logic Drive&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1-800-255-7778&nbsp;
&nbsp;\_\/.\ San Jose, California 95124-3450&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1-408-879-5199&nbsp;
-------------------------------------------------------------------</pre>
&nbsp;</html>

--------------7FB0D021144509B516D3919E--

--------------DED6A3B2420B0CAB7336F407
Content-Type: text/x-vcard; charset=us-ascii;
 name="brianp.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brian Philofsky
Content-Disposition: attachment;
 filename="brianp.vcf"

begin:vcard 
n:Philofsky;Brian
tel;fax:(408) 879-4442
tel;work:1-800-255-7778
x-mozilla-html:TRUE
org:<BR><H1 ALIGN="CENTER"><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx" ALIGN="CENTER">  Design Center
version:2.1
email;internet:brianp@xilinx.com
title:<H3 ALIGN="CENTER"><img src="http://bennyhills.fortunecity.com/deadparrot/108/homer.gif" alt="Homer" align="center"> Design Engineer 
adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2510;San Jose;CA;95124-3450;USA
x-mozilla-cpt:;25776
fn:<H3 ALIGN="CENTER">Brian Philofsky
end:vcard

--------------DED6A3B2420B0CAB7336F407--

Article: 18720
Subject: Re: Sample Rate Conversion.
From: wavefront@SPAMbigfoot.com (martin griffith)
Date: Tue, 09 Nov 1999 20:53:00 GMT
Links: << >>  << T >>  << A >>
On Tue, 09 Nov 1999 10:21:32 -0600, Srikanth Gurrapu <gurrapu@ti.com>
scribbled:

>Hello all,
>
>I'm looking for a VHDL/verilog model for a sample rate converter,
>probably for FPGA implementations. For e.g., I want to design
>a module for upconverting 44.1kHz/22.05kHz/11.025kHz audio samples to
>48kHz.
>
>Could somebody help me in getting some pointers for this.
>Thanks in advance,
>
>--
>Regards,
>-Srikanth.
>Texas Instruments, Inc.
>gurrapu@ti.com
>972-480-2318
>
>
>
i suppose you could start with AD1892 data sheet



Martin







Article: 18721
Subject: Re: Sample Rate Conversion.
From: "Bill Groves" <bgroves@venturetechnologiesspammenot.com>
Date: 09 Nov 1999 13:11:23 PST
Links: << >>  << T >>  << A >>
Srikanth ,
Sounds big - big fifo etc... Once you have the 44.1K to 48K upconversion the
others are easy since they are covered by the least-common denominator for
the 2 larger numbers (divide by 2 or 4).

Try: http://www.analog.com/publications/whitepapers/products/AD1890.html
for theory of operation & background on polyphase filtering & related sample
conversion.

Gd. luck,
Bill

Bill Groves
Sachem Acoustics R&D

Srikanth Gurrapu <gurrapu@ti.com> wrote in message
news:38284A06.404A4C5A@ti.com...
> Hello all,
>
> I'm looking for a VHDL/verilog model for a sample rate converter,
> probably for FPGA implementations. For e.g., I want to design
> a module for upconverting 44.1kHz/22.05kHz/11.025kHz audio samples to
> 48kHz.
>
> Could somebody help me in getting some pointers for this.
> Thanks in advance,
>
> --
> Regards,
> -Srikanth.
> Texas Instruments, Inc.
> gurrapu@ti.com
> 972-480-2318
>
>
>


Article: 18722
Subject: test
From: Brian Boorman <XYZ.bboorman@harris.com>
Date: Tue, 09 Nov 1999 16:59:55 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------14E1AB51380722305725271D
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

test
--------------14E1AB51380722305725271D
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brian Boorman
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             Brian Boorman
n:              Boorman;Brian
org:            Harris RF Communications
adr:            1680 University Ave;;;Rochester;NY;14610;USA
email;internet: XYZ.bboorman@harris.com
title:          Electrical Design Engineer
tel;work:       (716) 242-3744
tel;fax:        (716) 242-3150
x-mozilla-cpt:  ;0
x-mozilla-html: FALSE
version:        2.1
end:            vcard


--------------14E1AB51380722305725271D--

Article: 18723
Subject: CAN tools reccomendations?
From: "Arnold Beland" <acbel@brookings.net>
Date: Tue, 9 Nov 1999 17:16:12 -0600
Links: << >>  << T >>  << A >>
I have decided to use the CAN bus for a variety of control projects.  I
would appreciate any suggestions.

Thanks in advance,

Arnold Beland


Article: 18724
Subject: where can I find fitter algorithms
From: anup kumar raghavan <anup@elec.uq.edu.au>
Date: Wed, 10 Nov 1999 10:42:35 +1000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------9983C74A8453C89DFACA2AC0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello, Can U please mention where I would be able to find what kind of
Fitter algorithms are being used to map the Netlists into the FPGA
architecture for Xilinx family..

I am interested in finding out how the fitter algorithm actually
transfers the netlist into the device..

If there are any relevant web pages regarding this, can you please let
me know.

Thanks and regards

Anup

--------------9983C74A8453C89DFACA2AC0
Content-Type: text/x-vcard; charset=us-ascii;
 name="anup.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for anup kumar raghavan
Content-Disposition: attachment;
 filename="anup.vcf"

begin:vcard 
n:Anup Kumar;Raghavan
tel;home:0061-7-38761962
tel;work:0061-7-33658849
x-mozilla-html:FALSE
url:www.csee.uq.edu.au
org:University of Queensland;Computer Science and Electrical Engineering
adr:;;;;;;Australia
version:2.1
email;internet:anup@elec.uq.edu.au
fn:Anup Kumar
end:vcard

--------------9983C74A8453C89DFACA2AC0--



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