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Messages from 13625

Article: 13625
Subject: multi-dimensional arrays and viewlogic
From: rk <stellare@NOSPAMerols.com>
Date: Mon, 14 Dec 1998 20:48:45 -0500
Links: << >>  << T >>  << A >>
hi,

suppose i write the following declaration in vhdl:

     signal MemoryFile : Array ( 5 DownTo 0 ) of Std_Logic_Vector ( 7
DownTo 0);

use it in the vhdl and compile it into an edif file using { synopsys,
exemplar, synplicity }.  now, with the viewlogic tools run edifneti to
make a wir file and then viewgen to make a schematic.  sounds good,
right?

if i go from the wir file to the .vsm file using viewvsm, it gets into
the simulator ok.  but if i open it up with viewdraw and try to save it
i get error messages.  if i try to run viewvsm after opening viewdraw
(w/out even having saved it), then viewvsm reports a fatal error and
croaks.

i tried this with 7.4 and 7.5 versions of viewlogic, 1998.02,
1998.02-02, and 1998.08 versions of synopsys.

so,

does anyone have a successful  experience with multi-dimensional arrays
going from edif -> viewdraw?  ideas?

thanks,

rk

p.s. for now i'm expanding all of my code to only use single-dimension
arrays but want to know how to deal with this problem.

Article: 13626
Subject: Re: Documention AHDL?
From: "gs" <guys@mediaone.net>
Date: Mon, 14 Dec 1998 22:41:00 -0600
Links: << >>  << T >>  << A >>
Somewhere (i can't remember) on the www.altera.com site is a place for PDF
versions of thier documentation for AHDL manual.  Use the site search engine
to help.  Also, Maxplus2 (development tools) has pretty good AHDL
on-line-help that is also context sensitive (open ahdl file in the text
editor, highlight keyword, and press SHIFT-F1 to bring you to the help).
GS


Vincenzo Liguori wrote in message <36740162.9916E43F@nospam.com>...
>> Hi,
>>
>> is there a good documentation about AHDL available on the net? I need to
>> understand written AHDL code. I searched with Altavista but  had no
>> success (only for "AHDL - Animal Health Database Library" or so).
>
>There's an excellent site that helps particularly with poorly
>documentedAHDL's features :
>
>http://193.215.128.3/freecore/
>
>It also has some free cores.
>
>> Thanks for any help,
>>
>> Lars
>
>As usual, my real email is in my web page.
>
>Enzo
>
>---------------------------------------------------------------------------
----
>
>Vincenzo Liguori
>Ocean Logic Pty Ltd
>PO BOX 768
>Manly NSW 2100
>Australia
>
>Ph : +61-2-99054152
>Fax : +61-2-99050921
>WWW : http://www.bigfoot.com/~oceanlogic
>
>
>
>
>


Article: 13627
Subject: Re: FAQ Address Please
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 14 Dec 1998 21:17:48 -0800
Links: << >>  << T >>  << A >>
While I don't know of a FAQ for comp.arch.fpga, we maintain the start of an
FAQ on programmable logic on The Programmable Logic Jump Station at
http://www.optimagic.com/faq.html .  In general, you will find links to
various topics including software, boards, books, consultants, etc. on our
site (www.optimagic.com).

You can find archives for various FPGA, VHDL, and Verilog newsgroups at
http://www.optimagic.com/newsgroups.html including a link to DejaNews.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Ing. Cristiano Golin wrote in message <36755925.8EE@witcom.com>...
>Please send me the FAQ repository address.
>Regards,
> C. Golin


Article: 13628
Subject: Re: Parallel Port Pass Through Specs?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 15 Dec 1998 01:23:21 -0500
Links: << >>  << T >>  << A >>
Arnold Beland wrote:
> 
> I am designing a device that will be driven  in EPP mode from the Printer
> Port of an existing PC.  These PC's will usually have a printer using this
> port.  I don't want my customers to have to install another parallel port. I
> notice that the Zip Drives have a pass-through capability.  Could anyone
> give me a clue as to how this is accomplished?  Thanks in advance.
> 
> Arnold Beland

The printer uses the Strobe to indicate the presence of valid data on
the 8 data lines. If you don't toggle Strobe, the printer does not care
what you do with the 8 data lines. So you can use those 8 lines to
control your device. I don't remember the other signals that are output
from the parallel port, but you must use one to disable your device when
data is being sent to the printer. 

The only devices I have examined are parallel port keys. They don't need
to be disabled when the printer is working, they only need to be
transparent. So I don't know how a Zip drive, for example, keeps from
getting bogus data when the printer is being used. 

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13629
Subject: [Altera]Unrecognized Devices..
From: ktoh@hdtv.snu.ac.kr (Kyutaeg Oh)
Date: 15 Dec 1998 10:31:39 GMT
Links: << >>  << T >>  << A >>
I would like to program max7000s series(exactly, EPM7064STC100-5),
using bit-blaster or byte-blaster. but fail to download .pof file.
The error message is "Unrecognized Devices or Socket Empty",
but I checked all the power line and also device connection.
MAX+plus II version is 9.01(compiler), 9.1(programmer).

Are ther anyone who can show me the right way ?
Thanks.

Kyutaeg.

Article: 13630
Subject: Neural nets
From: wpauwels <wpauwels@info.vub.ac.be>
Date: Tue, 15 Dec 1998 12:32:34 +0100
Links: << >>  << T >>  << A >>
Can anyone help me to implement a neuron (neural network) on a FPGA.
Please mail me some examples.
Thank you,
 wpauwels@info.vub.ac.be


Article: 13631
Subject: Re: multi-dimensional arrays and viewlogic
From: Alain <alain_raynaud@mentorg.com>
Date: Tue, 15 Dec 1998 12:50:46 +0100
Links: << >>  << T >>  << A >>
rk wrote:
> 
> p.s. for now i'm expanding all of my code to only use single-dimension
> arrays but want to know how to deal with this problem.

You have an option in Synopsys Design Compiler so that you can convert
multi-dimensional nets to single-dimension if you want to.

So there is no need to change your code.

Alain.
-- 
-----------------------------------------------------------------------
 Alain RAYNAUD                                            META SYSTEMS 
 R&D Logic Design Team                                          LP 853
                                   3 Avenue du Canada - Batiment Sigma
 Tel: (33) 01 64 86 61 69             91975 Courtaboeuf Cedex - FRANCE
 E-Mail: Alain_Raynaud@mentor.com             Fax: (33) 01 64 86 61 61
-----------------------------------------------------------------------

Article: 13632
Subject: Re: multi-dimensional arrays and viewlogic
From: rich katz <rich.katz@gsfc.nasa.gov>
Date: Tue, 15 Dec 1998 07:18:21 -0500
Links: << >>  << T >>  << A >>
Alain wrote:

> rk wrote:
> >
> > p.s. for now i'm expanding all of my code to only use single-dimension
> > arrays but want to know how to deal with this problem.
>
> You have an option in Synopsys Design Compiler so that you can convert
> multi-dimensional nets to single-dimension if you want to.
>
> So there is no need to change your code.
>
> Alain.

hi alain, do you know the synopsys command to do this?

anyways, i fear i will have to keep my vhdl code single dimensional as i
need to have my vhdl code work with synplicity and exemplar too - do they
have options for that, too?  actmap, the actel synthesizer (one of the
devices we target) doesn't accept 2-d arrays at all.  or perhaps we should
dump viewlogic.  do other cae environments have problems with this? any
ideas?

thanks,

rk

Article: 13633
Subject: Re: FAQ Address Please
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Tue, 15 Dec 1998 09:23:15 -0500
Links: << >>  << T >>  << A >>
Comp.arch.fpga FAQ

Q: Is there a FAQ for comp.arch.fpga?
A: This is it.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13634
Subject: Re: Parallel Port Pass Through Specs?
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Tue, 15 Dec 1998 09:39:57 -0500
Links: << >>  << T >>  << A >>


Rickman wrote:

> Arnold Beland wrote:
> >
> > I am designing a device that will be driven  in EPP mode from the Printer
> > Port of an existing PC.  These PC's will usually have a printer using this
> > port.  I don't want my customers to have to install another parallel port. I
> > notice that the Zip Drives have a pass-through capability.  Could anyone
> > give me a clue as to how this is accomplished?  Thanks in advance.
> >
> > Arnold Beland
>
> The printer uses the Strobe to indicate the presence of valid data on
> the 8 data lines. If you don't toggle Strobe, the printer does not care
> what you do with the 8 data lines. So you can use those 8 lines to
> control your device. I don't remember the other signals that are output
> from the parallel port, but you must use one to disable your device when
> data is being sent to the printer.
>
> The only devices I have examined are parallel port keys. They don't need
> to be disabled when the printer is working, they only need to be
> transparent. So I don't know how a Zip drive, for example, keeps from
> getting bogus data when the printer is being used.
>

You can also wake up the device when it sees a specific sequence on the control
and/or data lines. For more sophisticated devices, you may want to use teh decoded
sequence to shut off the pass The pass through while the device is active (ie
until it sees a control/data sequence that shuts it back off)The other (control)
signals are:
Outputs to printer:
    SelectIn, Autofeed,Strobe, INIT

Article: 13635
Subject: Re: Parallel Port Pass Through Specs?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 15 Dec 1998 09:52:34 -0500
Links: << >>  << T >>  << A >>
I thought about this a little more and realized that there must also be
a software component that snoops the printer functions to make sure that
the "extra" device is not being accessed when the printer is being
accessed. If you tried to talk to your device at the same time another
program was printing, you would get unpredictable reasults.



Arnold Beland wrote:
> 
> I am designing a device that will be driven  in EPP mode from the Printer
> Port of an existing PC.  These PC's will usually have a printer using this
> port.  I don't want my customers to have to install another parallel port. I
> notice that the Zip Drives have a pass-through capability.  Could anyone
> give me a clue as to how this is accomplished?  Thanks in advance.
> 
> Arnold Beland

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13636
Subject: Re: [Altera]Unrecognized Devices..
From: "Matthew Morris" <mmorris@no_spam.carrieraccess.com>
Date: Tue, 15 Dec 1998 08:12:47 -0700
Links: << >>  << T >>  << A >>
Probably you are targeting the wrong programmer..

With the programmer window as the active pane, select the options menu - >
Hardware Setup..
choose byteblaster or bit-blaster depending on whether it is hanging on the
parallel or serial port respectively..

Matt

Kyutaeg Oh wrote in message <755dqb$aod$1@news.kren.nm.kr>...
>I would like to program max7000s series(exactly, EPM7064STC100-5),
>using bit-blaster or byte-blaster. but fail to download .pof file.
>The error message is "Unrecognized Devices or Socket Empty",
>but I checked all the power line and also device connection.
>MAX+plus II version is 9.01(compiler), 9.1(programmer).
>
>Are ther anyone who can show me the right way ?
>Thanks.
>
>Kyutaeg.


Article: 13637
Subject: Re: Dedicated pin in ALTERA 10K familly
From: "Matthew Morris" <mmorris@no_spam.carrieraccess.com>
Date: Tue, 15 Dec 1998 08:17:06 -0700
Links: << >>  << T >>  << A >>
Search through the application notes on configuration of 10K devices, that
will detail
use of nce & nceo (depends on your configuration topology) , tdi & tdo etc
are jtag ports..
you should wire high with pull-ups all inputs except for trst which should
be tied pulled low..

You might want to concider building in a scan ring for test purposes..

Matt




Hubert Gagnon wrote in message <75414h$l98$1@news.quebectel.com>...
>What should I do with all dedicated pins in a 10k20 device? I'm talking
>about nce, nceo, tdi, tdo etc. There is no documentation regarding those
>pins on the data book. I use the bit blaster to program the part.
>
>Thanks
>Hubert Gagnon
>
>


Article: 13638
Subject: Re: Parallel Port Pass Through Specs?
From: John Chambers <johnc@ihr.mrc.ac.uk>
Date: Tue, 15 Dec 1998 15:31:45 +0000
Links: << >>  << T >>  << A >>
Have a look at http://www.lvr.com/parport.html.  There is a link there
to a microsoft document describing chaining.  I'm working on a parallel
port device working in EPP mode too and this page has been very useful (
I even bought the book).

John

johnc@ihr.mrc.ac.uk

Article: 13639
Subject: Re: XESS FPGA Board?
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Tue, 15 Dec 1998 16:50:59 +0000
Links: << >>  << T >>  << A >>
Shane Tow wrote:
> 
> I am considering purchasing an XESS XS40 FPGA board.  ...

We've just run a design lab exercise using these boards for our
second-year students.  Very successful.  We made no use (this time) of
the on-board 8031 - just the FPGA, display and the various xsload,
xsport commands.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions

Article: 13640
Subject: Re: Parallel Port Pass Through Specs?
From: z80@ds2.com (Peter)
Date: Tue, 15 Dec 1998 18:43:51 GMT
Links: << >>  << T >>  << A >>

Which is one of the reasons why a lot of "pass-through" simply doesn't
work reliably.

We have all had problems for years with "pass through" dongles, and
today almost every parallel port device (scanners, mass storage
devices, etc) have "pass through" so a printer can be driven through
it, but often it is unreliable. 

I have spent enough time messing with such products, most recently
with an HP scanner driving an Epson inkjet printer. The HP readme file
contains a long list of app software and peripherals which won't work,
or won't work properly.

Yes, extra software is needed to manage the port contention, and it is
usually quite dirty in the way it hooks into the O/S, so you can get
lots of very complex and subtle conflicts with other software.

Years ago, I implemented a parallel port device which had "pass
through". It wasn't a dongle, but it might have been for this
explanation. I basically implemented a UART using some of the printer
control signals (using INIT as an output, IIRC) to talk to *my*
device, and my device then filtered out the muck before passing those
signals on to the printer. It was slow but it was 100% reliable and
compatible - with any "normal" printer.

>I thought about this a little more and realized that there must also be
>a software component that snoops the printer functions to make sure that
>the "extra" device is not being accessed when the printer is being
>accessed. If you tried to talk to your device at the same time another
>program was printing, you would get unpredictable reasults.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13641
Subject: Re: Dedicated pin in ALTERA 10K familly
From: Steve@XXX_REMOVE_XXXrsn-tech.demon.co.uk (Steve Rencontre)
Date: Tue, 15 Dec 1998 18:48:59 GMT
Links: << >>  << T >>  << A >>
On Mon, 14 Dec 1998 16:50:07 -0500, "Hubert Gagnon"
<hgagnon@absolu.com> wrote:

>What should I do with all dedicated pins in a 10k20 device? I'm talking
>about nce, nceo, tdi, tdo etc. There is no documentation regarding those
>pins on the data book.

Yes there is.

--
Steve Rencontre, Design Consultant
http://www.rsn-tech.demon.co.uk/  --  remember to despam return address

Article: 13642
Subject: Samples of Xilinx Virtex XVC300+?
From: Andrew Plumb <tekmage@io.com>
Date: Tue, 15 Dec 1998 14:28:24 -0500
Links: << >>  << T >>  << A >>
Anyone know where I can get 5 or 6 of Xilinx' newer Virtex XVC300 (or
'400, '600, '800, or '1000) chips?  Even one or two will do.

Any help is GREATLY appreciated! (no one seems to have any...)

Andrew, VE3SLG
E-mail: tekmage@io.com


Article: 13643
Subject: Re: Parallel Port Pass Through Specs?
From: "Arnold Beland" <acbel@worldnet.att.net>
Date: 15 Dec 1998 19:29:40 GMT
Links: << >>  << T >>  << A >>
Thanks for the help, everyone.  I just now ordered the book from amazon.

Best Regards,

Arnold



Article: 13644
Subject: Fast *Industrial* 22V10?
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Wed, 16 Dec 1998 14:15:12 +0000
Links: << >>  << T >>  << A >>
Does anyone know of a manufacturer of a 22V10 with guaranteed
combinational propagation delay 5ns or better for the full INDUSTRIAL
temperature range?

All the devices I've looked at so far are limited to COMMERCIAL
temperature range.  The fastest industrial grade devices appear to be
7.5ns (several sources).

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions

Article: 13645
Subject: XCV300 Samples? (not Re: Samples of Xilinx Virtex XVC300+?)
From: Andrew Plumb <tekmage@io.com>
Date: Wed, 16 Dec 1998 09:49:51 -0500
Links: << >>  << T >>  << A >>
Oops.  Just noticed the part number...  It's XCV300, not XVC300.

Still looking.  Anyone?

Thanks!

Andrew, VE3SLG
E-mail: tekmage@io.com

--

Andrew Plumb wrote:

> Anyone know where I can get 5 or 6 of Xilinx' newer Virtex XVC300 (or
> '400, '600, '800, or '1000) chips?  Even one or two will do.
>
> Any help is GREATLY appreciated! (no one seems to have any...)
>
> Andrew, VE3SLG
> E-mail: tekmage@io.com

Article: 13646
Subject: Re: Dedicated pin in ALTERA 10K familly
From: timo@novaengr.com (Tim O)
Date: Wed, 16 Dec 1998 15:15:24 GMT
Links: << >>  << T >>  << A >>
On Mon, 14 Dec 1998 16:50:07 -0500, "Hubert Gagnon"
<hgagnon@absolu.com> wrote:

If you're using Max+Plus II you can look in the report (.rpt) file and
look at the big ascii picture of the chip.  It will make
recommendations for unused pins.

	Tim.

>What should I do with all dedicated pins in a 10k20 device? I'm talking
>about nce, nceo, tdi, tdo etc. There is no documentation regarding those
>pins on the data book. I use the bit blaster to program the part.
>
>Thanks
>Hubert Gagnon
>
>

Article: 13647
Subject: Problem with timing spec through a RAM
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 16 Dec 1998 10:31:17 -0500
Links: << >>  << T >>  << A >>
I am building a FIFO with multiple banks of RAM and I am not getting
timing errors even though I find very long net delays when I check by
hand. 

My circuit looks like this.

      +----+       +-----+      +-------+       +-----+
      |Read| >40ns | FIFO|      |  CLB  |       | IOB |
      |Addr|------>| RAM |----->| Logic |------>| FF  |
   +->|>   |       |     |      |       |    +->|>    |
   |  +----+       +-----+      +-------+    |  +-----+
   |                                         |
   |    30 nS Period Constraint              |
---+-----------------------------------------+

There are 96 CLBs used for the RAM, so I expect that there will be long
slow nets on the read (and write) address. I will be working on this.
But I don't understand why the period constraint didn't flag this as an
error. I remember this was a problem back when Xilinx first came out
with RAM, but I thought they fixed the problem a long time ago. Any
ideas? 

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13648
Subject: Re: Problem with timing spec through a RAM
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 16 Dec 1998 11:06:04 -0500
Links: << >>  << T >>  << A >>
I forgot to mention a few useful details. First, I am using the Xilinx
Foundation toolset, version 1.4. The target part is an XC4013XL. My
constraints are in a UCF file. 

Thanks in advance!


Rickman wrote:
> 
> I am building a FIFO with multiple banks of RAM and I am not getting
> timing errors even though I find very long net delays when I check by
> hand.
> 
> My circuit looks like this.
> 
>       +----+       +-----+      +-------+       +-----+
>       |Read| >40ns | FIFO|      |  CLB  |       | IOB |
>       |Addr|------>| RAM |----->| Logic |------>| FF  |
>    +->|>   |       |     |      |       |    +->|>    |
>    |  +----+       +-----+      +-------+    |  +-----+
>    |                                         |
>    |    30 nS Period Constraint              |
> ---+-----------------------------------------+
> 
> There are 96 CLBs used for the RAM, so I expect that there will be long
> slow nets on the read (and write) address. I will be working on this.
> But I don't understand why the period constraint didn't flag this as an
> error. I remember this was a problem back when Xilinx first came out
> with RAM, but I thought they fixed the problem a long time ago. Any
> ideas?
> 
> --
> 
> Rick Collins
> 
> redsp@XYusa.net
> 
> remove the XY to email me.

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Article: 13649
Subject: Re: Fast *Industrial* 22V10?
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Wed, 16 Dec 1998 11:15:07 -0500
Links: << >>  << T >>  << A >>
You don't say what Vcc input, 3.3V or 5V, so I assume 5V. I know that
Lattice had some GAL16LV8D devices that I believe had 5 ns timing. (Sorry
I don't have data sheet handy to verify this). Have you looked at them?
They may have some 22V10 compatible GAL devices in that speed range.

Tim Forcer wrote:

> Does anyone know of a manufacturer of a 22V10 with guaranteed
> combinational propagation delay 5ns or better for the full INDUSTRIAL
> temperature range?
>
> All the devices I've looked at so far are limited to COMMERCIAL
> temperature range.  The fastest industrial grade devices appear to be
> 7.5ns (several sources).
>
> --
> Tim Forcer               tmf@ecs.soton.ac.uk
> Department of Electronics & Computer Science
> The University of Southampton, UK
>
> The University is not responsible for my opinions



--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>




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