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Messages from 20550

Article: 20550
Subject: Re: Problem in Wildforce synthesis.
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 14 Feb 2000 12:00:38 -0700
Links: << >>  << T >>  << A >>
>Sir,
>    I did not simulate it. But it is a blank architecture that I am trying
>to synthesise.
>Please tell me if I can send the actual .vhd files I am using the .vhd
files
>given by wildforce to do my synthesis. I want to get the environment right
>before I start synthesizing for my research.
>For now I am attaching the pe1lca.vhd file. This is the logic core that is
>the only part that we write. Aso I am sending you the pe1ifa.vhd, file that
>is the interface file in which the errors are comming.

Problem #1 is that I can't find any definition of "synthesis" anywhere.  In
addition, I don't think your

    if (synthesis = '1') generate

will do what you want.  You should probably use the synopsys
synthesis_off/synthesis_on pragmas.

You may also want to read the tool documentation in more detail.

I strongly urge to to SIMULUATE YOUR CODE before synthesizing.  Trust me,
you'll find debugging a whole lot easier.

-a

>Shrinath Kutty
>
>Andy Peters wrote:
>
>> TS Kutty wrote in message <38A51625.A87709CD@ececs.uc.edu>...
>> >Hi,
>> >    I am a student of the University Of Cincinnati. This query is about
>> >a problem in using the synthesis tools for the WILDFORCE board. This
>> >board is made up of 4 FPGA's.
>> >    I get  these errors in wildforce synthesis. I am using synopsys
>> >tools for synthesis and M1 tools for routing and placement in to a
>> >4036xl fpga.
>>
>> [snip errors]
>>
>> sounds like your code isn't any good.  did you do a simulation of your
>> source code before attempting to synthesize it?
>>
>> -- a
>> -----------------------------------------
>> Andy Peters
>> Sr Electrical Engineer
>> National Optical Astronomy Observatories
>> 950 N Cherry Ave
>> Tucson, AZ 85719
>> apeters (at) noao \dot\ edu
>>
>> "Money is property; it is not speech."
>>             -- Justice John Paul Stevens
>
>--
>-----------------------------------------------------
>Click here for Free Video!!
>http://www.gohip.com/freevideo/
>
>


Article: 20551
Subject: Re: Xilinx Virtex Reset
From: mark.luscombe@lineone.net (Mark Luscombe)
Date: Mon, 14 Feb 2000 20:46:43 GMT
Links: << >>  << T >>  << A >>
Ray,

Thanks for your input, but if the GSR net is used, then routing and
CLB resources are not used, as it is a "free" function.

The Xilinx Rep is coming to see me Monday, so hopefully he'll be able
to say whether i can use the GSR net at 74MHz.

Cheers, Mark.

On Sun, 13 Feb 2000 17:27:01 GMT, Ray Andraka <randraka@ids.net>
wrote:

>Not every flip flop in an FPGA design needs to be reset;  You only need to
>reset select flip-flops to make sure that 'loops' in the logic reach a known
>state after some number of clock cycles.  Data path will self clear, so
>there's no need to apply explicit resets.  You may also want to reset the
>flip-flops closest to the outputs, and hold them reset for a number of
>clocks after reset is released.
>
>I know that this makes the ASIC guys blood curdle, but the fact of the
>matter is that it uses up resources in the FPGA and slows down your design.
>
>Rickman wrote:
>
>> Mark Luscombe wrote:
>> >
>> > Hi,
>> >
>> > I am trying to work out a satifactory method for resetting a
>> > synchronously design Virtex running at 74MHz.
>> >
>> > Now, the reset signal needs to be synchronised with the 74MHz clock
>> > and the propagation delay from this to the CLB and IOB DFFs needs to
>> > be less than 13ns to ensure that all registers within the device at
>> > reset on the sam clock edge.
>> >
>> > Xilinx seem to have been telling people not to use the GSR net, as it
>> > is too slow, but it does seem a pity not to use it, and use extra
>> > routing and CLB inputs for a global reset.
>> >
>> > It seems as though the STARTUP_VIRTEX component can accept a USER_CLK
>> > input, i.e. the 74MHz, so is this a good solution ?
>> > Also, this component has a GSR input for an external reset signal,
>> > does anybody know if this is also synchronised with the USER_CLK input
>> > ?
>> > The device is configured in 8-bit parallel with CCLK which is related
>> > to the 74MHz.
>> >
>> > What have other designers done in this situation.
>> >
>> > Cheers, Mark.
>>
>> This is a subject that is often discussed here. What you describe with
>> using a user clock for startup is one way to do it. That should work if
>> the GSR net is fast enough to operate within your clock cycle.
>>
>> Another way to use the GSR which does not depend on sychronized release
>> of the GSR is to make sure that all of the inputs to your various FSMs
>> or other sychronous logic are in a state that will not cause the
>> machines to make a state change. For example if the FSMs reset to an
>> IDLE state, then make sure that none of the inputs that let the machine
>> leave the IDLE state are asserted. Then even if the GSR is released on
>> different clock cycles for different FFs, it will not matter.
>>
>> Or use a couple of delay FFs to generate (from the GSR) a separate,
>> synchronized input to the FSMs which will delay state changes from this
>> initial state until it releases. This net will not need to go to all of
>> the FFs in your design and can be routed much faster.
>>
>> Another method which is similar to this last one is to have a separate,
>> external reset signal which is controlled by a micro or other logic.
>> This will only be released well after the config is complete and is
>> synchrnized to the clock. As in the last method, this reset will not
>> need to go to every FF in the FPGA and so can be routed more quickly.
>>
>> The GSR is nice in that it puts every FF into a known state and it is
>> asynch so it does it NOW! But releasing it can be a problem. A second,
>> more limited reset is a good way to get the FPGA started on the right
>> foot.
>>
>> I can't remember other ways that have been described, but I am sure
>> there are some.
>>
>> --
>>
>> Rick Collins
>>
>> rick.collins@XYarius.com
>>
>> remove the XY to email me.
>>
>> Arius - A Signal Processing Solutions Company
>> Specializing in DSP and FPGA design
>>
>> Arius
>> 4 King Ave
>> Frederick, MD 21701-3110
>> 301-682-7772 Voice
>> 301-682-7666 FAX
>>
>> Internet URL http://www.arius.com
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>

Article: 20552
Subject: FPGA Network stack
From: Joshua Lamorie <jpl@xiphos.ca>
Date: Mon, 14 Feb 2000 16:16:23 -0500
Links: << >>  << T >>  << A >>
Gidday there,

    Has anyone had any experience with making a network stack
(MAC+IP+TCP etc.) in an FPGA?  Any cores available? Links?

    Thanks

Joshua Lamorie
Systems Designer
Xiphos Technologies Inc.

Article: 20553
Subject: Post-synthesis simulation in Foundation Express
From: Paul Urbanus <urb@ti.com>
Date: Mon, 14 Feb 2000 15:57:33 -0600
Links: << >>  << T >>  << A >>
Hi all,

My problem: I'd like to simulate my design after it has been synthesized in
Foundation Express 2.1i. And I'd like to simulate it using ModelSim and the 
testbench, just as I did before it was synthesized.

In order to simulate my post-synthesis design, I need for Foundation Express to
write a post-synthesis structural VHDL file which is equivalent to the
gate-level XNF or EDIF file which was produced. I've looked in every directory
tree I can think of that makes sense, and there's no sign of any post-synth
VHDL file.

I've looked at the Synthesis Options menu, and can find no option to output a
structural, gate-level equivalent, VHDL file. On the other hand, this option is
clearly available in one of the Implemenation submenus, allowing one to run a
post-place-and-route simulation.

In trying to find the solution to my problem and doing lot's of searching of
the Xilinx data base from their web page, I found one reference to
http://toolbox.xilinx.com/docsan/2_1i/data/common/sim/sim5_2.htm  I have
snipped the following from that URL


     <begin snipped documentation, with my caps for emphasis>

Post-synthesis simulation is synthesis vendor-dependent, and the synthesis tool
must write VHDL or Verilog netlists in terms of UniSim library components.
CHECK WITH YOUR SYNTHESIS VENDOR FOR THIS FEATURE. The library usage guidelines
for RTL simulation also apply to post-synthesis pre-NGDBuild gate-level
functional simulation. LogiBLOX models remain as behavioral blocks and can be
simulated in the same design as structural UniSim components. You may have to
insert library statements into the HDL code.

     <end snipped documentation>


I'm trying to do something which should be relatively painless and easy. Yes, I
know that I can simulate my design using the builtin Aldec gate-level
simulator. I already have a complete test bench written VHDL - I'd just like to
be able to run it again.

Surely there is a design flow to support this for the Xilinx-bundled version of
FPGA Express, and presumably Xilinx is my synthesis vendor.

I'm hoping there is something simple I have missed and one of you will kindly
point it out to me.

Paul Urbanus
************************************************************************
*   Never wrestle with a pig - you get dirty and the pig likes it!    *
************************************************************************
Article: 20554
Subject: Altera: how to convert .tdf to .gdf?
From: Yuyuan Lu <luyy@yahoo.com>
Date: Mon, 14 Feb 2000 22:02:44 GMT
Links: << >>  << T >>  << A >>
Hi, experts,

I am reading a Altera Max+Plus II .tdf file writen by someone else.
It is a huge file and hard for me to follow the logic equations. I am
wondering
if there is any way to convert .tdf file to .gdf file (a schematic).

Thanks in advance.

Yuyuan

Article: 20555
Subject: FPGA Express/XC4KXLA annoyance
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 14 Feb 2000 15:24:35 -0700
Links: << >>  << T >>  << A >>
OK, so I have this all-VHDL design that fits into 83% of an XC4013XLA.  My
clock is 80 MHz.  The chip has an SDRAM interface (I have an external PLL
clock buffer that generates the FPGA clock and the SDRAM clock).  I set an
offset constraint on the SDRAM data, address and control lines to ensure
that I meet the SDRAM setup requirements.

Since the SDRAM data bus is bidirectional, I have an output enable for the
data bus.  This output enable is generated by a state machine and is
registered.  The SDRAM data bus outputs are registered in the IOBs, too.

After place and route, trce tells me that some of my SDRAM data bus outputs
aren't meeting the timing constraints.  A bit of poking around in FPGA
Editor tells me that, for some reason, the output enable signal doesn't go
directly to the IOBs; rather, it gets "looped back" into the CLB where its
register is, gets run through an LUT, and that LUT's output gets distributed
to the IOBs where it drives the tristate enable.

Turns out that the LUT simply inverts the output enable signal.
Unfortunately, the delay through the LUT is enough to cause me to fail
timing (otherwise, I would never have noticed this!).  Sooooo...what's
causing this?

Back to FPGA Express.  I open the optimized design's schematic and find the
reason:  it turns out that FPGA Express runs my output enable through an
inverter!  My code generates the output enable as active high, which is
reasonable because while the tristate enable in the IOB is active low,
there's a mux in the IOB that selects active low or active high tristate
enable.  (This mux is present on all of the XC4K parts, at least back to the
'E'!)  FPGA Express, however, doesn't know about this mux, and uses an LUT
to invert the output enable!

The "fix" is obvious - I just went back into my state machine and made that
output enable signal active low.  Now, the registered (in the CLB; using the
registered tristate in the IOB is a PITA) output enable drives the tristate
enables in the IOBs properly, and I meet timing, too.

Note to synopsys: fix this bug, please. Now.  OK, so maybe it's not a bug.
But it would be nice if the tools supported the architectural features!  I
can't believe this hasn't been 'discovered' before.

Note to Xilinx: howzabout getting that registered tristate enable in the
IOBs to work without having to use a silly black-box-Perl-script-driven
HACK?  Those flops have been around since you introduced the "X" series
parts.  How long ago was that?

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens


Article: 20556
Subject: Re: MULTIRATE DESIGN
From: erika_uk@my-deja.com
Date: Mon, 14 Feb 2000 22:27:54 GMT
Links: << >>  << T >>  << A >>
HI ,

I THINK YOU SHOULD USE THE FLOORPLANNER ....


In article <889393$i6q$1@nnrp1.deja.com>,
  ritchie99_uk@my-deja.com wrote:
> Hi all,
>
> VIRTEX-E target.
>
> My design produces 12 parrallel outputs at once
> 4 are in the left edge, 4 are in the middle and 4 are in the right at
> decreasing rate.
>
> I have to use only one off-chip bank ram, hoping to succeed to design
> the required address generator....
>
> i am just wondering what's the appropriate way to route the different
> outputs, i mean more precisely how many delays i have to apply to the
> left, middle , and the right outputs which will feed my address-
> generator
>
> i am applying timing constraint only, (no placement constraint)
> do you think that i have to use the floorplanner, for example, and so
> orient by my-self the placement
>
> any help will be much appreciated
>
> regards
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20557
Subject: Re: Post-synthesis simulation in Foundation Express
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 14 Feb 2000 15:31:40 -0700
Links: << >>  << T >>  << A >>
Paul Urbanus wrote in message <38A87A4D.193189BB@ti.com>...
>Hi all,
>
>My problem: I'd like to simulate my design after it has been synthesized in
>Foundation Express 2.1i. And I'd like to simulate it using ModelSim and the
>testbench, just as I did before it was synthesized.
>
>In order to simulate my post-synthesis design, I need for Foundation
Express to
>write a post-synthesis structural VHDL file which is equivalent to the
>gate-level XNF or EDIF file which was produced. I've looked in every
directory
>tree I can think of that makes sense, and there's no sign of any post-synth
>VHDL file.

In the standalone FPGA Express (not run from the Project Manager), one of
the options you get when you export the netlist is Simulation Output format.
It will generate a file, in the same directory that it puts the .XNF(s),
with a name along the lines of "designname_sim0.vhd".

hope this helps,


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 20558
Subject: Advice please
From: sweazle@my-deja.com
Date: Mon, 14 Feb 2000 22:37:38 GMT
Links: << >>  << T >>  << A >>
I'm going to a new job where I will be doing FPGA's and will have to
acquire the software and programmer for them. There will be a budget
constraint so price will be an issue. I'm looking for advice on the
"best" set of tools for this and price. What I'll be looking for is:

1. Schematic capture
2. Verilog (or could learn VHDL) simulation
3. Floor-planning would be nice
4. Synthesis (at least ability to add later)
5. Place and route with back annotation into the simulator
6. An FPGA programmer

As the projects will be varied, I believe I will be using different
companies FPGA's so having a set of tools that could use different
libraries and a programmer that can program those parts is required.

I have 15 years experience designing digital I.C.'s using Cadence so a
set of tools like Composer/NCVerilog/BuildGates would be nice, but is
far too expensive for this place.

Expected size of devices will be 2K - 50K gates (in IC terms, not sure
how that relates to FPGA's) plus 0 - 40Kbits memory (internal would be
good but could be external).

Any advice is welcome.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20559
Subject: Re: Post-synthesis simulation in Foundation Express
From: a@z.com
Date: Mon, 14 Feb 2000 17:45:57 -0500
Links: << >>  << T >>  << A >>
Hi Paul,

When you place and route your FPGA with M2.1 select from the main menu
Design->Options->Simulation and ModelSimVHDL from the simulation format list. This
will generate a VHDL and SDF file that can be used for timing simulation with
ModelSim (you will aslo have to compile the libraries found in
$XILINX\vhdl\src\simprims).

Regards,

Catalin

Paul Urbanus wrote:

> Hi all,
>
> My problem: I'd like to simulate my design after it has been synthesized in
> Foundation Express 2.1i. And I'd like to simulate it using ModelSim and the
> testbench, just as I did before it was synthesized.
>
> In order to simulate my post-synthesis design, I need for Foundation Express to
> write a post-synthesis structural VHDL file which is equivalent to the
> gate-level XNF or EDIF file which was produced. I've looked in every directory
> tree I can think of that makes sense, and there's no sign of any post-synth
> VHDL file.
>
> .......

Article: 20560
Subject: Re: Public Domain Micro Processor Project
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Mon, 14 Feb 2000 22:59:54 +0000
Links: << >>  << T >>  << A >>
Don Golding wrote:
> 
> --                       Public domain Forth Processor design

A shift register type of stack may be faster than a register style stack
if the final
programmable logic device does not provide fast ram as your data path to
and from the alu
is shorter. It may make some other operations simpler like rot and swap.
As for the real
speed of the processor it still is how fast your main memory is for
opcode fetching.
A good resource page for forth,
http://www.cs.cmu.edu/~koopman/stack.html
Good luck on your project.

-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
The Lagging edge of technology:
http://www.jetnet.ab.ca/users/bfranchuk/woodelf/index.html
Article: 20561
Subject: Re: Post-synthesis simulation in Foundation Express
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 14 Feb 2000 16:24:00 -0700
Links: << >>  << T >>  << A >>
a@z.com wrote in message <38A885A5.5AF09382@z.com>...
>Hi Paul,
>
>When you place and route your FPGA with M2.1 select from the main menu
>Design->Options->Simulation and ModelSimVHDL from the simulation format
list. This
>will generate a VHDL and SDF file that can be used for timing simulation
with
>ModelSim (you will aslo have to compile the libraries found in
>$XILINX\vhdl\src\simprims).


that's post-ROUTE.  the poster asked about post-SYNTHESIS.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 20562
Subject: Is EDIF format adopted by all FPGA manufacturers???
From: "J.R." <j_robby@hotmail.com>
Date: Mon, 14 Feb 2000 23:39:38 -0000
Links: << >>  << T >>  << A >>
Hello,

I know that Xilinx and Altera tools generates netlists in EDIF format (from
HDL or schematics). Do all other FPGA manufacturers tools (i.e Atmel,
Lucent, etc.) do that?.


Cheers.


Article: 20563
Subject: Re: Advice please
From: "Gary Spivey" <spivey@rincon.com>
Date: Mon, 14 Feb 2000 16:51:16 -0700
Links: << >>  << T >>  << A >>
I just did a similar thing (though thankfully not with the same budget
constraints). It appears that you, like me, have been desiging ASIC's in
Verilog, but now find yourself faced with FPGA's in (God Forbid) at least
some VHDL. For this, most people seem to recommend the ModelTech simulator -
it is the market leader for VHDL (and 3rd for Verilog - though I imagine a
distant third). If you get the Language neutral license, you can run either
VHDL or Verilog. If you get two of them, you can run both at the same time
(which is what I am doing - I have a board with VHDL models and I use
Verilog for my own code). Problem is, this will run about 50K as I recall
(this was for a floating UNIX license - you can get a lot cheaper with
node-locked PC). I am not certain if NC-Verilog and NC-whatever the VHDL
compiler is can run concurrently. That would be worth looking into, but
likely more expensive than the ModelTech - of course, after what Cadence did
with the BuildGates pricing, who knows?
By the way, I would recommend testing the ModelTech, playing with its
windows environment, discovering that it is not comparable to a real one
(like Virsim or Novas or SignalScan), and then hitting up your budget people
for the 5K to get a real one - the ModelTech windows expect you to be in
interactive mode for anything but the waveform tools - the other ones give
you an entire debug environment in post simulation mode - by the way, I
misspoke on Novas - it runs about 20K, but by DAC timeframe will be able to
do full post simulation debugging on a mixed VHDL/Verilog simulation -
pretty cool - VirSim can do both languages, but not to the extent of Novas -
hence VirSim's ~ 5K price tag - what about UnderTow?? Anybody like that one
for VHDL and Verilog?).
(By the way, the Ashenden book - The designer's guide to VHDL - is a really
good book - since we don't need HDL training, just VHDL information - it
does a good job of describing the language itself, rather than how to use
the langauge to build hardware).

With the Xilinx tools you get a floorplanner (which you will need to use for
tight timing constraints - however, it is nowhere near the floorplanner you
were used to as an ASIC designer. In the Xilinx floorplanner (and I
understand there is some effort to change this), you have to specify the
layout of every cell (or LUT or CLB or whatever - FPGA folks correct me on
terminolgy here) - it is more what we would consider a placement tool rather
than a standard ASIC floorplanner - sort of a bummer - actually, quite a
bummer. This only runs about $1500 (again for UNIX). Hopefully Xilinx can
get a real floorplanner (in the ASIC sense of a floorplanner) in there soon.

As for schematics, I can't help you there - I am sure there are quite a few
people who still use them, however, for the larger parts, schematic capture
can be rather extensive. I know some shops use schematics to do top level
connections as well as low level macros (in order to get really good
timing). Don't know if that's what you want or not. Interesting point here,
with the larger parts, the FPGA design flow is almost what we are used to in
ASIC's (maybe using shcematics for top level, and cell designers for low
level)  - with the exception of the following:

   Why do you want back annotation into the simulator? You get static timing
analysis  with the layout tools and you get real life simulation with the
FPGA. Remember, we no longer have to get it right the first time :-).

   Synthesis is pretty much between Synplcity, Synopsys FPGA-Express, and
Mentor's Leonardo. All of them will synthesize. We went with Synplicity, and
it does its job, but I would not begin to hold a flag for one of these
products as vastly better than the other - they all work (although Mentor
seemed to want to deal the most - I guess that's what falling in market
share does).

   For a platform, we chose an Annapolis Microsystems Starfire board with a
Virtex-1000 part on it - at least to start playing with. I was more
interested in having all of the C level API's, a PCI bus interface, and
simulation models for the board. Makes it so you can go right at playing
with the FPGA rather than trying to figure out your own API's to talk to the
board, figuring out how to program the little fella's, and being able to
simulate the entire system. However, it costs about $10,000 more than the
little test boards. If you do go with a PC option (some of my friends did
this with laptops and they loved it - again, Modeltech and Synplcicty),
Annapolis has a cool little card that gives you a Virtex in a Cardbus slot.
Not only is this just cool to play with, it is only about 1K.

OK you FPGA experts, please correct me where I am wrong or where you
disagree (save your VHDL comments) These are just the opinions of a stupid
former ASIC yet devoted Verilog guy :-)

Cheers,
Gary Spivey
spivey@rincon.com


<sweazle@my-deja.com> wrote in message news:<88a03i$8f3$1@nnrp1.deja.com>...
> I'm going to a new job where I will be doing FPGA's and will have to
> acquire the software and programmer for them. There will be a budget
> constraint so price will be an issue. I'm looking for advice on the
> "best" set of tools for this and price. What I'll be looking for is:
>
> 1. Schematic capture
> 2. Verilog (or could learn VHDL) simulation
> 3. Floor-planning would be nice
> 4. Synthesis (at least ability to add later)
> 5. Place and route with back annotation into the simulator
> 6. An FPGA programmer
>
> As the projects will be varied, I believe I will be using different
> companies FPGA's so having a set of tools that could use different
> libraries and a programmer that can program those parts is required.
>
> I have 15 years experience designing digital I.C.'s using Cadence so a
> set of tools like Composer/NCVerilog/BuildGates would be nice, but is
> far too expensive for this place.
>
> Expected size of devices will be 2K - 50K gates (in IC terms, not sure
> how that relates to FPGA's) plus 0 - 40Kbits memory (internal would be
> good but could be external).
>
> Any advice is welcome.
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



Article: 20564
Subject: Re: Xilinx Virtex Reset
From: Ray Andraka <randraka@ids.net>
Date: Mon, 14 Feb 2000 23:53:14 GMT
Links: << >>  << T >>  << A >>
It's only free if it meets timing.  I think you'll find that you are past it at
74MHz.  Even in the 4K parts, GSR was only good up to a fraction of the clock
rate the part can easily achieve with careful design.  Also, the GSR hits every
single flip-flop in the design, which in some cases can cause you grief
(especially when you consider the need to resync the reset).

Mark Luscombe wrote:

> Ray,
>
> Thanks for your input, but if the GSR net is used, then routing and
> CLB resources are not used, as it is a "free" function.
>
> The Xilinx Rep is coming to see me Monday, so hopefully he'll be able
> to say whether i can use the GSR net at 74MHz.
>
> Cheers, Mark.
>
> On Sun, 13 Feb 2000 17:27:01 GMT, Ray Andraka <randraka@ids.net>
> wrote:
>
> >Not every flip flop in an FPGA design needs to be reset;  You only need to
> >reset select flip-flops to make sure that 'loops' in the logic reach a known
> >state after some number of clock cycles.  Data path will self clear, so
> >there's no need to apply explicit resets.  You may also want to reset the
> >flip-flops closest to the outputs, and hold them reset for a number of
> >clocks after reset is released.
> >
> >I know that this makes the ASIC guys blood curdle, but the fact of the
> >matter is that it uses up resources in the FPGA and slows down your design.
> >
> >Rickman wrote:
> >
> >> Mark Luscombe wrote:
> >> >
> >> > Hi,
> >> >
> >> > I am trying to work out a satifactory method for resetting a
> >> > synchronously design Virtex running at 74MHz.
> >> >
> >> > Now, the reset signal needs to be synchronised with the 74MHz clock
> >> > and the propagation delay from this to the CLB and IOB DFFs needs to
> >> > be less than 13ns to ensure that all registers within the device at
> >> > reset on the sam clock edge.
> >> >
> >> > Xilinx seem to have been telling people not to use the GSR net, as it
> >> > is too slow, but it does seem a pity not to use it, and use extra
> >> > routing and CLB inputs for a global reset.
> >> >
> >> > It seems as though the STARTUP_VIRTEX component can accept a USER_CLK
> >> > input, i.e. the 74MHz, so is this a good solution ?
> >> > Also, this component has a GSR input for an external reset signal,
> >> > does anybody know if this is also synchronised with the USER_CLK input
> >> > ?
> >> > The device is configured in 8-bit parallel with CCLK which is related
> >> > to the 74MHz.
> >> >
> >> > What have other designers done in this situation.
> >> >
> >> > Cheers, Mark.
> >>
> >> This is a subject that is often discussed here. What you describe with
> >> using a user clock for startup is one way to do it. That should work if
> >> the GSR net is fast enough to operate within your clock cycle.
> >>
> >> Another way to use the GSR which does not depend on sychronized release
> >> of the GSR is to make sure that all of the inputs to your various FSMs
> >> or other sychronous logic are in a state that will not cause the
> >> machines to make a state change. For example if the FSMs reset to an
> >> IDLE state, then make sure that none of the inputs that let the machine
> >> leave the IDLE state are asserted. Then even if the GSR is released on
> >> different clock cycles for different FFs, it will not matter.
> >>
> >> Or use a couple of delay FFs to generate (from the GSR) a separate,
> >> synchronized input to the FSMs which will delay state changes from this
> >> initial state until it releases. This net will not need to go to all of
> >> the FFs in your design and can be routed much faster.
> >>
> >> Another method which is similar to this last one is to have a separate,
> >> external reset signal which is controlled by a micro or other logic.
> >> This will only be released well after the config is complete and is
> >> synchrnized to the clock. As in the last method, this reset will not
> >> need to go to every FF in the FPGA and so can be routed more quickly.
> >>
> >> The GSR is nice in that it puts every FF into a known state and it is
> >> asynch so it does it NOW! But releasing it can be a problem. A second,
> >> more limited reset is a good way to get the FPGA started on the right
> >> foot.
> >>
> >> I can't remember other ways that have been described, but I am sure
> >> there are some.
> >>
> >> --
> >>
> >> Rick Collins
> >>
> >> rick.collins@XYarius.com
> >>
> >> remove the XY to email me.
> >>
> >> Arius - A Signal Processing Solutions Company
> >> Specializing in DSP and FPGA design
> >>
> >> Arius
> >> 4 King Ave
> >> Frederick, MD 21701-3110
> >> 301-682-7772 Voice
> >> 301-682-7666 FAX
> >>
> >> Internet URL http://www.arius.com
> >
> >--
> >-Ray Andraka, P.E.
> >President, the Andraka Consulting Group, Inc.
> >401/884-7930     Fax 401/884-7950
> >email randraka@ids.net
> >http://users.ids.net/~randraka
> >
> >

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20565
Subject: Re: Advice please
From: "Gary Spivey" <spivey@rincon.com>
Date: Mon, 14 Feb 2000 17:02:45 -0700
Links: << >>  << T >>  << A >>
>    Why do you want back annotation into the simulator? You get static
timing
> analysis  with the layout tools and you get real life simulation with the
> FPGA. Remember, we no longer have to get it right the first time :-).
>

Actually, let me follow up my question with a more open ended question to
the group - Who out there does do back annotation of timing into the
simulator? How often? Do most people attempt to find these problems with
some sort of on chip debugging practice? Or do most FPGA designers rely on
some form of back annotation?

How accurate are the static timing analyzers? In a perfect ASIC world, a
designer would use functional verification, static timing analysis, and then
do formal verification to verify the pre and post sysnthesis netlists match
(actually, I assume that some shops actually do this :-). The whole goal of
all of this was to get rid of the backannotated timing simulation. In the
FPGA, it seems to me that the formal verification is done by programming and
running the chip.

Any thoughts?

Cheers,
Gary Spivey
spivey@rincon.com


Article: 20566
Subject: Re: LUT & VHDL
From: raja <raja@elec.uq.edu.au>
Date: Tue, 15 Feb 2000 10:31:19 +1000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Transfer-Encoding: 7bit

Hi,
yes of course . you can decribe LUT using vhdl . LUT is basically a RAM with
some contents . first try to model a ram and then define the ram as per your
inputs . I have experienced in designing  4 input LUT. it works without
using FPGA vendor specific library.
hope this helps

kamal

Jamil Khatib wrote:

> Hi,
>
> Is there any way to use the LUT by VHDL code, that is to write a VHDL
> code "without using the FPGA vendor specific library" that I can know in
> advance that it will be
> synthesized to LUT or is it just the synthesizer problem? I need this
> feature because I want to test some techniques I learned about LUT usage
>
> Thanks
> Jamil Khatib
> OpenIP Organization   http://www.openip.org
> OpenIPCore Project   http://www.openip.

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n:kamalanathan;Raja
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email;internet:raja@elec.uq.edu.au
fn:Raja kamalanathan
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--------------24B77370D908D8E08E26E11D--

Article: 20567
Subject: Re: Advice please
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 14 Feb 2000 17:36:02 -0700
Links: << >>  << T >>  << A >>
Gary Spivey wrote in message <88a513$29p$1@nnrp02.primenet.com>...
>>    Why do you want back annotation into the simulator? You get static
>timing
>> analysis  with the layout tools and you get real life simulation with the
>> FPGA. Remember, we no longer have to get it right the first time :-).
>>
>
>Actually, let me follow up my question with a more open ended question to
>the group - Who out there does do back annotation of timing into the
>simulator? How often? Do most people attempt to find these problems with
>some sort of on chip debugging practice? Or do most FPGA designers rely on
>some form of back annotation?

I always take the post-route simulation source/SDF and do a board-level
timing simulation.  of course, it's only as accurate as the models of the
rest of the system, and clearly, estimates of board delay and timing based
on loading can be little more than a WAG, but it can be very helpful in
finding problems.  Assuming that much of the hard work in verification was
done up front, it shouldn't take too long.  It ends up being an idiot check.
It can point out things you didn't account for in your static timing
constraints.

ymmv.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 20568
Subject: Re: Advice please
From: Ray Andraka <randraka@ids.net>
Date: Tue, 15 Feb 2000 01:22:18 GMT
Links: << >>  << T >>  << A >>
Back annotation, what's that?  My methodology is to do a functional simulation
on the design and on the synthesized design if I use synthesis, followed by a
static timing analysis.  Timing simulations in FPGAs are dangerous at best,
especially in heavily arithmetic circuits.  The static timing tools with the
FPGA suites are quite accurate, and if you do synchronous design, are easy to
use.  I verify the design before it goes to a bitstream.  I don't care much for
chasing problems in the lab, and honestly I more often than not never even set
eyes on the FPGA or the board the design goes into.  Programming and running the
chip can accelerate verification if you are careful, since the FPGA does run a
heckuva lot faster than the simulator.  The important thing there is to have the
hooks to get controllability and observability into the design (probes ain't
gonna cut it here, but reconfigurability is a big plus).  You also want to pass
a rigorous static timing analysis and at least some basic functional sims on the
modules in the design before you put bitstreams to silicon lest you spend the
rest of your career in the lab..

Gary Spivey wrote:

> >    Why do you want back annotation into the simulator? You get static
> timing
> > analysis  with the layout tools and you get real life simulation with the
> > FPGA. Remember, we no longer have to get it right the first time :-).
> >
>
> Actually, let me follow up my question with a more open ended question to
> the group - Who out there does do back annotation of timing into the
> simulator? How often? Do most people attempt to find these problems with
> some sort of on chip debugging practice? Or do most FPGA designers rely on
> some form of back annotation?
>
> How accurate are the static timing analyzers? In a perfect ASIC world, a
> designer would use functional verification, static timing analysis, and then
> do formal verification to verify the pre and post sysnthesis netlists match
> (actually, I assume that some shops actually do this :-). The whole goal of
> all of this was to get rid of the backannotated timing simulation. In the
> FPGA, it seems to me that the formal verification is done by programming and
> running the chip.
>
> Any thoughts?
>
> Cheers,
> Gary Spivey
> spivey@rincon.com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20569
Subject: Re: Xilinx Virtex Reset
From: murray@pa.dec.com (Hal Murray)
Date: 15 Feb 2000 02:22:57 GMT
Links: << >>  << T >>  << A >>

In article <38A8959D.66710000@ids.net>,
 Ray Andraka <randraka@ids.net> writes:
> It's only free if it meets timing.  I think you'll find that you are past it at
> 74MHz.  Even in the 4K parts, GSR was only good up to a fraction of the clock
> rate the part can easily achieve with careful design.  Also, the GSR hits every
> single flip-flop in the design, which in some cases can cause you grief
> (especially when you consider the need to resync the reset).

Suggestion to vendors:

  Please sdd that timing spec to your data sheets.

I think the only case I'm interested in is coming out of
reset cleanly.  I'd be happy if the Reset signal went through
some internal logic to clean things up - that delay doesn't bother
me.

-- 
These are my opinions, not necessarily my employers.
Article: 20570
Subject: Re: Xilinx Virtex Decoupling Cap Guidelines
From: "peter dudley" <padudle@worldnet.att.net>
Date: Tue, 15 Feb 2000 03:47:14 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

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--=20
Pete Dudley

Arroyo Grande Systems

Andreas Heiner <Andreas.Heiner@de.bosch.com> wrote in message =
news:880gv5$hin$1@proxy.fe.internet.bosch.de...
>=20
> > I aggree the Xilinx recommendation is overkill.
> >
> > I use one 10uF, two or three 1uF tantalums per board per power =
plane. For
> > the Virtex 300 I use eight .01uF ceramic caps on each of its two =
power
> > supplies. The fpga runs at 125 MHz with lots of simultaneous =
switching.
> >
> > If you can afford good power/ground planes, don't worry about =
getting the
> > caps directly adjacent to the power pins of the fpga. What you =
should be
> > doing is AC coupling together the ground and power planes.
> >
> > For the ultimate in high frequency decoupling it's possible to use =
"buried
> > capacitance layers" imbedded directly into the board. These are
> power/ground
> > layers placed very close together in the board stack up.
>=20
> The last two things are exactly what I mean with bideband decoupling. =
A very
> good AC coupling over the whole frequence range (requires a filter =
design)
> and very close power layers (we're using 68um, the last boards has =
50um
> distance between the layers).
Very good. I can't remember exactly how thin the buried capacitance =
layer is that we use but it might be a little thinner, like 25um ~ 1 =
mili inch.
>=20
> >
> > Avoid creating islands in the ground or power planes as these will =
only
> > degrade signal integrity.
>=20
> If you will separate the ground plane the design would !!! NOT !!! =
work
> !!!!. Please don't do this! The separation of the VCC plane is just
> neccessary for two purposes:
> 1. The possible max decoupling frequency depends on the size of the =
area. If
> you decrease the area, you increase the maximun decoupling frequency
> (physical law). Our program calculates up to 1 GHz.
Here's where I disagree. The thing that limits the performance of =
decoupling is the inductance in the power supply pins. Creating an =
"island" does nothing to reduce the inductance and only reduces the =
available capacitance to decouple your part.=20
> 2. If you have analog and digital parts on one PCB it is much better =
to
> seperate the power planes. It's the same for "rough" digital logic (as
> FPGA's) and "sensible" logic (as SDRAM's). But this is not absolutely
> neccessary.
Here again you are a little off base. You want continuous power and =
ground planes as much as possible between digital chips in your system. =
Power planes often act as reference planes for the AC return current of =
a signal trace. If you cut the power planes you will increase inductance =
in the signal trace that wil reduce the performance of your board and =
increase EMI. I realize that you often have to spit power planes just to =
reduce the number of layers in the board, but this should be avoided =
where possible.

I can recommend a book on this subject.

 High Speed Digital Design: A Handbook of Black Magic=20
by Howard W., Ph.D. Johnson, Martin, Ph.D. Graham=20
 =20
    =20
    =20
Textbook Binding - 384 pages 1 edition (April 8, 1993)=20
Prentice Hall; ISBN: 0133957241=20






Adios


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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2722.2800" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY>
<DIV>&nbsp;</DIV>
<DIV><BR><FONT face=3DArial size=3D2>-- <BR>Pete Dudley</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Arroyo Grande Systems<BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Andreas Heiner &lt;<A=20
href=3D"mailto:Andreas.Heiner@de.bosch.com">Andreas.Heiner@de.bosch.com</=
A>&gt;=20
wrote in message <A=20
href=3D"news:880gv5$hin$1@proxy.fe.internet.bosch.de">news:880gv5$hin$1@p=
roxy.fe.internet.bosch.de</A>...</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>&gt; <BR>&gt; &gt; I aggree the Xilinx=20
recommendation is overkill.<BR>&gt; &gt;<BR>&gt; &gt; I use one 10uF, =
two or=20
three 1uF tantalums per board per power plane. For<BR>&gt; &gt; the =
Virtex 300 I=20
use eight .01uF ceramic caps on each of its two power<BR>&gt; &gt; =
supplies. The=20
fpga runs at 125 MHz with lots of simultaneous switching.<BR>&gt; =
&gt;<BR>&gt;=20
&gt; If you can afford good power/ground planes, don't worry about =
getting=20
the<BR>&gt; &gt; caps directly adjacent to the power pins of the fpga. =
What you=20
should be<BR>&gt; &gt; doing is AC coupling together the ground and =
power=20
planes.<BR>&gt; &gt;<BR>&gt; &gt; For the ultimate in high frequency =
decoupling=20
it's possible to use "buried<BR>&gt; &gt; capacitance layers" imbedded =
directly=20
into the board. These are<BR>&gt; power/ground<BR>&gt; &gt; layers =
placed very=20
close together in the board stack up.<BR>&gt; <BR>&gt; The last two =
things are=20
exactly what I mean with bideband decoupling. A very<BR>&gt; good AC =
coupling=20
over the whole frequence range (requires a filter design)<BR>&gt; and =
very close=20
power layers (we're using 68um, the last boards has 50um<BR>&gt; =
distance=20
between the layers).</FONT></DIV>
<DIV><FONT color=3D#008000 face=3DArial size=3D2>Very good. I can't =
remember exactly=20
how thin the buried capacitance layer is that we use but it might be a =
little=20
thinner, like 25um ~ 1 mili inch.<BR></FONT><FONT face=3DArial =
size=3D2>&gt;=20
<BR>&gt; &gt;<BR>&gt; &gt; Avoid creating islands in the ground or power =
planes=20
as these will only<BR>&gt; &gt; degrade signal integrity.<BR>&gt; =
<BR>&gt; If=20
you will separate the ground plane the design would !!! NOT !!! =
work<BR>&gt;=20
!!!!. Please don't do this! The separation of the VCC plane is =
just<BR>&gt;=20
neccessary for two purposes:<BR>&gt; 1. The possible max decoupling =
frequency=20
depends on the size of the area. If<BR>&gt; you decrease the area, you =
increase=20
the maximun decoupling frequency<BR>&gt; (physical law). Our program =
calculates=20
up to 1 GHz.</FONT></DIV>
<DIV><FONT color=3D#008000 face=3DArial size=3D2>Here's where I =
disagree. The thing=20
that limits the performance of decoupling is the inductance in the power =
supply=20
pins. Creating an "island" does nothing to reduce the inductance and =
only=20
reduces the available capacitance to decouple your part. =
<BR></FONT><FONT=20
face=3DArial size=3D2>&gt; 2. If you have analog and digital parts on =
one PCB it is=20
much better to<BR>&gt; seperate the power planes. It's the same for =
"rough"=20
digital logic (as<BR>&gt; FPGA's) and "sensible" logic (as SDRAM's). But =
this is=20
not absolutely<BR>&gt; neccessary.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><FONT color=3D#008000>Here again you =
are a little off=20
base. You want continuous power and ground planes as much as possible =
between=20
digital chips in your system. Power planes often act as reference planes =
for the=20
AC return current of a signal trace. If you cut the power planes you =
will=20
increase inductance in the signal trace that wil reduce the performance =
of your=20
board and increase EMI. I realize that you often have to spit power =
planes just=20
to reduce the number of layers in the board, but this should be avoided =
where=20
possible.</FONT></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><FONT =
color=3D#008000></FONT></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><FONT color=3D#008000>I can recommend a =
book on this=20
subject.</FONT></FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><FONT =
color=3D#008000>&nbsp;<STRONG><FONT=20
face=3Dverdana,arial,helvetica>High Speed Digital Design: A Handbook of =
Black=20
Magic</FONT></STRONG> <FONT face=3Dverdana,arial,helvetica =
size=3D-1><BR>by <A=20
href=3D"http://www.amazon.com/exec/obidos/Author=3DJohnson%2C%20Howard%20=
W.%2C%20Ph.D./102-8613139-9272007">Howard=20
W., Ph.D. Johnson</A>, <A=20
href=3D"http://www.amazon.com/exec/obidos/Author=3DGraham%2C%20Martin%2C%=
20Ph.D./102-8613139-9272007">Martin,=20
Ph.D. Graham</A>&nbsp;</FONT><BR>=20
<TABLE align=3Dright border=3D0 width=3D190 hspace=3D"3" vspace=3D"3">
  <TBODY>
  <TR>
    <TD></TD></TR>
  <TR align=3Dmiddle>
    <TD></TD></TR>
  <TR>
    <TD></TD></TR></TBODY></TABLE><FONT face=3Dverdana,arial,helvetica =
size=3D-1>
<P></FONT><FONT face=3Dverdana,arial,helvetica size=3D2><B>Textbook =
Binding</B> -=20
384 pages 1 edition (April 8, 1993) <BR></FONT><FONT size=3D-2>Prentice =
Hall;=20
ISBN: 0133957241 </FONT><BR></FONT></P>
<P>&nbsp;</P>
<P>&nbsp;</P>
<P><FONT color=3D#008000>Adios</FONT></P></FONT></DIV></BODY></HTML>

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Article: 20571
Subject: decoder
From: rsche42109@aol.com (RSche42109)
Date: 15 Feb 2000 05:53:46 GMT
Links: << >>  << T >>  << A >>
I have a Posh MR3 programmable decoder version 6.1 and need software to make it
function.  Where can I get the software???????????
Article: 20572
Subject: Re: xilinx
From: "rodger" <brownsco@frii.com>
Date: Mon, 14 Feb 2000 22:59:39 -0700
Links: << >>  << T >>  << A >>
Try this:

http://www.xilinx.com/xapp/xapp058.pdf

The App Note is titled:

Xilinx In-System Programming Using an Embedded Microcontroller - XAPP058,
v2.0 (06/99)

It will get you started. The programming mode is JTAG and the included code
example is for a 8051, with minor modifications needed for other
architectures.

-r

<elynum@my-deja.com> wrote in message news:881ajg$c3l$1@nnrp1.deja.com...
> How would I go about programming 2 xilinx fpga's on a single board?
> Would I need 2 separate EEPROM chips(ATMEl) or just one?  How would
> I go about doing it with a microprocessor 8051 or 860?  What would I
> need to do this?
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 20573
Subject: BCH Implementation
From: gerizamir@my-deja.com
Date: Tue, 15 Feb 2000 06:40:55 GMT
Links: << >>  << T >>  << A >>
Hello,

My gold is to implement BCH Error detection and correction inside FPGA.

1. I would like u to help me find information about BCH Error detection
and correction.
2. If any one can direct me to VHDL code for that implementation.
3. I don't mind to buy a VHDL core for implement if over FPGA, So if any
one know a company that sale this kind of core please direct me to there
site.

I will really appreciate if any one will help me.

Thanks.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20574
Subject: clock
From: "Benoît HAMON" <benoit.hamon@elios-informatique.fr>
Date: Tue, 15 Feb 2000 10:37:06 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm trying to implemente (with "FOUNDATION implementation" in a Xilinx
CPLD9500) a function in order to delay an output from an input ?.

ex : clk_out <= clk_in after 10ns.
I found many VHDL example in Web, but never implemented.

NB: my aim is to create a Clock multiplier  : 13MHz => 26MHz.
Can someone please give me an example IMPLEMENTED ?.



Please Help me !.
Thank you in advance for your help.

benoit.hamon@elios-informatique.fr







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