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Messages from 20600

Article: 20600
Subject: Re: 100% slice utilization in Virtex FPGA
From: Kamal Chaudhary <kamal@xilinx.com>
Date: Tue, 15 Feb 2000 14:58:33 -0800
Links: << >>  << T >>  << A >>
Don't be alarmed by the 100% utilization figure. The mapper will pack
things more tight only if needed. You can safely add more logic to
the device. If you would like the mapper to pack as much as possible
use -c 1 switch.

Kamal.

Matt Gavin wrote:

> FPGA gurus,
>
> I am trying to fit a design in a Virtex XCV300 (2.5V part).
> The Xilinx mapper reports 100% slice utilization, which shocked me.
> However, if you do the math on their flop and LUT counts,
> (assuming 2 flops and LUTs per slice), the flop and LUT utilizations
> are 55% and 76%, repectively, which is what I expected.
> The equivalent gate count is ~60K, which isn't that high
> (especially since Xilinx claims that 322K system gates can fit in
> a XCV300.)
>
> Should I be worried that my slice utilization is 100%?
> Why would the mapper choose to use every single slice
> if the flop and LUT counts are so low?
>
> The report is given below for reference.
>
> Thanks for any help,
>
>    Matt Gavin
>    mtgavin@collins.rockwell.com
>
> ------------------
> Command Line   : map -p xcv300-5-pq240 -o map.ncd mimas_fpga.ngd
> mimas_fpga.pcf
> Target Device  : xv300
> Target Package : pq240
> Target Speed   : -5
> Mapper Version : virtex -- C.19
> Mapped Date    : Mon Feb 14 17:08:18 2000
>
> Design Summary
> --------------
>    Number of errors:      0
>    Number of warnings:    4
>    Number of Slices:            3,072 out of  3,072  100%
>       Slice Flip Flops:   3,408
>       4 input LUTs:       4,682 (4 used as a route-thru)
>    Number of Slices containing
>       unrelated logic:            948 out of  3,072   30%
>    Number of bonded IOBs:         120 out of    166   72%
>    Number of GCLKs:                 4 out of      4  100%
>    Number of GCLKIOBs:              3 out of      4   75%
> Total equivalent gate count for design:  60,367
> Additional JTAG gate count for IOBs:  5,904


Article: 20601
Subject: Re: FPGA Express/XC4KXLA annoyance
From: "John Fielden" <motorola@john.fielden.com>
Date: Tue, 15 Feb 2000 17:47:35 -0700
Links: << >>  << T >>  << A >>
Which OBUFT do you have instantiated.  There are two different kinds, active
high and active low enabled.  Maybe you need the opposite one.

Andy Peters wrote in message <889vgi$30a6$1@noao.edu>...
>OK, so I have this all-VHDL design that fits into 83% of an XC4013XLA.  My
>clock is 80 MHz.  The chip has an SDRAM interface (I have an external PLL
>clock buffer that generates the FPGA clock and the SDRAM clock).  I set an
>offset constraint on the SDRAM data, address and control lines to ensure
>that I meet the SDRAM setup requirements.
>
>Since the SDRAM data bus is bidirectional, I have an output enable for the
>data bus.  This output enable is generated by a state machine and is
>registered.  The SDRAM data bus outputs are registered in the IOBs, too.
>
>After place and route, trce tells me that some of my SDRAM data bus outputs
>aren't meeting the timing constraints.  A bit of poking around in FPGA
>Editor tells me that, for some reason, the output enable signal doesn't go
>directly to the IOBs; rather, it gets "looped back" into the CLB where its
>register is, gets run through an LUT, and that LUT's output gets
distributed
>to the IOBs where it drives the tristate enable.
>
>Turns out that the LUT simply inverts the output enable signal.
>Unfortunately, the delay through the LUT is enough to cause me to fail
>timing (otherwise, I would never have noticed this!).  Sooooo...what's
>causing this?
>
>Back to FPGA Express.  I open the optimized design's schematic and find the
>reason:  it turns out that FPGA Express runs my output enable through an
>inverter!  My code generates the output enable as active high, which is
>reasonable because while the tristate enable in the IOB is active low,
>there's a mux in the IOB that selects active low or active high tristate
>enable.  (This mux is present on all of the XC4K parts, at least back to
the
>to invert the output enable!
>
>The "fix" is obvious - I just went back into my state machine and made that
>output enable signal active low.  Now, the registered (in the CLB; using
the
>registered tristate in the IOB is a PITA) output enable drives the tristate
>enables in the IOBs properly, and I meet timing, too.
>
>Note to synopsys: fix this bug, please. Now.  OK, so maybe it's not a bug.
>But it would be nice if the tools supported the architectural features!  I
>can't believe this hasn't been 'discovered' before.
>
>Note to Xilinx: howzabout getting that registered tristate enable in the
>IOBs to work without having to use a silly black-box-Perl-script-driven
>HACK?  Those flops have been around since you introduced the "X" series
>parts.  How long ago was that?
>
>-- a
>-----------------------------------------
>Andy Peters
>Sr Electrical Engineer
>National Optical Astronomy Observatories
>950 N Cherry Ave
>Tucson, AZ 85719
>apeters (at) noao \dot\ edu
>
>"Money is property; it is not speech."
>            -- Justice John Paul Stevens
>
>


Article: 20602
Subject: synopsys, vhdl, verilog specs free?
From: "funky jim" <jmc8197@hotmail.com>
Date: Wed, 16 Feb 2000 01:00:14 -0000
Links: << >>  << T >>  << A >>
Am i gonna have to pay for all the above specs?

cheers.


Article: 20603
Subject: Verilog FAQ
From: rajesh52@hotmail.com
Date: Wed, 16 Feb 2000 01:41:18 GMT
Links: << >>  << T >>  << A >>
Greetings
This is semimonthly announcement of Verilog FAQ.

Verilog FAQ is located at
http://www.angelfire.com/in/verilogfaq/

Alternate Verilog FAQ is an attempt to gather the answers
one place. It also  contains list of publications, services,
and products.

Alternate Verilog FAQ is divided into three logical parts.

Part 1 : Introduction and misc. questions
Part 2 : Technical Topics
Part 3 : Tools and Services

What's New section outlines the changes in different versions
and announcements. Links connects you to related
informative

welcome.

Rajesh Bawankule
(Also Visit Verilog Center :
http://www.angelfire.com/in/rajesh52/verilog.html )

Sent via Deja.com http://www.deja.com/

Article: 20604
Subject: Re: xilinx
From: elynum@my-deja.com
Date: Wed, 16 Feb 2000 04:03:54 GMT
Links: << >>  << T >>  << A >>
I read the app note. It didn't mention about how to program the fpga
with an 8051 with just a buffer and ram.  Can you do that?  Can you do
it without using the jtag programmer?  It was kind of confusing and the
C code was fairly long.  It seems it would be faster to program with
just an eeprom.

n article <2X5q4.52$mjh.185876992@news.frii.net>, "rodger" <brownsco@frii.com> wrote: > Try this: > > http://www.xilinx.com/xapp/xapp058.pdf > > The App Note is titled: > > Xilinx In-System Programming Using an Embedded Microcontroller - XAPP058, > v2.0 (06/99) > > It will get you started. The programming mode is JTAG and the included code > example is for a 8051, with minor modifications needed for other > architectures. > > -r > > <elynum@my-deja.com> wrote in message news:881ajg$c3l\$1@nnrp1.deja.com...
> > How would I go about programming 2 xilinx fpga's on a single board?
> > Would I need 2 separate EEPROM chips(ATMEl) or just one?  How would
> > I go about doing it with a microprocessor 8051 or 860?  What would I
> > need to do this?
> >
> >
> > Sent via Deja.com http://www.deja.com/
>
>

Sent via Deja.com http://www.deja.com/

Article: 20605
Subject: Simulating Virtex
From: "Matt Billenstein" <mbillens@one.net>
Date: Wed, 16 Feb 2000 05:36:25 GMT
Links: << >>  << T >>  << A >>
All, I'm currently using Orcad tools (Capture/Simulate 9.1) to do a timing
simulation of my Xilinx designs, but I'm having problems getting my tools to
work with simulating a new Virtex design.  I think I don't have the
libraries necessary to describe all the components of the Virtex
architecture, so when I load the design I get a ton of errors...  What tools
are you folks using to simulate Virtex?  And is anyone using the tools that
I am that could lend a hand?

thx

m

--

Matt Billenstein
http://w3.one.net/~mbillens/
mbillens@one.net


Article: 20606
Subject: Re: 100% slice utilization in Virtex FPGA
From: gazit@my-deja.com
Date: Wed, 16 Feb 2000 08:08:30 GMT
Links: << >>  << T >>  << A >>
Matt,
try to use "map -c 1 ..........."  it will improve your device
utilization.
My experience shows that the ratio between the real gate count and
Xilinx numbers is ~1/5 ( 60K ASIC system gates into a "xcv300" device
sounds reasonable  ratio).
If your design is going to be changed you should consider immigrating
to a larger device. I believe you can use the same foot print.
Good luck.

-----------------------------------------------
Rotem Gazit
mailto:XXrotemg@mysticom.com
(remove XX to send mail)
MystiCom  LTD.
http://www.mysticom.com
-----------------------------------------------

In article <38A978D6.F2364810@collins.rockwell.com>,
Matt Gavin <mtgavin@collins.rockwell.com> wrote:
> FPGA gurus,
>
> I am trying to fit a design in a Virtex XCV300 (2.5V part).
> The Xilinx mapper reports 100% slice utilization, which shocked me.
> However, if you do the math on their flop and LUT counts,
> (assuming 2 flops and LUTs per slice), the flop and LUT utilizations
> are 55% and 76%, repectively, which is what I expected.
> The equivalent gate count is ~60K, which isn't that high
> (especially since Xilinx claims that 322K system gates can fit in
> a XCV300.)
>
> Should I be worried that my slice utilization is 100%?
> Why would the mapper choose to use every single slice
> if the flop and LUT counts are so low?
>
> The report is given below for reference.
>
> Thanks for any help,
>
>    Matt Gavin
>    mtgavin@collins.rockwell.com
>
> ------------------
> Command Line   : map -p xcv300-5-pq240 -o map.ncd mimas_fpga.ngd
> mimas_fpga.pcf
> Target Device  : xv300
> Target Package : pq240
> Target Speed   : -5
> Mapper Version : virtex -- C.19
> Mapped Date    : Mon Feb 14 17:08:18 2000
>
> Design Summary
> --------------
>    Number of errors:      0
>    Number of warnings:    4
>    Number of Slices:            3,072 out of  3,072  100%
>       Slice Flip Flops:   3,408
>       4 input LUTs:       4,682 (4 used as a route-thru)
>    Number of Slices containing
>       unrelated logic:            948 out of  3,072   30%
>    Number of bonded IOBs:         120 out of    166   72%
>    Number of GCLKs:                 4 out of      4  100%
>    Number of GCLKIOBs:              3 out of      4   75%
> Total equivalent gate count for design:  60,367
> Additional JTAG gate count for IOBs:  5,904
>
>

Sent via Deja.com http://www.deja.com/

Article: 20607
Subject: Re: Simulating Virtex
From: "Jean-Paul GOGLIO" <goglio@getris.alpes-net.fr>
Date: Wed, 16 Feb 2000 09:22:47 +0100
Links: << >>  << T >>  << A >>

Matt Billenstein a écrit dans le message ...
>All, I'm currently using Orcad tools (Capture/Simulate 9.1) to do a timing
>simulation of my Xilinx designs, but I'm having problems getting my tools
to
>work with simulating a new Virtex design.  I think I don't have the
>libraries necessary to describe all the components of the Virtex
>architecture, so when I load the design I get a ton of errors...  What
tools
>are you folks using to simulate Virtex?  And is anyone using the tools that
>I am that could lend a hand?
>
>thx
>
>m
>
>--
>
>
>Matt Billenstein
>http://w3.one.net/~mbillens/
>mbillens@one.net
>
>
>
>

One month a go, i saw a demo of Capture/simulate 9.1,
the guy was simulating a design with a 4005 half full and my impression was
it was running as slow as the one i was doing on Active VHDL with a Virtex
600E 100%full. So, i don't believe that Capture/simulate 9.1 is the good
soft for Virtex simulation.

Rather use Aldec Active VHDL or Modelsim.
For what i know, the prices are quite the same.
For myself, i choosed Aldec 18 months a go and i'm quite satisfied of it.
(i simulate multi virtex designs).

J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
E-mail : goglio@getris.com
Fax : (33) 4 76 18 52 01


Article: 20608
Subject: Re: coregen-bug produces bad blockram > 16 bit
From: P Little <little_pete@hotmail.com>
Date: Wed, 16 Feb 2000 11:25:08 +0000
Links: << >>  << T >>  << A >>
Which patch do you have installed for COREGen?

Regards,

Pete

Mark Hillers wrote:
>
> Hello,
>
> i think i have found a bug in xilinx-tool coregen 2.1i.
> it happens when creating single-port-blockrams with words larger than 16
> bit.
>
> the resulting ".edn"-file (for synopsys) uses one RAMB4_S16_S16
> component where the
> lower 16 bit of the 24-bit-word are mapped to port A (DOA[15:0]) and the
> upper 8 bit are mapped to port B (DOA[15:8]).
> But - and here comes the bug - the address of the desired word is simply
> following way:
>
> ADDRA(7 downto 5) = "000"
> ADDRB(7 downto 5) = "000"
>
> The problem is now that always both ports load the same address and with
> it the same data. The Result is an output which has the form CDABCD
> where A,B,C,D are hex-ciphers.
>
> In application-note XAPP130 (V1.1) is a solution to this problem. The
> mapping of the address-ports should be:
>
> ADDRA(7 downto 5) = "000"
> ADDRB(7 downto 5) = "100"
>
> Now I am looking for a simple patch. The simples would be a new version
> of coregen because i am not good in writing ".edn"-files :-(.
>
> greetings
> mark

Article: 20609
Subject: Re: coregen-bug produces bad blockram > 16 bit
From: usenet@brucke.de (Matthias Brucke)
Date: Wed, 16 Feb 2000 11:40:14 GMT
Links: << >>  << T >>  << A >>
On Wed, 16 Feb 2000 11:25:08 +0000, P Little <little_pete@hotmail.com>
wrote:

>Which patch do you have installed for COREGen?
>
>Regards,
>
>Pete

We work in the same department and we have installed patch #5 ;)

regards

mats
--
No Sig

Article: 20610
Subject: Re: clock
From: jball99653@aol.com
Date: Wed, 16 Feb 2000 11:51:07 GMT
Links: << >>  << T >>  << A >>
free  information wall clocksplesase e-mail to:jball99653@aol.com
http://members.aol.com/jball99653/usa.txt

Sent via Deja.com http://www.deja.com/

Article: 20611
Subject: multiplier
Date: Wed, 16 Feb 2000 18:29:19 +0530
Links: << >>  << T >>  << A >>
Hi,

Which would be the best implimentation of a multiplier in VHDL
(synthesisable) in terms of speed/area?
I know of array implimentation and the ragister configuration using a single
adder. Are there any other better ones ?
Thanks in anticipation,


Article: 20612
Subject: Re: clock
From: rob_dickinson@my-deja.com
Date: Wed, 16 Feb 2000 13:34:13 GMT
Links: << >>  << T >>  << A >>
Can I STRONGLY suggest that you spend a couple of hours finding out
what a CPLD is, otherwise this will only be the first of many foolish
things that you try to do with your "design".

I'm not that familliar with the XILINX CPLD's but if this is a one off
student(ish) design then you can delay your clock by feeding it through
at least three(?) macrocells and then EXOR the input clock with the
delayed version.  This will give you a very short pulse on the rising
and falling edge of your clock which you can clock everything else
with.

When you have discovered what a CPLD is you will see how dangerous this
is but it will get you out of a hole if your PCB is allready built.

Rob

Sent via Deja.com http://www.deja.com/

Article: 20613
Subject: Re: coregen-bug produces bad blockram > 16 bit
From: "Mark Hillers" <Mark.Hillers@Informatik.Uni-Oldenburg.DE>
Date: Wed, 16 Feb 2000 14:09:49 +0000
Links: << >>  << T >>  << A >>


Mark Hillers wrote:
> But - and here comes the bug - the address of the desired word is simply
> following way:
>
> ADDRA(7 downto 5) = "000"
> ADDRB(7 downto 5) = "000"

thats not really true. In the ".edn"-file from coregen the ADDRB(7) _is_
mapped to '1' but when loading and compiling it in design_analyzer this
ADDRB(7) is mapped to '0' commenting this with:

Warning: In design 'MYRAMLIB_rombsp32x24gain__block', there are 2 cells
that don't drive any nets. (LINT-30)
Warning: In design 'MYRAMLIB_rombsp32x24gain__block', there are 2 nets
with no drivers.  Logic 0 assumed. (LINT-30)

how can i aviod this?

the edif-predicates of .synopsys_dc.setup are

edifin_ground_port_name = "GROUND"
edifin_power_port_name = "VCC"
edifin_lib_logic_1_symbol = "VCC"
edifin_lib_logic_1_symbol = "GND"

Article: 20614
Subject: Using JTAG on XC4k
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Wed, 16 Feb 2000 14:19:22 +0000
Links: << >>  << T >>  << A >>
Although this has been kicked around before (great service, Deja News),
I can't find a specific reference to someone doing what I want to do
with a current XC4013E design.  Namely configure using master serial
mode from an EEPROM as per standard, but, optionally, use the JTAG port
to reconfigure.

According to the various Xilinx application notes and datasheets, as
long as the JTAG module is instantiated, all will be well.  So I can
hard-wire mode and programming pins to suit master serial, and don't
have to do anything about blipping /INIT (etc).  Just provide for
connection to the TAP (ensuring no noise could make it think it's
getting signals when nothing's connected) and do a JTAG download to the
powered-up and configured FPGA as and when.

It's not that I don't believe it can be done, just that I'd like to hear
that it _HAS_ been done!  Particularly if there were any aspects of
particularly well or badly.  I intend using a clone of the Xilinx DLC5
circuitry which has been proven on an XC9500 design.  Also, I've the
luxury of keeping dual-purpose pins to single-purpose use, so won't be

TIA.

--
Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions

Article: 20615
Subject: Re: Timing constraint on a DLL output
From: Kate Meilicke <Kate.Meilicke@xilinx.com>
Date: Wed, 16 Feb 2000 09:43:49 -0500
Links: << >>  << T >>  << A >>
Ooops...That should be:

There are NOT skew problems between the clk0 and 2x clock.  This is true
when global buffers are used.

That is what happens when the brain works faster than the fingers.

Kate


Article: 20616
Subject: Re: multiplier
From: Don McCarley <mccarley@lucent.com>
Date: Wed, 16 Feb 2000 09:58:11 -0500
Links: << >>  << T >>  << A >>
You might want to check out
http://modgen.fysel.ntnu.no/
There are Wallace tree multipliers there with pipelining options, these types
have given me the best results.

Don

> Hi,
>
> Which would be the best implimentation of a multiplier in VHDL
> (synthesisable) in terms of speed/area?
> I know of array implimentation and the ragister configuration using a single
> adder. Are there any other better ones ?
> Thanks in anticipation,
>


Article: 20617
Subject: Re: 100% slice utilization in Virtex FPGA
From: Ray Andraka <randraka@ids.net>
Date: Wed, 16 Feb 2000 15:28:55 GMT
Links: << >>  << T >>  << A >>
The mapper spreads the stuff out to reduce the route congestion unless
you use the c switch.  Depending on the speed requirements, you may also
find out how poor the automatic placer really is.

As to the gate count, keep in mind that the xilinx 'system gates' count
is based on using lots of memory both in the block memory and in the clb
RAM.  I prefer to call the Xilinx (and Altera) device gate counts
"marketing gates", as those counts have pretty much no basis in real
designs.  Count CLBs instead when fitting a design, and count LUTs when
comparing devices (with adjustments for special features).  There was a
discussion in EDN about 2 years ago on this topic, which I provided
technical background for.  There is a link to that article on my website
under the publications page.

Matt Gavin wrote:

> FPGA gurus,
>
> I am trying to fit a design in a Virtex XCV300 (2.5V part).
> The Xilinx mapper reports 100% slice utilization, which shocked me.
> However, if you do the math on their flop and LUT counts,
> (assuming 2 flops and LUTs per slice), the flop and LUT utilizations
> are 55% and 76%, repectively, which is what I expected.
> The equivalent gate count is ~60K, which isn't that high
> (especially since Xilinx claims that 322K system gates can fit in
> a XCV300.)
>
> Should I be worried that my slice utilization is 100%?
> Why would the mapper choose to use every single slice
> if the flop and LUT counts are so low?
>
> The report is given below for reference.
>
> Thanks for any help,
>
>    Matt Gavin
>    mtgavin@collins.rockwell.com
>
> ------------------
> Command Line   : map -p xcv300-5-pq240 -o map.ncd mimas_fpga.ngd
> mimas_fpga.pcf
> Target Device  : xv300
> Target Package : pq240
> Target Speed   : -5
> Mapper Version : virtex -- C.19
> Mapped Date    : Mon Feb 14 17:08:18 2000
>
> Design Summary
> --------------
>    Number of errors:      0
>    Number of warnings:    4
>    Number of Slices:            3,072 out of  3,072  100%
>       Slice Flip Flops:   3,408
>       4 input LUTs:       4,682 (4 used as a route-thru)
>    Number of Slices containing
>       unrelated logic:            948 out of  3,072   30%
>    Number of bonded IOBs:         120 out of    166   72%
>    Number of GCLKs:                 4 out of      4  100%
>    Number of GCLKIOBs:              3 out of      4   75%
> Total equivalent gate count for design:  60,367
> Additional JTAG gate count for IOBs:  5,904

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20618
Subject: Re: Virtex DLL inoperability
From: Ray Andraka <randraka@ids.net>
Date: Wed, 16 Feb 2000 15:32:05 GMT
Links: << >>  << T >>  << A >>
First, confirm that your input frequency is within the allowable range for
the DLL.  If it is, then check the signal quality of your input clock.  It
needs to be very clean with no corruption from reflections etc.  Also, check
the signal level to make sure it is within the range specified in the data
sheet for high and low values as well as transition time.

david gilchrist wrote:

> Steve Diferdinando wrote:
> >
> > Has anyone had trouble with the Virtex DLLs locking? If so, were you
> > able to find a workaround?
> >
> > Steve D.
>
> I have recently experienced some problem with DLLs locking on a
> development board from VCC.  The output clock appears to be very jittery
> and when I've attempted to double up the clock (using the CLK2X
> output).  The code was lifted straight from the Xilinx web site and
> looks fine when synthesised and put through P&R.  The output clock also
> looks like it has a 1:4 mark space ratio which suggests it hasn't
> locked.  I have also tried delaying the configuration until the DLL is
> locked and the configuration does take longer but the end result is
> identical.
>
> I am at a bit of a loss for what to try next.
>
> Any suggestions?
>
> Cheers
>
> DG

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20619
Subject: Re: multiplier
From: Ray Andraka <randraka@ids.net>
Date: Wed, 16 Feb 2000 15:35:44 GMT
Links: << >>  << T >>  << A >>
Wallace trees are not generally the fastest multipliers in FPGAs.  See the
multipliers in FPGAs page on my website under the DSP page for more details, as
well as a discussion of various multiplier approaches.

Don McCarley wrote:

> You might want to check out
> http://modgen.fysel.ntnu.no/
> There are Wallace tree multipliers there with pipelining options, these types
> have given me the best results.
>
> Don
>
>
> > Hi,
> >
> > Which would be the best implimentation of a multiplier in VHDL
> > (synthesisable) in terms of speed/area?
> > I know of array implimentation and the ragister configuration using a single
> > adder. Are there any other better ones ?
> > Thanks in anticipation,
> >

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20620
Subject: Re: launching a FPGA cores start-up
From: fpgaer@my-deja.com
Date: Wed, 16 Feb 2000 15:40:49 GMT
Links: << >>  << T >>  << A >>
Ray,

yes, even I'd appreciate if you could let us know these figures ?

Thanks......

In article <38A95836.286B4BED@yahoo.com>,
Rickman <spamgoeshere4@yahoo.com> wrote:
> Ray,
>
> Can you give us some ball park numbers for rates for FPGA designers
and
> for ASIC designers?
>
> Ray Andraka wrote:
> >
> > fpgaer@my-deja.com wrote:
> >
> > > Ray,
> > >
> > > what's the market like for custom FPGA designs (ie; consultancy )
?
> >
> > Right now there is plenty of opportunity for experienced FPGA
designers,
> > although customers are not willing to pay anywhere near what they
are
> > willing to pay for equivalent ASIC designs or experience.
> >
> > >
> > >
> > > In article <38A80ABE.33E78BB5@ids.net>,
> > >   Ray Andraka <randraka@ids.net> wrote:
> > > > My point is that there seems to be very little money in doing
> > > commercial
> > > > cores for FPGAs.  The silicon vendors have set the price point
> > > expectations
> > > > so low (free in many cases) that I suspect you will find little
if any
> > > > return on your investment especially after you factor in the
cost of
> > > > marketing and support.
> > > >
> > > > fpgaer@my-deja.com wrote:
> > > >
> > > > > Ray,
> > > > >
> > > > >
> > > > > I know that the FPGA core market is limited and is dominated
by big
> > > > > vendors. But would I be right in saying that this market is
growing,
> > > > > as the gate/price ratio is increasing (slowly) and with their
> > > > > reconfigurable nature & the time-to-market FPGAs win over
ASICs ?
> > > > > To add to it the 'fabrication-from-foundary' cost factor
attached to
> > > > > ASICs disappears in FPGAs so that individuals can think of
designing
> > > > > complete working systems (an impossible taks when concidering
> > > ASICs).
> > > > > I see scenarios where ONLY FPGA's qualify in terms their
> > > reconfigurable
> > > > > nature - which are increasing by the day !
> > > > >
> > > > > Taking all the pros & cons and reasoning from the above points
( I'm
> > > > > still not sure if they're right ! ), would it be a wise
decision to
> > > > > concentrate on the business ???
> > > > >
> > > > > In article <38A6E467.E85DCE58@ids.net>,
> > > > >   Ray Andraka <randraka@ids.net> wrote:
> > > > > > Good luck.  From what I've seen, people are not willing to
pay
> > > much
> > > > > for
> > > > > > FPGA based cores.  Seems the silicon vendors have set the
price
> > > > > > expectations for cores well below the cost to develop,
maintain
> > > and
> > > > > > support such cores.  Optimized FPGA cores are more difficult
to
> > > design
> > > > > > than comparable cores in ASICs, yet the market price for
FPGA
> > > cores is
> > > > > > orders of magnitude less than similar ASIC cores.
> > > > > >
> > > > > > fpgaer@my-deja.com wrote:
> > > > > >
> > > > > > > Hi,
> > > > > > >
> > > > > > > wld. appreciate if anyone cld. share their views on
launching a
> > > co.
> > > > > > > which delivers custom-made FPGA cores ? Wld. the effort be
worth
> > > in
> > > > > > > terms of time ( & money ) ...... specifically, is there a
> > > demanding
> > > > > > > market for FPGA cores ???
> > > > > > >
> > > > > > > Any comments wld. be highly appreciated !!!
> > > > > > >
> > > > > > > Thanks in advance........
> > > > > > >
> > > > > > > Sent via Deja.com http://www.deja.com/
> > > > > > > Before you buy.
> > > > > >
> > > > > > --
> > > > > > -Ray Andraka, P.E.
> > > > > > President, the Andraka Consulting Group, Inc.
> > > > > > 401/884-7930     Fax 401/884-7950
> > > > > > email randraka@ids.net
> > > > > > http://users.ids.net/~randraka
> > > > > >
> > > > > >
> > > > >
> > > > > Sent via Deja.com http://www.deja.com/
> > > > > Before you buy.
> > > >
> > > > --
> > > > -Ray Andraka, P.E.
> > > > President, the Andraka Consulting Group, Inc.
> > > > 401/884-7930     Fax 401/884-7950
> > > > email randraka@ids.net
> > > > http://users.ids.net/~randraka
> > > >
> > > >
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com
>

Sent via Deja.com http://www.deja.com/

Article: 20621
Subject: Re: clock
From: Dominique SZYMIK <szymik@nospam.univ-lille1.fr>
Date: Wed, 16 Feb 2000 17:03:45 +0100
Links: << >>  << T >>  << A >>
Hello

You may use a circuit like that to get double frequency clock:

----------
-------------------|               |
--- |                            |    XOR   |------------
------\/\/\/\/\-------|               |
R         |     ----------
|
------
------  C
|
|
-----
But to do that reliably you should have a 1/2 mark / space ratio of
original clock.
You may use instead of the RC net delay with buffer gates, but you won't
be able
to tune your mark/ space ratio.
If you don't need a well controlled delay beween clocks, and can tolerate
some
jitter on negative transitions, that will be ok for you.
You don't say much on tolerances and jitter requirements of yours clocks,
so we
may help a bit more.

d.


Article: 20622
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Wed, 16 Feb 2000 11:04:32 -0500
Links: << >>  << T >>  << A >>
I have finally completed my Xilinx SpartanXL design but I need to figure
how to get the file into the PROM.  I am using an AT17LV65-10PC prom.
First question... Can anyone tell me what type of prom to tell the the
PROM file formatter utility that I am using (XC1765D?)  More important,
am I to understand that I should not tell the utility to generate a HEX
file?  My system consists of only the FPGA (XCS05XL-5PC84C) and the prom
(AT17LV65-10PC).  It is intended to automatically load the4 FPGA when
the device powers up.
Thanks,
Theron Hicks


Article: 20623
Subject: Re: Xilinx Virtex Reset
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 16 Feb 2000 16:09:49 +0000
Links: << >>  << T >>  << A >>


Magnus Homann wrote:

> murray@pa.dec.com (Hal Murray) writes:
>
> > Suggestion to vendors:
> >
>
>

Looking at the Virtex data sheet there's a timing parameter for the GSR->IOB/CLB FF
outputs given. For a -4 part its 12.5nsec. The question is whether this includes GSR
routing. If it doesn't its got to be the slowest async reset since LS TTL.


Article: 20624
Subject: Re: A FPGA hickup
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 16 Feb 2000 16:18:18 +0000
Links: << >>  << T >>  << A >>


Magnus Homann wrote:

> Magnus Homann <d0asta@mis.dtek.chalmers.se> writes:
>
> > Hello,
> >
> > One of the FPGA we are using (Xilinx, XCV300) sometimes has a small
> > hickup. I would like to invite your opinion on where I should look
> > first.
> > [...]
>
> Well,
>
> I think we found a probelm with th design. You see, the Xilinx tools
> doesn't want to calculate timing on asynchronous set/reset to clock
> (on FFs). You have to enter some secret command in the .PCF file to
> get this extra feature. Suddenly, our design _didn't_ meet timing
> anymore.
>

I got burned by this one a couple of months ago as well. Its a change
between 1.5i, which checked these paths by default, and 2.1i which
doesn't. I only found it through post route simulation.

Note that this path control flag applies to both synch and async
sets/resets.