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"Benoît HAMON" a écrit : > > Hi, > > I'm trying to implemente (with "FOUNDATION implementation" in a Xilinx > CPLD9500) a function in order to delay an output from an input ?. > > ex : clk_out <= clk_in after 10ns. > I found many VHDL example in Web, but never implemented. This is legal VHDL but it is not synthesizable. It is only used in testbenches to generate stimuli. > NB: my aim is to create a Clock multiplier : 13MHz => 26MHz. > Can someone please give me an example IMPLEMENTED ?. I am no expert but I think a clock multiplier requires some analog electronics (at least a tapped delay line) This might be possible to do by cascading logic cells, each output being a tap. Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCE (j'ecris en anglais pour le forum mais on peut m'ecrire en francais)Article: 20576
Ray, what's the market like for custom FPGA designs (ie; consultancy ) ? In article <38A80ABE.33E78BB5@ids.net>, Ray Andraka <randraka@ids.net> wrote: > My point is that there seems to be very little money in doing commercial > cores for FPGAs. The silicon vendors have set the price point expectations > so low (free in many cases) that I suspect you will find little if any > return on your investment especially after you factor in the cost of > marketing and support. > > fpgaer@my-deja.com wrote: > > > Ray, > > > > Thanks for your comments. > > > > I know that the FPGA core market is limited and is dominated by big > > vendors. But would I be right in saying that this market is growing, > > as the gate/price ratio is increasing (slowly) and with their > > reconfigurable nature & the time-to-market FPGAs win over ASICs ? > > To add to it the 'fabrication-from-foundary' cost factor attached to > > ASICs disappears in FPGAs so that individuals can think of designing > > complete working systems (an impossible taks when concidering ASICs). > > I see scenarios where ONLY FPGA's qualify in terms their reconfigurable > > nature - which are increasing by the day ! > > > > Taking all the pros & cons and reasoning from the above points ( I'm > > still not sure if they're right ! ), would it be a wise decision to > > concentrate on the business ??? > > > > In article <38A6E467.E85DCE58@ids.net>, > > Ray Andraka <randraka@ids.net> wrote: > > > Good luck. From what I've seen, people are not willing to pay much > > for > > > FPGA based cores. Seems the silicon vendors have set the price > > > expectations for cores well below the cost to develop, maintain and > > > support such cores. Optimized FPGA cores are more difficult to design > > > than comparable cores in ASICs, yet the market price for FPGA cores is > > > orders of magnitude less than similar ASIC cores. > > > > > > fpgaer@my-deja.com wrote: > > > > > > > Hi, > > > > > > > > wld. appreciate if anyone cld. share their views on launching a co. > > > > which delivers custom-made FPGA cores ? Wld. the effort be worth in > > > > terms of time ( & money ) ...... specifically, is there a demanding > > > > market for FPGA cores ??? > > > > > > > > Any comments wld. be highly appreciated !!! > > > > > > > > Thanks in advance........ > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > Before you buy. > > > > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email randraka@ids.net > > > http://users.ids.net/~randraka > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20577
You should register the outputs in the IOBs whenever possible. It guarantees clock to output and input setup timing and decouples it from the internal routing. For the internal routing, the clock frequency you are working at and the geographic separation of your outputs will determine how much pipelining or duplication will be required. Pipelining is adding registers to distribute long combinatorial delays over several clock cycles, which allows you to increase the clock rate and overall data rate at the expense of clock latency. Duplication of logic (in this case perhaps two or three identical address counters) can reduce the delays attributed to fan out and long distance routes. Finally, if your design needs sub-multiples of the master clock, you want to use dividers and clock enables to produce the lower rate signals. As far as the floorplanning goes, use it if your design is not meeting timing or is not fitting in the part selected. ritchie99_uk@my-deja.com wrote: > Hi all, > > VIRTEX-E target. > > My design produces 12 parrallel outputs at once > 4 are in the left edge, 4 are in the middle and 4 are in the right at > decreasing rate. > > I have to use only one off-chip bank ram, hoping to succeed to design > the required address generator.... > > i am just wondering what's the appropriate way to route the different > outputs, i mean more precisely how many delays i have to apply to the > left, middle , and the right outputs which will feed my address- > generator > > i am applying timing constraint only, (no placement constraint) > do you think that i have to use the floorplanner, for example, and so > orient by my-self the placement > > any help will be much appreciated > > regards > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20578
Magnus Homann <d0asta@mis.dtek.chalmers.se> writes: > Hello, > > One of the FPGA we are using (Xilinx, XCV300) sometimes has a small > hickup. I would like to invite your opinion on where I should look > first. > [...] Well, I think we found a probelm with th design. You see, the Xilinx tools doesn't want to calculate timing on asynchronous set/reset to clock (on FFs). You have to enter some secret command in the .PCF file to get this extra feature. Suddenly, our design _didn't_ meet timing anymore. So, why do we use asynch. set/reset? Well, Xilinx use them in the FIFO core they provided for our use... A core that the timing tool can't handle, unless told to. A core that the P&R tool can't do timing driven P&R on. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 20579
fpgaer@my-deja.com wrote: > Ray, > > what's the market like for custom FPGA designs (ie; consultancy ) ? Right now there is plenty of opportunity for experienced FPGA designers, although customers are not willing to pay anywhere near what they are willing to pay for equivalent ASIC designs or experience. > > > In article <38A80ABE.33E78BB5@ids.net>, > Ray Andraka <randraka@ids.net> wrote: > > My point is that there seems to be very little money in doing > commercial > > cores for FPGAs. The silicon vendors have set the price point > expectations > > so low (free in many cases) that I suspect you will find little if any > > return on your investment especially after you factor in the cost of > > marketing and support. > > > > fpgaer@my-deja.com wrote: > > > > > Ray, > > > > > > Thanks for your comments. > > > > > > I know that the FPGA core market is limited and is dominated by big > > > vendors. But would I be right in saying that this market is growing, > > > as the gate/price ratio is increasing (slowly) and with their > > > reconfigurable nature & the time-to-market FPGAs win over ASICs ? > > > To add to it the 'fabrication-from-foundary' cost factor attached to > > > ASICs disappears in FPGAs so that individuals can think of designing > > > complete working systems (an impossible taks when concidering > ASICs). > > > I see scenarios where ONLY FPGA's qualify in terms their > reconfigurable > > > nature - which are increasing by the day ! > > > > > > Taking all the pros & cons and reasoning from the above points ( I'm > > > still not sure if they're right ! ), would it be a wise decision to > > > concentrate on the business ??? > > > > > > In article <38A6E467.E85DCE58@ids.net>, > > > Ray Andraka <randraka@ids.net> wrote: > > > > Good luck. From what I've seen, people are not willing to pay > much > > > for > > > > FPGA based cores. Seems the silicon vendors have set the price > > > > expectations for cores well below the cost to develop, maintain > and > > > > support such cores. Optimized FPGA cores are more difficult to > design > > > > than comparable cores in ASICs, yet the market price for FPGA > cores is > > > > orders of magnitude less than similar ASIC cores. > > > > > > > > fpgaer@my-deja.com wrote: > > > > > > > > > Hi, > > > > > > > > > > wld. appreciate if anyone cld. share their views on launching a > co. > > > > > which delivers custom-made FPGA cores ? Wld. the effort be worth > in > > > > > terms of time ( & money ) ...... specifically, is there a > demanding > > > > > market for FPGA cores ??? > > > > > > > > > > Any comments wld. be highly appreciated !!! > > > > > > > > > > Thanks in advance........ > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > > Before you buy. > > > > > > > > -- > > > > -Ray Andraka, P.E. > > > > President, the Andraka Consulting Group, Inc. > > > > 401/884-7930 Fax 401/884-7950 > > > > email randraka@ids.net > > > > http://users.ids.net/~randraka > > > > > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > Before you buy. > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20580
Ray, Can you give us some ball park numbers for rates for FPGA designers and for ASIC designers? Ray Andraka wrote: > > fpgaer@my-deja.com wrote: > > > Ray, > > > > what's the market like for custom FPGA designs (ie; consultancy ) ? > > Right now there is plenty of opportunity for experienced FPGA designers, > although customers are not willing to pay anywhere near what they are > willing to pay for equivalent ASIC designs or experience. > > > > > > > In article <38A80ABE.33E78BB5@ids.net>, > > Ray Andraka <randraka@ids.net> wrote: > > > My point is that there seems to be very little money in doing > > commercial > > > cores for FPGAs. The silicon vendors have set the price point > > expectations > > > so low (free in many cases) that I suspect you will find little if any > > > return on your investment especially after you factor in the cost of > > > marketing and support. > > > > > > fpgaer@my-deja.com wrote: > > > > > > > Ray, > > > > > > > > Thanks for your comments. > > > > > > > > I know that the FPGA core market is limited and is dominated by big > > > > vendors. But would I be right in saying that this market is growing, > > > > as the gate/price ratio is increasing (slowly) and with their > > > > reconfigurable nature & the time-to-market FPGAs win over ASICs ? > > > > To add to it the 'fabrication-from-foundary' cost factor attached to > > > > ASICs disappears in FPGAs so that individuals can think of designing > > > > complete working systems (an impossible taks when concidering > > ASICs). > > > > I see scenarios where ONLY FPGA's qualify in terms their > > reconfigurable > > > > nature - which are increasing by the day ! > > > > > > > > Taking all the pros & cons and reasoning from the above points ( I'm > > > > still not sure if they're right ! ), would it be a wise decision to > > > > concentrate on the business ??? > > > > > > > > In article <38A6E467.E85DCE58@ids.net>, > > > > Ray Andraka <randraka@ids.net> wrote: > > > > > Good luck. From what I've seen, people are not willing to pay > > much > > > > for > > > > > FPGA based cores. Seems the silicon vendors have set the price > > > > > expectations for cores well below the cost to develop, maintain > > and > > > > > support such cores. Optimized FPGA cores are more difficult to > > design > > > > > than comparable cores in ASICs, yet the market price for FPGA > > cores is > > > > > orders of magnitude less than similar ASIC cores. > > > > > > > > > > fpgaer@my-deja.com wrote: > > > > > > > > > > > Hi, > > > > > > > > > > > > wld. appreciate if anyone cld. share their views on launching a > > co. > > > > > > which delivers custom-made FPGA cores ? Wld. the effort be worth > > in > > > > > > terms of time ( & money ) ...... specifically, is there a > > demanding > > > > > > market for FPGA cores ??? > > > > > > > > > > > > Any comments wld. be highly appreciated !!! > > > > > > > > > > > > Thanks in advance........ > > > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > > > Before you buy. > > > > > > > > > > -- > > > > > -Ray Andraka, P.E. > > > > > President, the Andraka Consulting Group, Inc. > > > > > 401/884-7930 Fax 401/884-7950 > > > > > email randraka@ids.net > > > > > http://users.ids.net/~randraka > > > > > > > > > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > Before you buy. > > > > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email randraka@ids.net > > > http://users.ids.net/~randraka > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 20581
I used to do back annotation, but have since found static timing analysis to be much more efficient with the design flows we experience. Too many times I've func simmed, targeted, and back annotated only to have the spec change the next day! Every time you place and route you had to perform back annotated regression sims. Back annotation was causing most of my headache and overtime. With static timing you can specify one set of timing constraints that apply each and every time you reroute. The only caveat is that your static timing analysis had damn well better be right!!! If your analysis is incorrect you can have timing problems even though your constraints are met. I will usually sit down with one or two senior engineers and go through it with a fine tooth comb. It's not a bad way to learn stuff too! I've also found that static timing usually requires more up-front time and effort. I've had some program managers make noise about it while fingering their Gantt chart. They usually quiet down when we get into the lab and have a first-time 'go'. ;-) $0.02 - Craig Gary Spivey wrote: > Actually, let me follow up my question with a more open ended question to > the group - Who out there does do back annotation of timing into the > simulator? How often? Do most people attempt to find these problems with > some sort of on chip debugging practice? Or do most FPGA designers rely on > some form of back annotation? > > How accurate are the static timing analyzers? In a perfect ASIC world, a > designer would use functional verification, static timing analysis, and then > do formal verification to verify the pre and post sysnthesis netlists match > (actually, I assume that some shops actually do this :-). The whole goal of > all of this was to get rid of the backannotated timing simulation. In the > FPGA, it seems to me that the formal verification is done by programming and > running the chip. > > Any thoughts? > > Cheers, > Gary Spivey > spivey@rincon.comArticle: 20582
Hi all, I have a piece of design (Verilog module) that appears many times in my project. To improve the overall density I want to convert it into an area optimized macro. Is there a simple (automatic) way to insert "macro external pins" instead of IOBs in the FPGA Editor ? My synthesizer (Synplify) supports "compile whiteout I/O insertion" but how will know where to connect the "macro external pins". Thanks, ----------------------------------------------- Rotem Gazit mailto:Xrotemg@mysticom.com (remove the X to send me mail.) MystiCom LTD. http://www.mysticom.com ----------------------------------------------- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20583
I use Lattice Synario exclusively. It has VHDL and Verilog and Schematic capture. I use the schematic capture package and have produced several products with it. Paul idezilla@yahoo.com * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 20584
FPGA gurus,
I am trying to fit a design in a Virtex XCV300 (2.5V part).
The Xilinx mapper reports 100% slice utilization, which shocked me.
However, if you do the math on their flop and LUT counts,
(assuming 2 flops and LUTs per slice), the flop and LUT utilizations
are 55% and 76%, repectively, which is what I expected.
The equivalent gate count is ~60K, which isn't that high
(especially since Xilinx claims that 322K system gates can fit in
a XCV300.)
Should I be worried that my slice utilization is 100%?
Why would the mapper choose to use every single slice
if the flop and LUT counts are so low?
The report is given below for reference.
Thanks for any help,
Matt Gavin
mtgavin@collins.rockwell.com
Design Information
------------------
Command Line : map -p xcv300-5-pq240 -o map.ncd mimas_fpga.ngd
mimas_fpga.pcf
Target Device : xv300
Target Package : pq240
Target Speed : -5
Mapper Version : virtex -- C.19
Mapped Date : Mon Feb 14 17:08:18 2000
Design Summary
--------------
Number of errors: 0
Number of warnings: 4
Number of Slices: 3,072 out of 3,072 100%
Slice Flip Flops: 3,408
4 input LUTs: 4,682 (4 used as a route-thru)
Number of Slices containing
unrelated logic: 948 out of 3,072 30%
Number of bonded IOBs: 120 out of 166 72%
Number of GCLKs: 4 out of 4 100%
Number of GCLKIOBs: 3 out of 4 75%
Total equivalent gate count for design: 60,367
Additional JTAG gate count for IOBs: 5,904
Article: 20585murray@pa.dec.com (Hal Murray) writes: > In article <38A8959D.66710000@ids.net>, > Ray Andraka <randraka@ids.net> writes: > > It's only free if it meets timing. I think you'll find that you are past it at > > 74MHz. Even in the 4K parts, GSR was only good up to a fraction of the clock > > rate the part can easily achieve with careful design. Also, the GSR hits every > > single flip-flop in the design, which in some cases can cause you grief > > (especially when you consider the need to resync the reset). > > Suggestion to vendors: > > Please sdd that timing spec to your data sheets. Yes! And please make your tools calculate the reset timing! Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 20586
Hello! What about using the SRL16 component in a Virtex for synching asynch inputs? Good metastability properties? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 20587
In article <38A2E5B2.2136@worldnet.att.net>, Mary Frantz <maryfrantz@worldnet.att.net> wrote: > We have been using Lattice CPLD's (ispLSI1024, ispLSI2064, etc.) in the > past with Synopsis software and are dissatisfied with the performance of > both. Our designs are generally quite simple (glue logic and > registers). Does anyone have a recommendation either for or against > Altera (MAX7000 family) using MAXBaseline or MAXPlus, and Cypress (Ultra > 37000 family) using Warp 5.2? Any known hardware or software prolems? > > Thanks in advance. > Mary Frantz > Mary, I have been using Cypress CPLDs and Warp for several years now. Lately I have been using the Ultra 37000 series exclusively. I have run across a few Warp bugs, but Cypress responded quickly to my e-mail concerning these with a work-around and/or a fix. I am very satisfied with the device performance and with Warp. At about $100 Warp is an excellent value. Charles Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20588
Yes, as far as I know all FPGA vendors PAR tools accept EDIF 2.0.0.Article: 20589
Benoît HAMON wrote in message <88b6gj$du$1@news.entreprises.cegetel.fr>...
>Hi,
>
>I'm trying to implemente (with "FOUNDATION implementation" in a Xilinx
>CPLD9500) a function in order to delay an output from an input ?.
>
>ex : clk_out <= clk_in after 10ns.
>I found many VHDL example in Web, but never implemented.
Well, the construct 'after 10 ns' is ignored for synthesis. RTFM. It's
there.
>NB: my aim is to create a Clock multiplier : 13MHz => 26MHz.
>Can someone please give me an example IMPLEMENTED ?.
Inside an XC9500 part? You can't do it. Period.
Thank you, drive through.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20590Steve Diferdinando wrote: > > Has anyone had trouble with the Virtex DLLs locking? If so, were you > able to find a workaround? > > Steve D. I have recently experienced some problem with DLLs locking on a development board from VCC. The output clock appears to be very jittery and when I've attempted to double up the clock (using the CLK2X output). The code was lifted straight from the Xilinx web site and looks fine when synthesised and put through P&R. The output clock also looks like it has a 1:4 mark space ratio which suggests it hasn't locked. I have also tried delaying the configuration until the DLL is locked and the configuration does take longer but the end result is identical. I am at a bit of a loss for what to try next. Any suggestions? Cheers DGArticle: 20591
Definitely a good primer on FPGA configuration. Allow me to pick a few nits
below:
Rickman wrote:
> The PRGM- signal normally is tied together on all of the FPGAs,
> regardless of the mode you are using to configure them. The main reason
> you would want to make these separate signals is if you want to be able
> to load any of them without loading them all. The PRGM- signal will
> start
> the configuration process when asserted low. The INIT- signal (which
> should be wired together from all FPGAs if using a daisychain config) is
> pulled low by the FPGAs. When PRGM- released high, the FPGAs run through
> at least one more
> config reset cycle and then release INIT-. Because INIT- is open
> collector,
> all chips have to release INIT- for it to go high. If you are
> configuring the FPGAs with separate data and clocks, then the INIT-
> signals can also be separate.
>
> Once INIT- is high, you can start clocking the data out. The CCLK should
> not be clocked by a free running clock. The clock edges are counted by
> the FPGA and
> must match the count contained within the bit file.
>
This is true for the 3000 and 4000 families only. Virtex (and Spartan-II)
do not use a LengthCount, so a free running CCLK is just fine.
>
> There are a lot of details associated with clocking the data. You have
> to supply the right number of clocks without no clocks coming before the
> beginning of the data. Further, you will have to provide some number of
> extra clocks at the end with the data high. This number depends on how
> the bit file
> is specified for the synchonization of the DONE, the internal GSR being
> released, the release of the IO tristate control and the end of the data
> configuration. This is all specified to
> the program that builds the bit file. It is a bit complex. I always use
> the default which I believe uses three extra clocks. I think you can add
> some extra clocks beyond the ones required at the end without hurting
> anything.
>
Absolutely true.
I encourage anyone who feels the documentation is misleading or confusing
in any way to open a case with the hotline. These app notes are written to
explain these concepts without confusion, and can certainly be updated and
changed.
Mike
Article: 20592In article <888t7k$du$1@seagoon.newcastle.edu.au>, mwojko@collpits.newcastle.edu.au (Mathew Wojko) wrote: > Hi, > > Currently I'm migrating/implementing schematic entered designs I > created for the Xilinx XC4000 series. I'm now implementing these on Virtex > devices. However, I'm facing a problem with VCC & GND nets. > > My designs are heirachical and most sheets contain instances of VCC & GND > components. However, when I map these designs to the Virtex architecture > (using Foundation v1.5) I'm getting extremely high CLB slice requirements > due to extensive instances of VCC and GND. It appears that for each sheet > containing a VCC or GND component, when the sheet (or macro created from > it) is implemented, the VCC and GND components are implemented exclusively > to the particular instance of the sheet. > > On viewing the design imlementation using EPIC, it is evident that many > CLB slices are used exclusively to output a logic '0' or '1' for GND or > VCC respectively. > > My question is why is it doing this? When previously using Foundation > v1.4 to implement the same designs on the XC4000 series, I did not come > across this problem. As you could guess, I anticipated similar CLB counts > for implementing the designs on the Virtex architecture, but was > considerably shocked to view the difference in cell counts. > > Is there any way that I can consolidate the VCC and GND nets to reduce > the CLB count? I am aware that if I do this, I may encounter a considerably > longer PWR/GND routing delay. But I am willing to make this tradeoff. > I've searched through DejaNews and queried Xilinx support (with no response) > but have not yet found any answers. > > Can anyone provide any suggestion here? > > Thanks in advance. > > Mathew. > Try this: On one sheet of the design place a single instance of the GND component, connect it to a hanging net, and label the net GND. Wherever you need a ground connection on an input, connect the input to a hanging net labeled GND. Do the same thing for VCC. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20593
This reminds me of a problem I had with an XCV300 DLL which would lock OK when fed a clock from a PLL chip -but not from an XTAL! The Zen 'fix' was to reduce the signal level from the 5V XTAL with a couple of resistors -it took me a while to find it too.. (Also make sure the input frequency is within range for the DLL) Hope this works for you.. ++Simon (remove the anti-spam '_'s in my address to reply..) On Tue, 15 Feb 2000 17:01:46 +0000, david gilchrist <david.gilchrist@NOSPAM.ccom> wrote: >Steve Diferdinando wrote: >> >> Has anyone had trouble with the Virtex DLLs locking? If so, were you >> able to find a workaround? >> >> Steve D. > >I have recently experienced some problem with DLLs locking on a >development board from VCC. The output clock appears to be very jittery >and when I've attempted to double up the clock (using the CLK2X >output). The code was lifted straight from the Xilinx web site and >looks fine when synthesised and put through P&R. The output clock also >looks like it has a 1:4 mark space ratio which suggests it hasn't >locked. I have also tried delaying the configuration until the DLL is >locked and the configuration does take longer but the end result is >identical. > >I am at a bit of a loss for what to try next. > >Any suggestions? > >Cheers > >DGArticle: 20594
Assignment 438
PRODUCT VALIDATION ENG.
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Vancouver BC
Your role will be to develop functional test plans
and
validation boards for the in-depth
validation of our ASSPs. As well, you will
participate
in all phases of the development
process from board definition through testing;
design
circuit boards at the analog and
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methodologies
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Customer Support groups.
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understand that you're the last "gate"
before products are shipped to the customer and take
pride in finding and solving
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with 3 years' applicable
experience in complex board design. Proficient in
analog, digital designs, FPGA,
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and
have knowledge of ATM, Sonet and
frame relay.
TWO POSITIONS AVAILABLE-OTTAWA ON & VANCOUVER BC
Strong or Expert
Technical Skills:ASSP,FPGA,C
Academic or Intermediate
Technical Skills:ATM,SONET,FRAMERELAY
Please respond to meganp@talentlab.com
Article: 20595Hello, i think i have found a bug in xilinx-tool coregen 2.1i. it happens when creating single-port-blockrams with words larger than 16 bit. the resulting ".edn"-file (for synopsys) uses one RAMB4_S16_S16 component where the lower 16 bit of the 24-bit-word are mapped to port A (DOA[15:0]) and the upper 8 bit are mapped to port B (DOA[15:8]). But - and here comes the bug - the address of the desired word is simply mapped to both address-ports (ADDRA and ADDRB (8 bit wide)) the following way: ADDRA(4 downto 0) = myaddress(4 downto 0) ADDRA(7 downto 5) = "000" ADDRB(4 downto 0) = myaddress(4 downto 0) ADDRB(7 downto 5) = "000" The problem is now that always both ports load the same address and with it the same data. The Result is an output which has the form CDABCD where A,B,C,D are hex-ciphers. In application-note XAPP130 (V1.1) is a solution to this problem. The mapping of the address-ports should be: ADDRA(4 downto 0) = myaddress(4 downto 0) ADDRA(7 downto 5) = "000" ADDRB(4 downto 0) = myaddress(4 downto 0) ADDRB(7 downto 5) = "100" Now I am looking for a simple patch. The simples would be a new version of coregen because i am not good in writing ".edn"-files :-(. greetings markArticle: 20596
When the data sheet lists the XCV600E as having an array size of 48x72, is that 48 rows or 48 columns? -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 20597
All, I'm starting to write a VHDL testbench for my VHDL Virtex design. I'm using Orcad release 9.1, but there aren't any Virtex primitive libraries... How are you all simulating the timing of your Virtex designs? Which tools? I've barely look at the Foundation simulator, but I've heard it's not good? thx mArticle: 20598
The smaller number describes the rows, the larger one the columns. Peter Alfke Don Husby wrote: > When the data sheet lists the XCV600E as having an array size of 48x72, > is that 48 rows or 48 columns? > > -- > Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby > Fermi National Accelerator Lab Phone: 630-840-3668 > Batavia, IL 60510 Fax: 630-840-5406Article: 20599
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