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Messages from 22500

Article: 22500
Subject: Re: Hardware TCP/IP stack?
From: Jamil Khatib <jamilkhatib75@yahoo.com>
Date: Wed, 10 May 2000 15:31:49 +0200
Links: << >>  << T >>  << A >>
try to check the opencores organization you ma find some one interested in this
idea and to work with

Jamil Khatib
http://www.opencores.org

Gary Watson wrote:

> I've noticed that there are now a couple of hardware TCP/IP implementations
> around, like the Seiko S7600, and there is a VHDL TCP/IP stack in some IP at
> www.iReady.net.   Does there exist a free or low cost attempt at a TCP/IP
> stack which would fit in a Xilinx FPGA?  I'm thinking in terms of a
> system-on-a-chip web appliance, and/or a high speed NAS processor.
>
> --
>
> Gary Watson
> gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
> Nexsan Technologies Ltd.
> Derby DE21 7BF  ENGLAND
> http://www.nexsan.com

Article: 22501
Subject: Re: ? economical SPROM programmer for Xilinx
From: Hernan Sanchez <hsanchez@egresados.upb.edu.co>
Date: Wed, 10 May 2000 13:52:25 GMT
Links: << >>  << T >>  << A >>
Hi.

I made a simple ATMEL EEPROM Programmer.. you can find it at:

http://members.xoom.com/microele/paralelo/aplicaciones.html

I hope this will help you.

--
Hernán Sánchez
Professor
Universidad Pontificia Bolivariana


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Article: 22502
Subject: Re: ? economical SPROM programmer for Xilinx
From: Ray Andraka <ray@andraka.com>
Date: Wed, 10 May 2000 13:56:57 GMT
Links: << >>  << T >>  << A >>
needham electronics EMP20 is supposed to  do serial EEPROMs.  Before you buy get a
money back guarantee if it doesn't work out.  I have an older version of the
software for it.  It programs the data in a 1701L fine, but doesn't handle the
reset polarity correctly.  It took them a very long time (several months) to get a
patch and that patch didn't work right either.  Perhaps by now they have it fixed.
I haven't turned it on in over a year now.

Emmanuel Lecomte wrote:

> Hello,
>
> You could have a look to http://www.mvd-fpga.com/  -> products -> tiny prog
>
> Greetings,
>
> Emmanuel
>
> Rick Filipkiewicz a écrit :
>
> > Dan wrote:
> >
> > > The Data IO programmers cost $1500ish to program Xilinx SPROM. Does anyone
> > > know of a more reasonably priced one ?
> > >
> > > Thanks Dan
> >
> > If you're in smallish volume why not consider the reprogrammable 1800 series
> > devices from Xilinx. They are JTAG programmable. Once you've got the design
> > stable you could get your SPROM distributor to program one-time ones for you.
> >
> > Alternatively avoid SPROMs altogether & use a standard EPROM+small CPLD to
> > generate the bit stream.

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22503
Subject: ASIC question
From: Yang Li <yang_li1@yahoo.co.uk>
Date: Wed, 10 May 2000 14:31:45 GMT
Links: << >>  << T >>  << A >>
Hello there ,
	I am facing some problem in ASIC packaging . I could not find
the appropriate forum to ask
So I am asking here .

I have a die 5mmx5mm after fab. of 256 pads. But the ASIC packaging
house can not package this due to bonding wire length violations.It can
be done in 208 pin package. So I need to cut down some pads ( keeping
them unconnected and not carrying out them to pins via bonds ) Now
while doing so , I need to cut some power as well as some functional
pads.
The result of this is uneven distribution of power pins on IC ( PQFP
package )
This package has no substrate ( as with BGA ) so that I can have ring
there .

1) What is general ratio of number of power pins to number of
functional pins.

2) Can uneven distribution of power pins be done and still the IC make
work. What I assume is any way inside there is a power ring in die
(ASIC).

2) If I left some of the input PADS open , what will be the effect of
this (The techonology is 0.25 micron CMOS )

3) If I keep some power pads open , what will be the effect.

4) Can the pads be bonded to VDD , VSS inside the package.


Can anyone help

Waiting for your valueable reply.


Please mail a cc to my email address also
yang_li1@yahoo.co.uk

Thanks

Yang Li


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Article: 22504
Subject: Re: Altera Megafunction in Exemplar Leonardo
From: Georg Berliner <gbe@pe.dk>
Date: Wed, 10 May 2000 16:52:01 +0200
Links: << >>  << T >>  << A >>
Quartus ( maxplus )  does not understand the Leonardo-Spectrum's way
for dealing with generics

In order to get it work you must  blackboxing  using attribute instead

 of generics





entity RAM_INST is 
port (clock, we: in bit;
      data : in bit_vector (7 downto 0);
      address: in bit_vector (7 downto 0);
      q: out bit_vector (7 downto 0));
end myram;

architecture arch1 of RAM_INST is


    component RAM_INST_8X8
              port (data: in bit_vector (7 downto 0);
                       address: in bit_vector (7 downto 0);
                       inclock, outclock, we: in bit;
                       q: out bit_vector (7 downto 0) );
    end component;

--  Declare the black_box and parameters and their types

attribute black_box: boolean;
attribute LPM_WIDTH: integer;
attribute LPM_WIDTHAD: integer;
attribute LPM_TYPE: string;


-- Assign values to each attribute

attribute black_box of RAM_INST_8X8: component is true;
attribute LPM_WIDTH of RAM_INST_8X8: component is 8;
attribute LPM_WIDTHAD of RAM_INST_8X8: component is 8; 
-- Specify the name of the LPM function as the value of the 
-- LPM_TYPE attribute
attribute LPM_TYPE of RAM_INST_8X8: component is "LPM_RAM_DQ";

begin
          -- Instantiate the LPM component
          u_ram: RAM_INST_8X8  port map(data, address, clock,
		                                         clock, we,
q); 

end arch1;


For simulation You need  to use generics

--use translate off /on directive to  comment out the generics  for
synthesis.








On Tue, 9 May 2000 09:37:49 +0200, "Thorsten Bunte"
<t.bunte@beckhoff.de> wrote:

>Hi,
>
>I want to use the Megafunction SCFIFO created with Maxplus 2.
>The properties are:
>- width: 1Bit
>- deep: 8
>- both sides are synchronized by one clock
>- outputs: empty
>- asynchronous clear
>- show-ahead synchronous FIFO mode
>
>I am targeting a FLEX6k.
>
>After synthesis in Leonardo I get the message:
>Warning, component scfifo has no visible entity binding.
>
>During place&route the following message appears:
>Warning: Illegal memory cell name "scfifo_1_8_on_on"
>Error: can't find design file "scfifo_1_8_on_on"
>
>If I use only Maxplus 2 everything works fine.
>
>Is it possible to use megafunctions created with MaxPlus 2 any how?
>How can I use these functions with Leonardo?
>
>I hope someone can help me.
>
>Thanks,
>Thorsten
>

Article: 22505
Subject: Re: EETools Topmax
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Wed, 10 May 2000 09:15:25 -0700
Links: << >>  << T >>  << A >>
Long wrote in message ...
>Anyone have any experience with the EETools Topmax universal device
>programmer?

I have the TopMax "Universal Programmer" w/the TM-A48 pod sitting here on my
desk.

>- frequency of software updates: EMP-20 and EMP-30 software last updated
>3/27/200.  Topmax last updated 5/4/200 with at least 3 updates within the
>last two weeks or so when I started researching device programmers.


I think the updates are mostly to add new device support.

>- DOS and Windows support: EMP-20 supports DOS and Windows 95/98, EMP-30
>supports DOS and Windows 9X/NT4/NT2000, Topmax supports DOS and Windows
>9X/NT4/NT2000.  Didn't have any problems running either in a DOS box
>under Windows 98 SE with ECP/EPP printer port mode setting.  EMP-30 has
>Windows version of software but is listed as beta with fewer devices
>support than DOS version.  Topmax also has Windows software version with
>same revision number as DOS software (haven't tried).


I'm using the Windows software on an NT box.

>- software ease of use:  EMP-20 requires manual look-up of devices.
>Topmax can search by typing in a few letters of manufacturer and/or part
>number.  Topmax also supports auto device ID on some devices and testing
>of memory and logic ICs.  Edge goes to Topmax software.


Except the software does not have online help, so figuring out what some of
the features are is a bit of a challenge.  Good luck trying to figure out
how to load a hex-formatted file.  And there's a "config option" dialog
which lets you set the port speed, and it's not obvious why you'd want to
change that option (but see below).

And there are spelling and grammar errors EVERYWHERE.  "Device signature
dose not match."  "The polarity of the Reset/OE pin may be toggle.  Press ok
to make RESET to toggle polarity."  OK, that's picking nits, but I think
that if they can't spell right, can they code correctly?

>- support: Both Needham's and EETools are local Northern California based
>companies.  Did a search of the newgroups with good things said about
>both companies' support.  Both companies answer with a live person when
>calling by phone.  I've sent emails to EETools and got a response within
>a few days.  I haven't requested for a new device support but they both
>seem willing to help.

EEtools willing to help?  Sure, maybe, until you have an actual problem.  It
turns out that we couldn't get the thing to program our parts (Atmel
AT17LV010), and calling their tech support was less than useless.  The woman
who answers the phone must be having a bad YEAR, because another engineer
called there and had the same problem.  This person is arrogant and nasty
and immediately assumes that the problems are the user's fault, regardless
of the details.  So I asked to speak to the "president of the company" and
eventually spoke to someone who still couldn't answer my question.  It turns
out that the port speed had to be reduced to "slow,"  which I discovered by
accident.  Do they test their software?  I don't really think so.  Clearly,
they don't understand how the end-user would actually use the product.

Did I mention the lack of a help file?

Oh, yeah, the 20-pin PLCC-to-DIP deadbug programming adapter shipped with
Pin 1 in the wrong position.

What's funny/sad is that this was the SECOND Topmax box with the same
problem.  They gave us an RMA for the first one, which we sent back, only to
have the second one have the same problems. It costs them money.

I should have sent the goddamn thing back, just on general principles.


-- andy
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke



Article: 22506
Subject: Re: pipeline shiftreg in virtex
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Wed, 10 May 2000 09:18:32 -0700
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote in message <3918666E.A9D2149B@algor.co.uk>...

>For Virtex parts an LUT can be configured as a Shift register in much the
same
>way as it can be configured as a sync. RAM.  See the SRL16xx components in
the
>lib guide.

ah, didn't know that.  neat.  sorry for shootin' my mouth off.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke



Article: 22507
Subject: Re: virtex configuration with synplify
From: chadlamb@my-deja.com
Date: Wed, 10 May 2000 16:45:32 GMT
Links: << >>  << T >>  << A >>
For virtex, there is no need to specify a startup clock to Synplify.
This is done when running bitgen.  This is unlike the XC4000 series
devices.  I know this to be true when using the cclk or jtag tck for
your startup, but I'm unsure about that when using the user clock.

chad


In article <V6pR4.1395$Qf.18285@news2.bora.net>,
  "Ben" <ejhong@future.co.kr> wrote:
> I have a question on using synplify for virtex configuration.
> When I implement and configure virtex design within synplify, there
seems no
> way of choosing a "Startup Clock". To the contrary, in Foundation, we
can
> select a startup clock among "User Clock", "CCLK", and "JTAG Clock".
> Certainly there'll be a way of making a choice, but I cannot find it.
> Will somebody tell me how?
>
> TIA,
>
> Ben
>
>


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Article: 22508
Subject: SpartanXL driving 5V CMOS input
From: "Mark Harvey" <mark.harvey@iol.it>
Date: Wed, 10 May 2000 16:51:25 GMT
Links: << >>  << T >>  << A >>
Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type) input
without any problems, external pullups, etc?



Mark.


Article: 22509
Subject: Re: Hardware TCP/IP stack?
From: cyrilw@my-deja.com
Date: Wed, 10 May 2000 17:08:28 GMT
Links: << >>  << T >>  << A >>


I am interested in it too!But I can't find any information
about it!Please give me some hint.
cyrilw@sina.com
In article <391964C5.CFCCA47D@yahoo.com>,
  khatib@ieee.org wrote:
> try to check the opencores organization you ma find some one
interested in this
> idea and to work with
>
> Jamil Khatib
> http://www.opencores.org
>
> Gary Watson wrote:
>
> > I've noticed that there are now a couple of hardware TCP/IP
implementations
> > around, like the Seiko S7600, and there is a VHDL TCP/IP stack in
some IP at
> > www.iReady.net.   Does there exist a free or low cost attempt at a
TCP/IP
> > stack which would fit in a Xilinx FPGA?  I'm thinking in terms of a
> > system-on-a-chip web appliance, and/or a high speed NAS processor.
> >
> > --
> >
> > Gary Watson
> > gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
> > Nexsan Technologies Ltd.
> > Derby DE21 7BF  ENGLAND
> > http://www.nexsan.com
>
>


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Article: 22510
Subject: Re: SpartanXL driving 5V CMOS input
From: bobperl@best_no_spam_thanks.com (Bob Perlman)
Date: Wed, 10 May 2000 17:19:18 GMT
Links: << >>  << T >>  << A >>
On Wed, 10 May 2000 16:51:25 GMT, "Mark Harvey" <mark.harvey@iol.it>
wrote:

>Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type) input
>without any problems, external pullups, etc?

The logic HIGH input threshold of a true CMOS receiver is ~ 0.7*Vcc,
or about 3.5V if the device is run from a 5V supply.  Driving such an
input from a 3.3V CMOS output is unreliable.  You'll need a pullup or
a level translator.

Bob Perlman

-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 22511
Subject: Re: SpartanXL driving 5V CMOS input
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 10 May 2000 13:20:27 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------19AB8D450D392D40E173840D
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

> Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type) input
> without any problems, external pullups, etc?
>
> Mark.

5V CMOS has a logic threshold around 2.5V.  The Spartan XL data sheet lists the minimum output level for a logic 1 as 2.4V at a current of 4 mA.  The minimum output level goes up to 90% of Vcc (3.0V) if the current is limited to 500 uA.  The second case seems more like what you will encounter with CMOS input circuits, so the answer seems to be yes and you have about 0.5V of margin.  But I have never actually done this.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


--------------19AB8D450D392D40E173840D
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
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Content-Disposition: attachment;
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begin:vcard 
n:Vanden Bout;Dave
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;-16464
fn:Dave Vanden Bout
end:vcard

--------------19AB8D450D392D40E173840D--

Article: 22512
Subject: Re: SpartanXL driving 5V CMOS input
From: Greg Neff <gregneff@my-deja.com>
Date: Wed, 10 May 2000 17:29:56 GMT
Links: << >>  << T >>  << A >>
In article <hsgS4.7106$uk2.82101@news.infostrada.it>,
  "Mark Harvey" <mark.harvey@iol.it> wrote:
> Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type)
input
> without any problems, external pullups, etc?
>
> Mark.
>
>

No.  For example, the minimum high level input voltage for 74AC logic
(Vcc = 5.5V) is 3.85V.  If you don't need speed, then use pseudo open
collector outputs with pullups.  If you need speed, then use a 74ACT
buffer.  If you need very high speed, then you will have to hunt around
for some other solution.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Article: 22513
Subject: Re: pipeline shiftreg in virtex
From: "Gary Spivey" <spivey@ieee.org>
Date: 10 May 2000 12:46:02 -0500
Links: << >>  << T >>  << A >>
Ok,
  I'll bite - I am missing something here. While all of this information is
quite useful (Thank you Ray), what is the real issue? You said that they
need to act as pipeline registers to help break up the long travel time
across the chip. Doesn't the LUT implementation do that? The signals are
being registered ... correct? So obviously I am missing something. Please
clue me in ...

Cheers,
Gary
spivey@ieee.org

"Ray Andraka" <ray@andraka.com> wrote in message
news:39192201.728B434A@andraka.com...
> Synplify infers the SRL16 or SRL16e if there is no reset term.  These, as
> you know, use the LUT as a 16 bit shift register in the VIrtex devices.
> Put a reset term on the shift register to keep it out of the LUT.  If you
> don't use the reset term, connect it to a dummy signal and keep that from
> getting optimized out in synthesis by putting a syn_keep attribute on the
> dummy signal.
>
>
>
> William LenihanIii wrote:
>
> > I have some shift registers in a Xilinx Virtex design and between the
> > synthesis tool (FPGA Compiler II) and the Xilinx Alliance P&R (2.1i), it
> > is placing these shift registers inside the Look-up tables, not in the
> > 'regular' registers in the slices/CLBs -- which is where I need them
> > since they are acting as pipeline registers to help break up the long
> > travel time from one side of the chip to the other -- and forcing them
> > inside a "SRL16" of one CLB isn't going to do that.
> >
> > Is there a way of coaxing the synthesis and/or P&R tool to put shift
> > registers in a resource of the designers' choosing (without manual
> > instantiation of SRL16's vs. FDCE's)?
> >
> > --
> > ========================
> > William Lenihan
> > lenihan3we@earthlink.net
> > ========================
>


Article: 22514
Subject: Re: SpartanXL driving 5V CMOS input
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 10 May 2000 11:36:45 -0700
Links: << >>  << T >>  << A >>
Mark Harvey wrote:

> Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type) input
> without any problems, external pullups, etc?

The answer is: Not reliably, not worst-case.
If you try it in the lab at nominal supply voltages, it will work, but you
don't want to ship it in production.
The output High voltage, when driving a CMOS load is exactly at the 3.3-V
supply, which of course might be as low as 3.0 V. And the 5-V supply might
be at 5.25 V, and the threshold at 70% of that.
It is unlikely that all these conditions come together, but we are
designers, not gamblers.  :-)
So you need a pull-up resistor to Vcc, and you also have to make the
output "open collector", otherwise the upper output transistor (~20 Ohm)
will clamp the Voh to slightly above the 3.3-V Vcc. This purely resistive
pull-up creates a very slow risetime, but there is a remedy:
Control the Spartan tristate with an AND gate that has the internal data
and the output pin as inputs. This results in an active ( low impedance =
fast ) rise time, until the pin voltage reaches about 1.5 V, when it turns
off the output pull-up transistor, and lets the resistor (  470 Ohm or
higher) pull all the way to 5 V.  Adding some internal delay to the AND
gate helps even more. So you can maintain reasonable speed, but you must
use an external resistor.

Peter Alfke, Xilinx Applications

>
>

Article: 22515
Subject: Re: SpartanXL driving 5V CMOS input
From: bobperl@best_no_spam_thanks.com (Bob Perlman)
Date: Wed, 10 May 2000 18:52:05 GMT
Links: << >>  << T >>  << A >>
On Wed, 10 May 2000 13:20:27 -0400, Dave Vanden Bout <devb@xess.com>
wrote:

>> Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type) input
>> without any problems, external pullups, etc?
>>
>> Mark.
>
>5V CMOS has a logic threshold around 2.5V.  The Spartan XL data sheet 
>lists the minimum output level for a logic 1 as 2.4V at a current of 
>4 mA.  The minimum output level goes up to 90% of Vcc (3.0V) if the 
>current is limited to 500 uA.  The second case seems more like what 
>you will encounter with CMOS input circuits, so the answer seems to 
>be yes and you have about 0.5V of margin.  But I have never actually 
>done this.

There's a difference between switching threshold (the 2.5V you
mentioned) and the DC thresholds for logic HIGH and LOW.  For true
CMOS devices, the logic HIGH and LOW DC thresholds are ~0.7*Vcc and
~0.3*Vcc, respectively.  The driving device must be able to drive
higher than the logic HIGH threshold and lower than the logic LOW
threshold to guarantee DC noise margin.

Bob Perlman

-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
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-----------------------------------------------------
Article: 22516
Subject: Re: EETools Topmax
From: "Norm Dresner" <ndrez@attl.net>
Date: Wed, 10 May 2000 19:04:22 GMT
Links: << >>  << T >>  << A >>
Okay, what device programmer would you recommend?

Andy Peters <apeters.Nospam@nospam.noao.edu.nospam> wrote in message
news:8fc25b$g0q$1@noao.edu...
    [SNIP of long Vent against Topmax]


Article: 22517
Subject: Re: pipeline shiftreg in virtex
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 10 May 2000 15:05:46 -0400
Links: << >>  << T >>  << A >>
William is trying to use multiple registers across the chip so that the
delay between each of them is very small. This will allow him to use a
very high clock rate. The LUT implementation puts all of the registers
in one spot so that it only cuts the travel time in half at best. 

This is one of the many problems with using an HDL to synthesize a
design. You spend less time describing a design at the logical level,
but you then spend more time getting the implementation you really want
(assuming you need tight control). In many designs you really don't need
to specify the exact implementation since it is not important or the
tools do a good job. In other cases, the tools have a very hard time
giving you what you really need. 

In this case William has been told that if he specifies the reset
behaviour, he will get the separate registers which he can then place
where he wants them. But the reset code then needs to be documented as
an implementation control so that a future designer does not take it out
and break the design.


Gary Spivey wrote:
> 
> Ok,
>   I'll bite - I am missing something here. While all of this information is
> quite useful (Thank you Ray), what is the real issue? You said that they
> need to act as pipeline registers to help break up the long travel time
> across the chip. Doesn't the LUT implementation do that? The signals are
> being registered ... correct? So obviously I am missing something. Please
> clue me in ...
> 
> Cheers,
> Gary
> spivey@ieee.org
> 
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:39192201.728B434A@andraka.com...
> > Synplify infers the SRL16 or SRL16e if there is no reset term.  These, as
> > you know, use the LUT as a 16 bit shift register in the VIrtex devices.
> > Put a reset term on the shift register to keep it out of the LUT.  If you
> > don't use the reset term, connect it to a dummy signal and keep that from
> > getting optimized out in synthesis by putting a syn_keep attribute on the
> > dummy signal.
> >
> >
> >
> > William LenihanIii wrote:
> >
> > > I have some shift registers in a Xilinx Virtex design and between the
> > > synthesis tool (FPGA Compiler II) and the Xilinx Alliance P&R (2.1i), it
> > > is placing these shift registers inside the Look-up tables, not in the
> > > 'regular' registers in the slices/CLBs -- which is where I need them
> > > since they are acting as pipeline registers to help break up the long
> > > travel time from one side of the chip to the other -- and forcing them
> > > inside a "SRL16" of one CLB isn't going to do that.
> > >
> > > Is there a way of coaxing the synthesis and/or P&R tool to put shift
> > > registers in a resource of the designers' choosing (without manual
> > > instantiation of SRL16's vs. FDCE's)?
> > >
> > > --
> > > ========================
> > > William Lenihan
> > > lenihan3we@earthlink.net
> > > ========================
> >


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22518
Subject: Re: SpartanXL driving 5V CMOS input
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 10 May 2000 15:06:01 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Transfer-Encoding: 7bit



Bob Perlman wrote:

> On Wed, 10 May 2000 13:20:27 -0400, Dave Vanden Bout <devb@xess.com>
> wrote:
>
> >> Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type) input
> >> without any problems, external pullups, etc?
> >>
> >> Mark.
> >
> >5V CMOS has a logic threshold around 2.5V.  The Spartan XL data sheet
> >lists the minimum output level for a logic 1 as 2.4V at a current of
> >4 mA.  The minimum output level goes up to 90% of Vcc (3.0V) if the
> >current is limited to 500 uA.  The second case seems more like what
> >you will encounter with CMOS input circuits, so the answer seems to
> >be yes and you have about 0.5V of margin.  But I have never actually
> >done this.
>
> There's a difference between switching threshold (the 2.5V you
> mentioned) and the DC thresholds for logic HIGH and LOW.  For true
> CMOS devices, the logic HIGH and LOW DC thresholds are ~0.7*Vcc and
> ~0.3*Vcc, respectively.  The driving device must be able to drive
> higher than the logic HIGH threshold and lower than the logic LOW
> threshold to guarantee DC noise margin.

Yes, I agree that you are correct.

I re-read the original question and I see he asks whether it can be done "without any problems".  You can probably get away with it in a lab, but not in production.



>
>
> Bob Perlman
>
> -----------------------------------------------------
> Bob Perlman
> Cambrian Design Works
> Digital Design, Signal Integrity
> http://www.best.com/~bobperl/cdw.htm
> Send e-mail replies to best<dot>com, username bobperl
> -----------------------------------------------------

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


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n:Vanden Bout;Dave
tel;fax:(919) 387-1302
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--------------AEDE1D642C4628788CEABBAB--

Article: 22519
Subject: clock skew doesn't compute with Altera
From: Don McCarley <mccarley@lucent.com>
Date: Wed, 10 May 2000 16:12:33 -0400
Links: << >>  << T >>  << A >>
I get the following error from Quartus when targetting an APEX20K.

---
Error: The 7 path(s) clocked by clock |clk have clock skew larger than
the data delay -- Circuit will not operate. See the fmax report panel
for details.
 Info: Hold Time Violation between |a and |b for clock |clk (Hold Time
is 29 ps)
    Info: + Largest Clock skew is 0.000 ns
       Info: + Longest Clock path from |clk to destination register is
6.500 ns
          Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. =
Unassigned; CLK Node = '|clk'
          Info: 2: + IC(5.000 ns) + CELL(0.100 ns) = 6.500 ns; Loc. =
Unassigned; REG Node = '..'
       Info: - Shortest Clock path from |clk to source register is 6.500
ns
          Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. =
Unassigned; CLK Node = '|clk'
          Info: 2: + IC(5.000 ns) + CELL(0.100 ns) = 6.500 ns; Loc. =
Unassigned; REG Node = '..'
    Info: - Micro clock to output delay of source is 0.100 ns
    Info: - Shortest register to register delay is 0.321 ns
       Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. =
Unassigned; REG Node = '..'
       Info: 2: + IC(0.180 ns) + CELL(0.141 ns) = 0.321 ns; Loc. =
Unassigned; REG Node = '..'
    Info: + Micro hold delay of destination is 0.450 ns
 Warning: Timing requirements were not met. See Report window for
details.
 Info: test_design: Netlist extraction and synthesis were unsuccessful.
1 error, 671 warnings.
---

Now, how can the clock skew (0.000 ns) be larger then the data delay
(0.321 ns)?

I can't add LCELLs because the design is coming from VHDL though a 3rd
party synthesis tool.

I have cliqued blocks with problem paths but this hasn't helped.

Any help is greatly appreciated.

Don



Article: 22520
Subject: Re: appropriate ASIC Prototyping Board
From: Anna Acevedo <acevedo@xilinx.com>
Date: Wed, 10 May 2000 13:47:56 -0700
Links: << >>  << T >>  << A >>
Take a look at the following:

http://www.embedded-solutions.ltd.uk/tech_info_3.htm

http://www.annapmicro.com/

http://www.associatedpro.com/

http://www.vcc.com/prod1.html

Patrick Schulz wrote:

> Hi all,
>
> we are targeting an PCI-based network interface ASIC prototype on VIRTEX1000(E),
> but I found only very few boards which meet our requirements (PCI_64, VIRTEX1000(E)).
> One of this is the DN2000k10 from the Dini Group (http://www.dinigroup.com). The problem
> with this board is, that it is not compatible with the PCI LogicCore from Xilinx and I'm
> not willing to design a PCI-Interface.
>
> Does anyone has experience with this board?
> Does anyone has an idea for a appropriate board??
>
> Thanks Patrick
>
> --
> Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
> University of Mannheim - Dep. of Computer Architecture
> 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
> Phone: +49-621-181-2720     Fax: +49-621-181-2713

--
*****************************
Anna M. Acevedo
Xilinx University Program
2100 Logic Drive
San Jose, CA 95124
PH: (408) 879-5338
FAX: (408) 879-4780

Email: anna.acevedo@xilinx.com
http://www.xilinx.com/programs/univ.htm
*****************************


Article: 22521
Subject: Info on using Reconfig feature of Virtex?
From: "Jim Patterson" <jpatters@stny.rr.com>
Date: Thu, 11 May 2000 00:49:57 GMT
Links: << >>  << T >>  << A >>
Where can I get some info on using the partial reconfiguration (while
powered up) features of the Xilinx Virtex family.  I can't find much on
their site.  I have read that floorplanning is key as the parts only do a
column at a time.  I have never used the floorplanner.  Is it tough?  Design
is in Verilog, using many RPM cores from coregen, including block RAM.
Using the Foundation 2.1i.  Thanks.

--
Jim Patterson
jpatters@stny.rr.com


Article: 22522
Subject: Re: appropriate ASIC Prototyping Board
From: Ray Andraka <ray@andraka.com>
Date: Thu, 11 May 2000 01:05:30 GMT
Links: << >>  << T >>  << A >>
Hi Patrick,

OK, I'll bite:   If you are doing a PCI based network interface in an ASIC, wouldn't you
want control over the PCI interface design too?  The xilinx core is designed to run in the
FPGA, not as an ASIC core.  In fact, I think the license for it says something about
retargeting it doesn't it?

As far as the Dini Board goes, I'm using one for a current project.  Its pretty good for
what it is supposed to be: an ASIC prototyping platform.  If your ASIC is to include the PCI
interface, then you'll most likely want to be doing your own design or buying a suitable
ASIC core.  Besides which, a design targetted at an ASIC is probably not going to run at
full speed in an FPGA.  If your design doesn't include a PCI interface, then Dini Group has
a simple PCI target that works just fine for interfacing to your logic in most cases.

Patrick Schulz wrote:

> Hi all,
>
> we are targeting an PCI-based network interface ASIC prototype on VIRTEX1000(E),
> but I found only very few boards which meet our requirements (PCI_64, VIRTEX1000(E)).
> One of this is the DN2000k10 from the Dini Group (http://www.dinigroup.com). The problem
> with this board is, that it is not compatible with the PCI LogicCore from Xilinx and I'm
> not willing to design a PCI-Interface.
>
> Does anyone has experience with this board?
> Does anyone has an idea for a appropriate board??
>
> Thanks Patrick
>
> --
> Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
> University of Mannheim - Dep. of Computer Architecture
> 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
> Phone: +49-621-181-2720     Fax: +49-621-181-2713

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22523
Subject: Re: SpartanXL driving 5V CMOS input
From: rk <stellare@nospamplease.erols.com>
Date: Wed, 10 May 2000 21:06:49 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Mark Harvey wrote:
>
> > Can a SpartanXL (3.3V) device drive a 5V CMOS (i.e. not ACT type) input
> > without any problems, external pullups, etc?
>
> The answer is: Not reliably, not worst-case.
> If you try it in the lab at nominal supply voltages, it will work, but you
> don't want to ship it in production.
> The output High voltage, when driving a CMOS load is exactly at the 3.3-V
> supply, which of course might be as low as 3.0 V. And the 5-V supply might
> be at 5.25 V, and the threshold at 70% of that.
> It is unlikely that all these conditions come together, but we are
> designers, not gamblers.  :-)

<rk applauds>

----------------------------------------------------------------------
rk                               The Soviets no longer were a threat
stellar engineering, ltd.        in space, and in the terms that
stellare@erols.com.NOSPAM        became commonplace among the veteran
Hi-Rel Digital Systems Design    ground crews, as well as the
                                 astronauts, the dreamers and builders
were replaced by a new wave of NASA teams, bureaucrats who swayed with
the political winds, sadly short of dreams, drive, and determination
to keep forging outward beyond earth.   -- Shepard and Slayton.



Article: 22524
Subject: Re: HELP - what to choose?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 11 May 2000 01:19:18 GMT
Links: << >>  << T >>  << A >>
I stand corrected then.  I simply was not aware of any Lucent based boards that
are commercially available.  I guess the marketing on those is not that great :-)

As far as the gate counts go, I think tailoring the design to the architecture and
floorplanning play a bigger part than the amount of memory.  For example, I've got
a virtex design in a 1000 that uses none of the block RAMs and is still over a
million gates.  There's no way that design would fit without designing it to the
Virtex architecture.  Advertised gate count on the devices is what I call
"marketing gates" which has little bearing on the actual attained gate count.  You
are much better off counting LUTs to determine the size of your design, and by
thinking LUTs you are likely to get to a better design anyway.  Whether you are
counting LUTs or gates, you need a pretty detailed concept of the design to get
anywhere close to an accurate estimate.  I do think the vendors would be more
forthcoming by sizing the parts by number of LUTs than by "gates".  At least that
is not design dependent.

Rickman wrote:

> Hey Ray! What about the PC104C31 which uses not only one, but four
> Lucent FPGA chips? I realize that our price does not fit the $300 limit
> imposed in this case, but don't say there aren't any commercial boards
> around that use the Lucent chip! :)
>
> Of course our board is not really intended to be an FPGA evaluation
> board, but rather a DSP board with FPGA capability. But it is so loaded
> with FPGA capability that anyone needing a lot of FPGA in multiple chips
> would do well to look at it and just consider the DSP to be a fancy boot
> loader. In fact the OR3T30 or OR3T55 that can be used on our board would
> be a very good choice for an attached coprocessor for the TMS320C31 that
> is on the board.
>
> I believe that APS also has a Lucent board much like their APS-X84 board
> although they may not be marketing it. They sent me a board at one point
> as a beta test which I never got around to using.
>
>
> > Andy Holt wrote:
> >
> > > This is the sort of thing I would expect to be an FAQ, but there doesn't
> > > seem to be one for this group.
> > >
> > > I have been thinking about "playing" with an FPGA both from the view of
> > > learning about an interesting-looking technology and with the hope of
> > > constructing an emulation of a '60s mainframe (more about this later).
> > >
> > > I am looking for advice on low-cost ways of doing this (Let's say price
> > > ceiling of about £200 [$300]). It seems that I am going to need two main
> > > things:
> > > * A package of software.
> > > * A prototyping/evaluation board.
> > >
> > > Taking the second of these first there seem to be few choices available
> > > (without paying lots of $$$) -
>
> Our board is a lot of money by comparison. The single piece price I have
> been quoting is between $2000 and $3000 depending on features and speed.
> But this will be changing to something a little more palatable at the
> end of the month. And of course the price is much better at quantity.
>
> ...snip...
> > > As for software, the Kanda and Atmel packages come with some, for the
> > > Xess one I would also have to spend another $100 for the Foundation
> > > student edition.
>
> The PC104C31 comes with a boot monitor program to allow you to program
> the Flash, boot the FPGAs and perform a lot of testing of the various
> parts of the board. Full source is provided along with the designs for
> the FPGAs. A low end package for the Lucent FPGAs is available for $150
> very much like the introductory package from Xilinx. This package
> includes Viewlogic schematic capture and simulation tools. I also
> believe it includes VHDL synthesis.
>
> > > ** so, first question: any known "gotcha's" with the above alternatives?
> > >   [ISTR a recent hint that the Atmel software was weak in one respect -
> > > it is noticeable that their web site seems to say almost nothing about
> > > its functionality - and the low cost version of Foundation doesn't
> > > include VHDL?]
> > > Are there other reasonable options?
> > >
> > > The other main question I have concerns estimating how big an FPGA I
> > > would need for the mainframe emulation. I assume that the "usable gate"
> > > counts for all devices tend to be as much marketing as technical
> > > statements. I have detailed (but only "almost complete") descriptions of
> > > the logic design for the mainframe that I am interested in (ICT 1905 -
> > > aka FP6000) and I can be reasonably confident that it has less than 6000
> > > gates including FPU ... probably less than 4000 without. Is this likely
> > > to fit in a "10000 gate" FPGA?, a "20000 gate" one, or whatever?
>
> Keep in mind that your gate count also needs to include the IO system
> for accessing the memory and any peripherals that will be attached. This
> can easily double the size of the design.
>
> Yes, you are right about the gate counts for the FPGAs. But the largest
> part of the gate inflation comes from the inclusion of memory in the
> gate counts. They make certain assumptions about the percentage of the
> memory used. Your design may use more or less of that memory. This will
> change the used gate count dramatically.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com




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