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Messages from 22600

Article: 22600
Subject: Re: simulation of Xilinx Coregen modules in schematic environment
From: rk <stellare@nospamplease.erols.com>
Date: Fri, 12 May 2000 19:43:20 -0400
Links: << >>  << T >>  << A >>
peter dudley wrote:

> LC,
>
> I'm using adders, block ROM's and multipliers so far. I'll probably use more
> if I can figure out how to simulate them.
>
> Your idea to use the edif netlist for simulation is interesting. Viewlogic
> provides an edif netlist reader called edifneti. Maybe I can use that to get
> a simulateable netlist.

Yes, that will give you a file in the wir subdirectory.  For simulation, you
make a .vsm file the usual way.  If you want to see the logic, you can use
viewgen to make a schematic.  I typically use this path when I want to see what
it is that vhdl synthesizers are up to.

Good luck!

----------------------------------------------------------------------
rk                               The world of space holds vast promise
stellar engineering, ltd.        for the service of man, and it is a
stellare@erols.com.NOSPAM        world we have only begun to explore.
Hi-Rel Digital Systems Design    -- James E. Webb, 1968



Article: 22601
Subject: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
From: Herman <aerosoft@AerospaceSoftware.com>
Date: Sat, 13 May 2000 01:13:07 GMT
Links: << >>  << T >>  << A >>
It was common in Low Dutch some 400 years ago.  I have read some old
manuscripts by the first Govenor of the Cape of Good Hope and it is full
of those things.  My own surname is also a misspelling by a Scottish
priest, but I don't know much about High Dutch or Scandiavian languages.

Jerry Avins wrote:
> 
> Was it always written so, or only when it represented the Dutch ij
> combination? I believe that I remember that Hilda Conrady Kingslake, in
> a biography of her father, implied that y-cum-umlaut was common only in
> words and names originally Dutch. Maybe I remember wrong. (I had a
> colleague at RCA whose name was Miiller. He said that the family name
> was originally Müller, but that some ignoramus at Ellis Island had read
> it wrong.)
> 
> Jerry
> --
> Engineering is the art of making what you want from things you can get.
> -----------------------------------------------------------------------
> Herman wrote:
> >
> > In bygone days, the letter 'y' was written with an umlaut (German -
> > don't know the English for that one) which is two dots on the 'y', which
> > makes it look almost exactly like 'ij', and these characters were in
> > fact equivalent.
> >
> > Jerry Avins wrote:
> > >
> > > Johan Kwisthout wrote:
> > > >
> > > >  ...
> > > >
> > > > It's Dijkstra (turn the i and j the other way around).   ...
> > > >
> > > > >>Johan.
> > >
> > > I remember the order because it looks like the letter "y" (with two
> > > tittles) in script. The great British (later, US) optical designer
> > > Conrady was born Conradij in The Netherlands.
> > >
> > > Jerry
Article: 22602
Subject: Re: HELP - what to choose?
From: "Tony Burch" <tony@BurchED.com.au>
Date: Sat, 13 May 2000 11:46:55 +1000
Links: << >>  << T >>  << A >>

Rickman wrote in message <3918F043.CE521982@yahoo.com>...
>Ray Andraka wrote:
>>
>> If you look at the FPGA architectural features as they apply to a
computer
>> design, I think you'd wind up settling on the Xilinx architectures.
First,
>> you'll probably want a fast carry chain so that you can do fast
arithmetic
>> with minimal logic.  That rules out pretty much everyone except Xilinx,
>> Altera and Lucent.  I haven't seen any commercial boards with Lucent, so
bye
>> bye Lucent.  Xilinx has a capability of using a LUT (a four input look-up
>> table which is the basis of the FPGA architecture) as a small RAM or
shift
>> register.  This makes for very compact register files, pipeline delays,
>> reordering queues etc.  In Altera, each bit of storage chews up another
>> logic element unless you use the buld memories.  Also, Altera's carry
logic
>> structure is not as powerful as the Xilinx structure, which means you
will
>> probably need two levels of logic for real-world arithmetic vs 1 level of
>> logic in Xilinx.
>>
>> If you want it small, you could always go to a bit serial design.  A
pretty
>> decent  bit serial scientific calculator will fit in an XCS-05
>

The BED-XILINX-BASE+ FPGA low cost prototyping board comes with
an XCS-05.  Once you have started your project, if you need
more gates, an XCS-10 will drop straight into the socket
on the board.  Pics, specs etc. at www.BurchED.com.au


>Hey Ray! What about the PC104C31 which uses not only one, but four
>Lucent FPGA chips? I realize that our price does not fit the $300 limit
>imposed in this case, but don't say there aren't any commercial boards
>around that use the Lucent chip! :)
>


Yep.  Also the BED-LUCENT-BASE+ from Burch Electronic Designs.
Low cost, and very much on sale.  We also have kits for
Altera, Actel and Xilinx (mentioned above) at www.BurchED.com.au


>Of course our board is not really intended to be an FPGA evaluation
>board, but rather a DSP board with FPGA capability. But it is so loaded
>with FPGA capability that anyone needing a lot of FPGA in multiple chips
>would do well to look at it and just consider the DSP to be a fancy boot
>loader. In fact the OR3T30 or OR3T55 that can be used on our board would
>be a very good choice for an attached coprocessor for the TMS320C31 that
>is on the board.
>
...snip...
>>
>> The only other low-priced boards available seem to be the Australian
>> ones from Burch Electronic Designs (http://www.burched.com.au) that were
>> recently advertised on this group. However they seem to be very "bare"
>> and more designed for building real-world prototypes than for learning.
>> All versions also come with FPGAs of minimal capacity (almost certainly
>> too small for my "big" project).
>>
...snip...

Andy, you've summed up our products pretty well.  Indeed they
are "bare", specifically for the reason that you mentioned -
they are "for building real-world prototypes".  However,
they are also bought by people who want to learn about
FPGAs, and don't necessarily want a board that has
the usual switches and LEDs arrangement (however
one LED and a canned crystal clock oscillator is
included).


Best regards

Tony Burch
Burch Electronic Designs
www.BurchED.com.au



Article: 22603
Subject: Re: Q: simplest FPGA structure for novel technology demonstration
From: Iain McClatchie <iain@10xinc.com>
Date: Fri, 12 May 2000 19:36:05 -0700
Links: << >>  << T >>  << A >>
Paul,

We've also bumped into the problem of demoing small amounts of
high speed logic.  There appear to be two problems:

(1) everyone else is trying to trade parallelism for speed
    -- and they're doing a good job.
    This rules out FIRs and many kinds of encoder/decoders/filters

(2) Fast algorithms end up needing a lot of state, which turns
    into lots of chip area.  This rules out a practical, small
    processor.

We've generally concentrated on algorithms with some sort of
recurrence relation that can't be eliminated.  Our demos are on
our web page, but basically: Viterbi decode, ALU+Bypass, CRC
calculation, or, my current favorite, DES encrypt/decrypt.  This
last example is wonderful because you spin the basic algorithm
16 times on each block of data, so that your core can run at
least 16 times as fast as your pins.  Better yet, do a triple-DES
encrypt/decrypt, and run your core 48 times as fast as your pins.

If I remember correctly, earlier kinds of superconducting logic
didn't have any decent SRAMs, making the logic useless for most
algorithms since almost everything that goes fast seems to access
a lot of state.  I think this is why I never saw a Josephson
Junction microprocessor.  If you've got dense RAM, even if you
don't have dense gates, then you've got an exciting technology.

So if you really want to blow away a cluey suit, build a 16-bit
RISC with a 4KB instruction RAM and a 4KB data RAM.

Paul> I used to hold the world digital processing speed record -
Paul> 370 GHz T-flip-flop/frequency divider (in 1.5 um tech),
Paul> then another one was designed by a guy in our group running
Paul> at 770 GHz (submicron tech).

Hmm.. why haven't you guys presented at ISSCC?  I certainly would
have enjoyed this stuff more than a few of the papers there.

-Iain McClatchie                            650-364-0520 voice
http://www.10xinc.com                       650-364-0530 FAX
iain@10xinc.com                             650-906-8832 cell
Article: 22604
Subject: Re: Do you know xilinx FPGAs well?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 13 May 2000 03:48:52 GMT
Links: << >>  << T >>  << A >>
He may not need the microcontroller or the memory at all if the design is done
as a hardware processor.  The toen generator and detect circuits are low enough
frequencies that even a bit serial design could be clocked at very low (in terms
of FPGA capabilities) rates.  For example, the TDMA digital cell phone modem TI
provides as an example for their TMS320C50 can be bested by a hardware design in
an XC4013 running at the blistering clock rate of 1.5 MHz (no that's not a
typo), and the FPGA solution does the IQ demodulation from a 4x sample where the
TI example runs at baseband and requires an external demodulator.  The FPGA
solution is also full duplex where the TI solution reciever maxes out a C50
running at full tilt.

In this case it really depends on what he is using the processor for.  If it is
some sort of database management (phone directory or user interface ala newer
cell phones) the processor makes sense to have in there, in which case an
integrated processor and FPAG fabric such as the Triscend part makes alot of
sense.

Joel Kolstad wrote:

> <shahzad2512@my-deja.com> wrote in message
> news:8fglhp$frl$1@nnrp1.deja.com...
> > I have to implement the following:
> > 1. 8032 microcontroller,
> > 2. 64kbytes SRAM,
> > 3. some 8 latches and two 3x8 decoders,
> > 4. 12kHz Generator
> > 5. 16kHz detection
> > 6. DTMF dialer.
> >
> > The above is the customized solution for a telephone set for some
> > telecom company.
>
> Sounds a lot like a homework assignment to me...
>
> > After some initial study, i think that Virtex could give me solution.
> > There is also an A/D converter(which i might need) in the Virtex and
> > such a large memory could only be implemented in an Virtex.
>
> There isn't an A/D converter in a Virtex FPGA, although you can certainly
> build crude ones with just a couple of extra components -- but the same
> thing can be done with a CPU.  In your case, however, at audio frequencies
> you're probably much better off just buying some little ADC chip with
> something like a serial interface that'll plug back into your 8032.
>
> > But then i thought that since Virtex is expensive, this is not a good
> > solution. I thought of SPARTAN II but then SRAM is out.
>
> You're correct, using a Virtex part just to get the 64KB of (block) RAM is a
> very expensive way to go.  If you're bound and determined to use an FPGA, a
> Spartan with a small RISC CPU embedded, 64KB of external SRAM (one IC), an
> external codec containing an ADC, DAC, and companding circuitry, and a
> little bit of analog glue would get you going on the cheap.  But this
> assumes you have the high volumes necessary to justify the development or
> purchase price of a CPU core.  If you don't, the microcontroller alternative
> looks very attractive.  If you're doing this on a small budget and need to
> do it reasonably rapidly (in a matter of months), the 8032 approach is
> definitely going to be a much lower risk approach than the FPGA one.
>
> You need to determine what your "time and money" constraints are to fully
> answer this question.
>
> ---Joel Kolstad

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22605
Subject: Re: pipeline shiftreg in virtex
From: Ray Andraka <ray@andraka.com>
Date: Sat, 13 May 2000 03:55:30 GMT
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:

> Only for us sensible people using Synplify. Do FPGA Express/Compiler &
> Spectrum have equivalent option flags ?

I don't know that! poof as he is flung into the gorge (sorry  Monty
Python on the brain).  I imagine exemplar has a similar switch, but I am
sure the syntax is different (why would we want the tools all using the
same syntax anyway :-)  ) .    I didn't see anything similar in FPGA
express last time I looked.


--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22606
Subject: Re: virtex configuration with synplify
From: "Austin Franklin" <austin@dark88room.com>
Date: 13 May 2000 04:29:51 GMT
Links: << >>  << T >>  << A >>
Just a note...  Unless you want to use GSR or GTS.  For Virtex, if you want
to use the GSR or GTS, Synplify requires you to instantiate the startup
block.  If you do not, the system reset is just routed using regular
routing resources.


chadlamb@my-deja.com wrote in article <8fc3n5$cqm$1@nnrp1.deja.com>...
> For virtex, there is no need to specify a startup clock to Synplify.
> This is done when running bitgen.  This is unlike the XC4000 series
> devices.  I know this to be true when using the cclk or jtag tck for
> your startup, but I'm unsure about that when using the user clock.
> 
> chad
> 
> 
> In article <V6pR4.1395$Qf.18285@news2.bora.net>,
>   "Ben" <ejhong@future.co.kr> wrote:
> > I have a question on using synplify for virtex configuration.
> > When I implement and configure virtex design within synplify, there
> seems no
> > way of choosing a "Startup Clock". To the contrary, in Foundation, we
> can
> > select a startup clock among "User Clock", "CCLK", and "JTAG Clock".
> > Certainly there'll be a way of making a choice, but I cannot find it.
> > Will somebody tell me how?
> >
> > TIA,
> >
> > Ben
> >
> >
> 
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.
> 
Article: 22607
Subject: Altera Schematic
From: "Johan Küstner" <kustner@intekom.co.za>
Date: Sat, 13 May 2000 09:23:06 +0200
Links: << >>  << T >>  << A >>
I'm looking for an example of a schematic for an Altera Flex10K device. I'm
designing a PC board using an EPF10K20RC240-4 device and need an example to
work from. A schematic example of any Flex10K device will suffice as the
pin-outs are basically the same.

--
Regards

Johan F. M. Küstner
Telephone (27) (11) 818-4850
E-mail kustner@intekom.co.za


Article: 22608
Subject: Re: Future of FPGAs?
From: z80@ds2.com (Peter)
Date: Sat, 13 May 2000 08:20:51 +0000
Links: << >>  << T >>  << A >>

>As NRE charges go
>through the roof for high-density ASICs, FPGAs will continue to severely
>erode all but the highest-volume ASIC sockets.

Unless you want low power, in which case an ASIC can give you a 10x +
advantage in dynamic Icc over an FPGA.

>: FPGAs will be used mainly for prototyping and educational environment.
>
>That's a total load of crap.  Ask Cisco.

Not such a good example, because everything they sell is very high
priced, so they can afford it.


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 22609
Subject: SV: foundation
From: "Björn Lindegren" <b.j.l@swipnet.se>
Date: Sat, 13 May 2000 11:07:14 +0200
Links: << >>  << T >>  << A >>
Trie to do an analyse, and then you can do a synthesis. I think the program
can find your errors there.

What kind of errors do you have....

BL


Frank Van de Sande <fvds12@yahoo.com> skrev i
diskussionsgruppsmeddelandet:jO_S4.2201$z%.3329@afrodite.telenet-ops.be...
> hello,
>
> just installed xilinx foundation tool...
>
> when i do a vhdl syntax check, no error report is generated, although
there
> are errors ...
>
>
> Any idea what the problem might be?
>
> thank you
>
> fvds12@yahoo.com
>
>


Article: 22610
Subject: Prom
From: "Björn Lindegren" <b.j.l@swipnet.se>
Date: Sat, 13 May 2000 11:12:07 +0200
Links: << >>  << T >>  << A >>
Hi

Do you know where I can find information about using a microprocessor insted
of  a prom for downloading a program to a Spartan FPGA device?

Thankful for help


Björn Lindegren

University, Trollhättan Sweden


Article: 22611
Subject: Re: virtex configuration with synplify
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sat, 13 May 2000 10:16:30 +0100
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> Just a note...  Unless you want to use GSR or GTS.  For Virtex, if you want
> to use the GSR or GTS, Synplify requires you to instantiate the startup
> block.  If you do not, the system reset is just routed using regular
> routing resources.

You have to be a little careful here. Instantiating the startup block allows
you to control the GSR & GTS nets
but not instantiating it doesn't mean its gone away. Its still there & the GSR
holds all the FFs in reset until a  number of clocks - defined by bitgen -
after the end of configuration. If you want to disable GSR and/or GTS, e.g. you
are prototyping an ASIC, you need to instantiate it & connect the inputs to gnd
via internal nodes or external dummy pins with pulldowns [or maybe just gnd
them, but I'm not sure that this wouldn't get optimised away].

Also, as many people have pointed out, actually using the GSR as your system
reset runs into the problem
of not really knowing the GSR timing. There is a parameter in the Virtex data
sheet called Tgsrq that gives the delay from GSR [I assume this is wrt the
startup clock] to the slice FF outputs. Unfortunately this isn't enough to
determine whether the async GSR will be disasserted in time for the next clock
edge - a requirement for synchronous systems. The best estimate I can come up
with is to assume that the propagation from the GSR input to the slice to the
FF output(s) is the same as the SR input - called Tiosriq - and the GSR input
setup time to the clock is again the same as the SR input Tiosrcki. Putting
these together we have the requirement:

Tclk >=  Tgsrq(max) - Tiosriq(min) + Tiosrcki

Estimating Tiosrq(min) as 1/3 max we get, for a -4 Virtex,

Tclk >= 12.5 - .6 + 1.3 = 13.2 i.e. max system clock freq = 75.7 MHz.

I've asked Xilinx to confirm this estimate but they've not done so.  The most
likely explanation is that they realise having these global functions is
dangerous for large FPGAs used for ASIC prototyping & would like to quietly
drop them.



Article: 22612
Subject: See if this code can work.
From: "Adams" <leezmina@sina.com>
Date: Sat, 13 May 2000 19:43:27 +0800
Links: << >>  << T >>  << A >>
Hi,

I write the following code to achieve a serial communition between PS2
keyboard and fpga. One start bit, 8 bits data, 1 parity, 1 stop.
then change it into parallel.  The problem is not the code did not work(I
know the pdata assignment should not be like this,I should use shift
register structure). I had changed them into a mess.  The confusing thing is
that the synthesizing tool can not recognize my state machine.  And it
ignored KBCLK, and the state variable.

I have tried Xilinx Foundation 2.1i/Fpga Express (use XCS10 LC 84) and
Maxplus 2(use EPM7128sLC84). Neither work.  In maxplus2, CNT8 change from S0
to S1, then S10!! Thean back to S0.  In Fpga Express, I can see the
synthesized schematic, it ignored my KBCLK.

Anyone knows why, please help me.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

ENTITY kbps2 IS
    PORT (
        RESET  : IN STD_LOGIC;
        KBCLK  : IN STD_LOGIC;
        KBDATA : IN STD_LOGIC;
        PDATA  : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
        PARITY : OUT STD_LOGIC;
        temp   : in std_logic;
 TRIG   : BUFFER STD_LOGIC
    );
END kbps2;

ARCHITECTURE ONE OF kbps2 IS
 type Sreg_type is (S0,S1,S2, S3,S4,S5,S6,S7,S8,S9,S10);
 SIGNAL CNT8:SREG_TYPE;
BEGIN
recv:
 process(reset,KBCLK,kbdata)
 begin
 if reset='1' then
  cnt8<=S0;
 elsif (KBCLK'event and KBCLK='1') then
   case cnt8 is

   when S0=>
    if kbdata='0' then
     cnt8<=S1;
    else
     cnt8<=S0;
    end if;
   when S1=>
    cnt8<=S2;
   when S2=>
    cnt8<=S3;
   when S3=>
    cnt8<=S4;
   when S4=>
    cnt8<=S5;
   when S5=>
    cnt8<=S6;
   when S6=>
    cnt8<=S7;
   when S7=>
    cnt8<=S8;
   when S8=>
    cnt8<=S9;
   when S9=>
    cnt8<=S10;

   when S10=>
    if kbdata='1' then
     cnt8<=S0;
    else
     cnt8<=S10;
    end if;

   when others=>
    null;
  end case;
 end if;
end process recv;

pdata(0)<=kbdata when cnt8=s1 else '0';
pdata(1)<=kbdata when cnt8=s2 else '0';
pdata(2)<=kbdata when cnt8=s3 else '0';
pdata(3)<=kbdata when cnt8=s4 else '0';
pdata(4)<=kbdata when cnt8=s5 else '0';
pdata(5)<=kbdata when cnt8=s6 else '0';
pdata(6)<=kbdata when cnt8=s7 else '0';
pdata(7)<=kbdata when cnt8=s8 else '0';

parity<=kbdata   when cnt8=s9 else '0';

trig<='1' when (cnt8=s10)else '0';

END ONE;


BR
Adams Lee


Article: 22613
Subject: New Robot info and general news site
From: "Don Golding" <dgolding@angelusresearch.com>
Date: Sat, 13 May 2000 15:22:01 -0000
Links: << >>  << T >>  << A >>
Check it out at:

http://www.angelusresearch.com/ResearchCentral.htm



Article: 22614
Subject: Re: Prom
From: dave_bernard@my-deja.com
Date: Sat, 13 May 2000 20:54:38 GMT
Links: << >>  << T >>  << A >>
In article <909T4.1551$JL6.5148@nntpserver.swip.net>,
  "Björn Lindegren" <bjorn.lindegren@home.se> wrote:
> Hi
>
> Do you know where I can find information about using a microprocessor
insted
> of  a prom for downloading a program to a Spartan FPGA device?
>
> Thankful for help
>
> Björn Lindegren
>
> University, Trollhättan Sweden
>
>

Here's a link to Xilinx appnote section that describes how to program
the FPGA's via an embedded microcontroller/processor.

  http://www.xilinx.com/xapp/xapp058.pdf

Regards,

  Dave


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22615
Subject: Re: Altera Schematic
From: "Adams" <leezmina@sina.com>
Date: Sun, 14 May 2000 09:16:14 +0800
Links: << >>  << T >>  << A >>
Do you have an Altera Data Book?
It contains everything you need.
The file about flex10k is ds\dsk10k.pdf

Adams

Johan Küstner wrote in message <8fivnh$stt$1@ctb-nnrp2.saix.net>...
>I'm looking for an example of a schematic for an Altera Flex10K device. I'm
>designing a PC board using an EPF10K20RC240-4 device and need an example to
>work from. A schematic example of any Flex10K device will suffice as the
>pin-outs are basically the same.
>
>--
>Regards
>
>Johan F. M. Küstner
>Telephone (27) (11) 818-4850
>E-mail kustner@intekom.co.za
>
>


Article: 22616
Subject: Re: New Robot info and general news site
From: Tom Burgess <tom.burgess@home.com>
Date: Sun, 14 May 2000 08:45:20 GMT
Links: << >>  << T >>  << A >>
I looked and looked on your site but could not find a reference to
this inspirational essay which activates my photoreceptor cleansing
subroutines each time I access it:

http://www.theonion.com/onion3522/robots_are_the_future.html

regards, tom

Don Golding wrote:
> 
> Check it out at:
> 
> http://www.angelusresearch.com/ResearchCentral.htm
Article: 22617
Subject: Bidirectional BUS!!!
From: "J. Boss" <jboss@wxs.nl>
Date: Sun, 14 May 2000 14:50:15 +0200
Links: << >>  << T >>  << A >>
Hi,

Why is it so diffucult to design a bidirectional bus in Foundation 2.1i?
This what I've designed using Schematic:

                                        /|
                                      /  |
  IOPAD___D[15:0]__/    |____DOUT[15:0]                                DOUT
is internally seperated into DOUT[15:8] and DOUT[7:0]
                        |           \    |
                        |            |\  |OBUFE16
                        |            |  \|
                        |            |______RW
                        |
                        |           |\
                        |           |  \
                        |_____ |    \____DIN[15:0]
                                    |    /
                                    |  /IBUF16
                                    |/

I've tried to simulate this. When I put data on D[15:0], data is also
visible on DIN[15:0]. But when I put data on DOUT[15:0] and activate RW,
there's no data visible on D[15:0]. I also get warning messages, when
starting the simulator:

Warning: unconnected input and output pins detected
Unconnected output pin: D1 ($I1)
Unconnected output pin: D10 ($I1)
Unconnected output pin: D11 ($I1)
Unconnected output pin: D12 ($I1)
Unconnected output pin: D13 ($I1)
Unconnected output pin: D14 ($I1)
Unconnected output pin: D15 ($I1)
Unconnected output pin: D2 ($I1)
Unconnected output pin: D3 ($I1)
Unconnected output pin: D4 ($I1)
Unconnected output pin: D5 ($I1)
Unconnected output pin: D6 ($I1)
Unconnected output pin: D8 ($I1)
Unconnected output pin: D9 ($I1)

This has something to do with my problem. But what can I do about it? I've
tried several ways, but I can't find any solution. Could anyone help me?


Jurjen


Article: 22618
Subject: Re: Bidirectional BUS!!!
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 14 May 2000 10:44:49 -0400
Links: << >>  << T >>  << A >>
I don't know exactly what is wrong. This should work fine. BTW, when you
try using ASCII art, you need to use a monospaced font, not a
porportional one. I took the liberty of fixing your diagram for this.

I would suggest that you go into the netlist and see just what is
connected to what. If you are using the Aldec schematic editor, I know
that there are some issues with busses. So verify what is connected to
what on D[15:0] and see if you can find anything odd in the schematic.
For example, maybe you have a 'O' (letter oh) instead of a '0' (zero) in
one of the labels. 



"J. Boss" wrote:
> 
> Hi,
> 
> Why is it so diffucult to design a bidirectional bus in Foundation 2.1i?
> This what I've designed using Schematic:
> DOUT is internally seperated into DOUT[15:8] and DOUT[7:0]
> 
>                        /|
>                      /  |
>   IOPAD___D[15:0]__/    |____DOUT[15:0]                                
>        |           \    |
>        |            |\  |OBUFE16
>        |            |  \|
>        |            |______RW
>        |
>        |      |\
>        |      |  \
>        |_____ |    \____DIN[15:0]
>               |    /
>               |  /IBUF16
>               |/
> 
> I've tried to simulate this. When I put data on D[15:0], data is also
> visible on DIN[15:0]. But when I put data on DOUT[15:0] and activate RW,
> there's no data visible on D[15:0]. I also get warning messages, when
> starting the simulator:
> 
> Warning: unconnected input and output pins detected
> Unconnected output pin: D1 ($I1)
> Unconnected output pin: D10 ($I1)
> Unconnected output pin: D11 ($I1)
> Unconnected output pin: D12 ($I1)
> Unconnected output pin: D13 ($I1)
> Unconnected output pin: D14 ($I1)
> Unconnected output pin: D15 ($I1)
> Unconnected output pin: D2 ($I1)
> Unconnected output pin: D3 ($I1)
> Unconnected output pin: D4 ($I1)
> Unconnected output pin: D5 ($I1)
> Unconnected output pin: D6 ($I1)
> Unconnected output pin: D8 ($I1)
> Unconnected output pin: D9 ($I1)
> 
> This has something to do with my problem. But what can I do about it? I've
> tried several ways, but I can't find any solution. Could anyone help me?
> 
> Jurjen


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22619
Subject: Re: Altera Schematic
From: "Johan Küstner" <kustner@intekom.co.za>
Date: Sun, 14 May 2000 19:34:01 +0200
Links: << >>  << T >>  << A >>
I can't seem to get what I require from the Altera Data CD (January 2000). I
need to see and example. This isn't available on the CD, so it seems, unless
I'm missing something.

--
Regards

Johan F. M. Küstner
Telephone (27) (11) 818-4850
E-mail kustner@intekom.co.za
Adams <leezmina@sina.com> wrote in message
news:8fkubq$5ne$1@news.cz.js.cn...
> Do you have an Altera Data Book?
> It contains everything you need.
> The file about flex10k is ds\dsk10k.pdf
>
> Adams
>
> Johan Küstner wrote in message <8fivnh$stt$1@ctb-nnrp2.saix.net>...
> >I'm looking for an example of a schematic for an Altera Flex10K device.
I'm
> >designing a PC board using an EPF10K20RC240-4 device and need an example
to
> >work from. A schematic example of any Flex10K device will suffice as the
> >pin-outs are basically the same.
> >
> >--
> >Regards
> >
> >Johan F. M. Küstner
> >Telephone (27) (11) 818-4850
> >E-mail kustner@intekom.co.za
> >
> >
>
>


Article: 22620
Subject: Re: Altera Schematic
From: vsundaram@my-deja.com
Date: Sun, 14 May 2000 21:45:03 GMT
Links: << >>  << T >>  << A >>
There are a few schematic examples on Altera's website at
http://www.altera.com/html/atlas/examples/ged/ged.html.

Also there is a complete tutorial called CHIPTRIP included with
MAX+PLUS2 software that you can use as a schematic reference. It should
be in one of the MAXPLUS2 subdirectories or MAX2WORK sub directories.

Vikram

In article <8fivnh$stt$1@ctb-nnrp2.saix.net>,
  "Johan Küstner" <kustner@intekom.co.za> wrote:
> I'm looking for an example of a schematic for an Altera Flex10K
device. I'm
> designing a PC board using an EPF10K20RC240-4 device and need an
example to
> work from. A schematic example of any Flex10K device will suffice as
the
> pin-outs are basically the same.
>
> --
> Regards
>
> Johan F. M. Küstner
> Telephone (27) (11) 818-4850
> E-mail kustner@intekom.co.za
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22621
Subject: Re: Do you know xilinx FPGAs well?
From: vsundaram@my-deja.com
Date: Sun, 14 May 2000 21:52:05 GMT
Links: << >>  << T >>  << A >>
Have you considered using a 10k130E device from Altera. May not be as
expensive as Virtex and has about memory as well. In fact if memory is
not enough on this chip then there is a 10K200E as well.

Vikram


In article <8fglhp$frl$1@nnrp1.deja.com>,
  shahzad2512@my-deja.com wrote:
> I have to implement the following:
> 1. 8032 microcontroller,
> 2. 64kbytes SRAM,
> 3. some 8 latches and two 3x8 decoders,
> 4. 12kHz Generator
> 5. 16kHz detection
> 6. DTMF dialer.
>
> The above is the customized solution for a telephone set for some
> telecom company.
>
> After some initial study, i think that Virtex could give me solution.
> There is also an A/D converter(which i might need) in the Virtex and
> such a large memory could only be implemented in an Virtex.
>
> But then i thought that since Virtex is expensive, this is not a good
> solution. I thought of SPARTAN II but then SRAM is out.
> What do u thing and suggest.
> Any comments........?
> Thanks and Regards,
> SHAH
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22622
Subject: Re: HELP - what to choose?
From: vsundaram@my-deja.com
Date: Sun, 14 May 2000 22:02:13 GMT
Links: << >>  << T >>  << A >>
If you are a member of staff at a university you will definitely get
the university package. All you need to do is send an email to
support@altera.com and someone will contact you.

Since the university board has a 10K20 device you have about 20,000
gates. In addition you get memory on the chip too.

As for the tools, the university package comes with the basic MAX+PLUS2
tool, but it is an old version 9.2 or something.

Altera gives free versions of its basic software called Baseline which
can be downloaded from their website. But these have limited device
support, but I think 10k20 is supported. Also this does not have VHDL
or Verilog synthesis capability, but Altera also gives free synthesis
software - FPGA Express, Leonardo Spectrum which can be again
downloaded from their website.

Thus the University Board + Free Baseline + Free Synthesis tools should
be the best combination.

Regards,
Vikram

In article <391822B5.77D0CAD6@city.ac.uk>,
  Andy Holt <andyh@city.ac.uk> wrote:
> This is the sort of thing I would expect to be an FAQ, but there
doesn't
> seem to be one for this group.
>
> I have been thinking about "playing" with an FPGA both from the view
of
> learning about an interesting-looking technology and with the hope of
> constructing an emulation of a '60s mainframe (more about this later).
>
> I am looking for advice on low-cost ways of doing this (Let's say
price
> ceiling of about £200 [$300]). It seems that I am going to need two
main
> things:
> * A package of software.
> * A prototyping/evaluation board.
>
> Taking the second of these first there seem to be few choices
available
> (without paying lots of $$$) -
>
> The most obvious seems to be the XS40 from Xess using the Xilinx 4000
> series devices. (http://www.xess.com)
>
> Less expensive with more features on board is the Atmel FPGA Starter
Kit
> from Kanda (http://www.kanda.com)
>
> If I qualify for the special deal (I am a member of staff at a
> University), the Altera Design Laboratory Package looks very
> attractively priced - if I can't get the deal it is likely to be too
> expensive. (http://www.altera.com)
>
> The only other low-priced boards available seem to be the Australian
> ones from Burch Electronic Designs (http://www.burched.com.au) that
were
> recently advertised on this group. However they seem to be very "bare"
> and more designed for building real-world prototypes than for
learning.
> All versions also come with FPGAs of minimal capacity (almost
certainly
> too small for my "big" project).
>
> As for software, the Kanda and Atmel packages come with some, for the
> Xess one I would also have to spend another $100 for the Foundation
> student edition.
>
> ** so, first question: any known "gotcha's" with the above
alternatives?
>   [ISTR a recent hint that the Atmel software was weak in one
respect -
> it is noticeable that their web site seems to say almost nothing about
> its functionality - and the low cost version of Foundation doesn't
> include VHDL?]
> Are there other reasonable options?
>
> The other main question I have concerns estimating how big an FPGA I
> would need for the mainframe emulation. I assume that the "usable
gate"
> counts for all devices tend to be as much marketing as technical
> statements. I have detailed (but only "almost complete") descriptions
of
> the logic design for the mainframe that I am interested in (ICT 1905 -
> aka FP6000) and I can be reasonably confident that it has less than
6000
> gates including FPU ... probably less than 4000 without. Is this
likely
> to fit in a "10000 gate" FPGA?, a "20000 gate" one, or whatever?
>
> More questions later :-)
>
> Andy Holt
> Systems Consultant
> City University
> London, England
> andyh@city.ac.uk
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22623
Subject: Re: Do you know xilinx FPGAs well?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 14 May 2000 19:00:54 -0400
Links: << >>  << T >>  << A >>
shahzad2512@my-deja.com wrote:
> 
> I have to implement the following:
> 1. 8032 microcontroller,
> 2. 64kbytes SRAM,
> 3. some 8 latches and two 3x8 decoders,
> 4. 12kHz Generator
> 5. 16kHz detection
> 6. DTMF dialer.
> 
> The above is the customized solution for a telephone set for some
> telecom company.
> 
> After some initial study, i think that Virtex could give me solution.
> There is also an A/D converter(which i might need) in the Virtex and
> such a large memory could only be implemented in an Virtex.
> 
> But then i thought that since Virtex is expensive, this is not a good
> solution. I thought of SPARTAN II but then SRAM is out.
> What do u thing and suggest.
> Any comments........?
> Thanks and Regards,
> SHAH

I don't have pricing at my fingertips, but I don't think you will have a
cost effective solution with any FPGA that can implement 64 K bytes of
SRAM. I would suggest that you use a low end DSP chip and implement the
tone generators and detectors in sofware. These algorithms have been
done many times before and are not terribly hard to do. 

If you use something like a TMS320LF2407 (under $15 in quantity), a 64K
x 16 SRAM and a small CPLD you will have everything you need plus
support circuitry. The CPLD will provide the bit IO and the SRAM will
round out the memory requirements. The DSP chip comes with a 2 MSPS 10
bit ADC and PWM to use as a DAC. 

If the 10 bit ADC and PWM DAC are not good enough, then you can use a
DSP without these options and add a codec to the serial port for another
$3. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22624
Subject: Re: Do you know xilinx FPGAs well?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 14 May 2000 19:06:15 -0400
Links: << >>  << T >>  << A >>
Rickman wrote:
> 
> shahzad2512@my-deja.com wrote:
> >
> > I have to implement the following:
> > 1. 8032 microcontroller,
> > 2. 64kbytes SRAM,
> > 3. some 8 latches and two 3x8 decoders,
> > 4. 12kHz Generator
> > 5. 16kHz detection
> > 6. DTMF dialer.
> >
> > The above is the customized solution for a telephone set for some
> > telecom company.
> >
> > After some initial study, i think that Virtex could give me solution.
> > There is also an A/D converter(which i might need) in the Virtex and
> > such a large memory could only be implemented in an Virtex.
> >
> > But then i thought that since Virtex is expensive, this is not a good
> > solution. I thought of SPARTAN II but then SRAM is out.
> > What do u thing and suggest.
> > Any comments........?
> > Thanks and Regards,
> > SHAH
> 
> I don't have pricing at my fingertips, but I don't think you will have a
> cost effective solution with any FPGA that can implement 64 K bytes of
> SRAM. I would suggest that you use a low end DSP chip and implement the
> tone generators and detectors in sofware. These algorithms have been
> done many times before and are not terribly hard to do.
> 
> If you use something like a TMS320LF2407 (under $15 in quantity), a 64K
> x 16 SRAM and a small CPLD you will have everything you need plus
> support circuitry. The CPLD will provide the bit IO and the SRAM will
> round out the memory requirements. The DSP chip comes with a 2 MSPS 10
> bit ADC and PWM to use as a DAC.
> 
> If the 10 bit ADC and PWM DAC are not good enough, then you can use a
> DSP without these options and add a codec to the serial port for another
> $3.

I missed the fact that the TMS320LF2407 has 40 bits of general purpose
IO, so the CPLD can be dropped and you have basically a two chip
solution (plus reset...).


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com


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