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Messages from 21300

Article: 21300
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: "Jared Church" <jaredc@icpdd.neca.nec.com.au>
Date: Thu, 16 Mar 2000 11:25:03 +1100
Links: << >>  << T >>  << A >>
So basically what we are all saying here is that there is no real separation
between these and the name is usually defined by the manufacturer as opposed
to strictly fitting in any guidlines as to the structure and other physical
characteristics of the devices ?

jc



Article: 21301
Subject: SpartanXL Express mode configuration
From: krw@attglobal.net (Keith R. Williams)
Date: 16 Mar 2000 03:52:12 GMT
Links: << >>  << T >>  << A >>

Ok, after wrestling with the *very* poor documentation in the 
Xilinx databook, I searched their site and found a relevant app 
note (why not include usefull information in the databook?).  Ok,
so I've made the several changes to the board already, because of
poor documentation, that's a done deal - I hope (yellow-wires are
a part of the job).  The documentation on how to do express mode 
files is also very poor and took me a few days to find.  ...yes, 
I'm working from the GUI until I find my way around.  I *think* I
have this one covered, at least the log files say I've generated 
an express-mode file.  

I have a very simple micro (8051 type) driving the express mode 
pins on this beast.  Even the app-note isn't clear here (timing 
diagrams of the pins would be nice).  Can I do the express mode 
programming at any speed, right down to single-stepping the 
controller with an ICE?  I know now what I'm doing wrong, but I 
don't want to blow another day loooking at what I "know" to be 
correct.

Thanks, for any pointers here.

----
  Keith  


Article: 21302
Subject: PCI Synthesis Question
From: Yang Li <yang_li1@yahoo.co.uk>
Date: Thu, 16 Mar 2000 04:03:03 GMT
Links: << >>  << T >>  << A >>
I know that PCI SIg mailing list is the best forum to raise this
question but I could not get any answers from there.
 So I am posting it here  . Please help


I have a design which is to be targeted to ASIC.

This design has synthesized with 66 Mhz PCI constraint. Timings are not
met with a slack of approx -4 ns
I gave worst case constraints from PCI side. and best case synthesis
cell selection options(timingwise)
As the code changes will take a lot time again to simulate, I have
another quick option
I am sure that this design will work on 33 Mhz clock.

Now what method I am following is
1) Synthesis with 66 Mhz constraint with worst case PCI delays. Let the
logic be generated with max efforts.
2) Generate timing reports for 66 Mhz , 33 Mhz . ( Ofcource 66 mhz will
fail. )
3) Target it to ASIC. with a facility on board made for 33 Mhz, 66 Mhz.
( PCI66EN and Config space bit reset from board jumpers ).
4) Assume that PCI chipset will give me best timings ( If I put the
card nearer to chipset ), I will give a try on 66 Mhz enable via board
jumpers.


Is this method appropriate ? What I am assuming is bus will not give me
worst timings.



Thanks in advance
Yang Li
yang_li1@yahoo.co.uk



Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21303
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 16 Mar 2000 04:33:14 GMT
Links: << >>  << T >>  << A >>


Jared Church wrote:

> So basically what we are all saying here is that there is no real separation
> between these and the name is usually defined by the manufacturer as opposed
> to strictly fitting in any guidlines as to the structure and other physical
> characteristics of the devices ?
>

That is much too harsh. This technology is evolving fast, and nobody has time
to wait for a standardization institute.

But look:
 There is no debate about what a PAL and even a PLA is.
 Everybody agrees that something that looks like multiple PALs on a chip is
called a CPLD, ( Even Altera seems to abandon the name CPLD for their FPGA ).
 And devices with a less rigid logic structure, more like typical ASICs, are
called FPGAs, whether they are SRAM or antifuse based ( even a lonely EPROM
based one ).

I would not call call that "no real separation"

The names are not based on technology, but rather on logic and interconnect
structures. And that is an excellent choice. IMHO

Peter Alfke


Article: 21304
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: Kevin Dale Kirmse <kirmse@netaxs.com>
Date: Thu, 16 Mar 2000 00:04:54 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> David Frith wrote:
>
> > Neglected to say that the interconnects in an FPGA are usually switched by
> > storing a '1' or a '0' in an SRAM cell whilst in a CPLD they are controlled
> > by a made or blown fuse (which may or may not be electrically erase-able).
> > FPGA's need their SRAMs loading each time they are powered-up (called
> > configuration) whilst CPLDs keep their program even when powered off. There
> > are advantages and disadvantages of both ways of doing things.
> >
> > David
>
> Here are a few corrections:
> FPGAs are not all SRAM-based. Actel and Quicklogic use anifuses, and they also
> do not use LUT-based logic.
>
> Altera likes to use the name CPLD for their SRAM- and LUT-based FPGAs, but
> that's for obscure  political reasons.
>
> PLD i generally used as a generic name for all programmable logic, including
> CPLDs and FPGAs
>
> Simple AND-OR based designs were introduced as, and are still called, PALs.
> They generally do not use fuses anymore, but rather CMOS EPROM cells for
> programming them,
>
> All modern CPLDs are now EEPROM or Flash-based and thus
> in-system-programmable.
>
> Peter Alfke, Xilinx Applications

Some of the larger parts in the Xilinx CoolRunner CPLD family are SRAM based.
Their internal structure looks to be more like an array of PALs than the more
complex internals of FPGA's



---------------------------------------------------------------------
| Dr. Kevin Dale Kirmse, PhD EE
| Portable System Design, High Speed Serial Links
| FPGA Design, Video Hardware, Graphics Hardware
|
| King of Prussia, PA 19406
| kirmse@netaxs.com
---------------------------------------------------------------------


Article: 21305
Subject: question for virtex
From: =?EUC-KR?B?wNPA58iv?= <jhlim@telpia.com>
Date: Thu, 16 Mar 2000 14:19:43 +0900
Links: << >>  << T >>  << A >>
Hi!

I have  some question for xilinx FPGA (virtex:XCV300-5-FG456).
Now, I design ATM function using this FPGA and Foundation 2.l.
I read the "READBACK" function of this chip from data sheet.
My question is following.
To make use of readback function for this chip(XCV300-5-FG456), What
equipment do I need and How much money I need  to buy the equipment?

I want to set  registers and memory element in FPGA as what I want  any
time
and investigate the value of registers and memory  in FPGA in runtime.
Can ReadBack function match my desire?

Thank you for reading my question

Article: 21306
Subject: Xilinx 6200 devices?
From: "Peter Sutton" <p.sutton@mailbox.uq.edu.au>
Date: Thu, 16 Mar 2000 16:11:26 +1000
Links: << >>  << T >>  << A >>
Does anyone know if XC6200 series devices can be obtained anywhere anymore?
The Xilinx University Program told me no, I'm just wondering if there are
any out there to be had.

(I have a senior project student who wanted to try some Silicon Evolution
experiments and an architecture which won't blow up with a random bit-stream
and lets you work backwards to a design is kind of useful.)

Thanks,
Peter
--
Dr Peter Sutton
Department of Computer Science and Electrical Engineering
The University of Queensland


Article: 21307
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 16 Mar 2000 06:44:26 GMT
Links: << >>  << T >>  << A >>


Kevin Dale Kirmse wrote:

> Some of the larger parts in the Xilinx CoolRunner CPLD family are SRAM based.
> Their internal structure looks to be more like an array of PALs than the more
> complex internals of FPGA's
>

CoolRunners are CPLDs because they have a PAL-derived logic and interconnect
structure. They store their configuration in on-chip EEPROM and are thus
non-volatile, just like all other CPLDs. Very consistent.

Most modern CPLDs, although they are EEPROM or Flash-based, transfer some of the
configuration bits from the EEPROM area internally into latches, distributed all
over the chip.
The largest CPLD manufacturer strangely never admits this (why?), but it is common
practice. XC9500 never made a secret out of it ( why should we?) Coolrunner just
uses shadow SRAM cells for all configuration.
IMHO this is the wave of the future.

Peter Alfke, Xilinx Applications


Article: 21308
Subject: Re: Xilinx 6200 devices?
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 16 Mar 2000 06:46:46 GMT
Links: << >>  << T >>  << A >>
Sorry, Xilinx is sold out. I tried previously and could not dig up any parts.
And I have a bit of clout...
Peter Alfke
===============================
Peter Sutton wrote:

> Does anyone know if XC6200 series devices can be obtained anywhere anymore?
> The Xilinx University Program told me no, I'm just wondering if there are
> any out there to be had.
>
> (I have a senior project student who wanted to try some Silicon Evolution
> experiments and an architecture which won't blow up with a random bit-stream
> and lets you work backwards to a design is kind of useful.)
>
> Thanks,
> Peter
> --
> Dr Peter Sutton
> Department of Computer Science and Electrical Engineering
> The University of Queensland

Article: 21309
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: "Alasdair MacLean" <nojunk@gecm.com>
Date: Thu, 16 Mar 2000 08:41:22 -0000
Links: << >>  << T >>  << A >>

JaeYong Kim wrote in message <006ucssuqv358olp893qesagof13ar5oue@4ax.com>...
>What is the difference between FPGA, PLD, CPLD ?
>they are all programmable chip. what is different ?
>

Have a look at the FAQ on the Optimagic web pages for a good description.

http://www.optimagic.com/faq.html#CPLD

Alasdair MacLean,
Senior Development Engineer,
BAE Systems,
Sensor Systems Division,
Silverknowes,
Edinburgh.


Article: 21310
Subject: Re: SystemC vs. VHDL
From: Bingfeng Mei <bennet@imec.be>
Date: Thu, 16 Mar 2000 11:35:41 +0100
Links: << >>  << T >>  << A >>
SystemC is only a specification tool at present. You only can simulate it.
No tool support
synthesis from a SystemC specification.

dulik@dcse.fee.vutbr.cz wrote:

> Hello,
>
> anybody heard about the SystemC ? I am a VHDL designer with a knowledge
> of C++ programming. What do you think SystemC would bring me ? I
> studied the specification and VHDL seems to be much more convenient as
> a HW specification language... Do you have any example of a case where
> the SystemC specification would bring some advantages in the design
> flow ?
>
> Best regards,
> Tomas Dulik
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Article: 21311
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: rk <stellare@nospam.erols.com>
Date: Thu, 16 Mar 2000 06:26:35 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Kevin Dale Kirmse wrote:
>
> > Some of the larger parts in the Xilinx CoolRunner CPLD family are SRAM based.
> > Their internal structure looks to be more like an array of PALs than the more
> > complex internals of FPGA's
> >
>
> CoolRunners are CPLDs because they have a PAL-derived logic and interconnect
> structure. They store their configuration in on-chip EEPROM and are thus
> non-volatile, just like all other CPLDs. Very consistent.
>
> Most modern CPLDs, although they are EEPROM or Flash-based, transfer some of the
> configuration bits from the EEPROM area internally into latches, distributed all
> over the chip.
> The largest CPLD manufacturer strangely never admits this (why?), but it is common
> practice. XC9500 never made a secret out of it ( why should we?) Coolrunner just
> uses shadow SRAM cells for all configuration.
> IMHO this is the wave of the future.

Hi Peter,

Very interesting topic.  Is the Coolrunner's use of SRAM to store configuration during
operation documented anywhere so I can read up on it a bit more?  I did look
specifically for this when I was designing a board [day job] although I might have
missed it.

Thanks in advance,

rk

Article: 21312
Subject: Re: Xilinx 6200 devices?
From: "Daryl Bradley" <dwb105@nospam.ohm.york.ac.uk>
Date: Thu, 16 Mar 2000 13:27:28 -0000
Links: << >>  << T >>  << A >>
You can now do evolution with the Virtex
If you get hold of Jbits for Virtex you can do all the evolutionary
processes in JAVA  - and make sure the bit streams are valid before they are
downloaded.

Peter Alfke <palfke@earthlink.net> wrote in message
news:38D08376.95DFB62C@earthlink.net...
> Sorry, Xilinx is sold out. I tried previously and could not dig up any
parts.
> And I have a bit of clout...
> Peter Alfke
> ===============================
> Peter Sutton wrote:
>
> > Does anyone know if XC6200 series devices can be obtained anywhere
anymore?
> > The Xilinx University Program told me no, I'm just wondering if there
are
> > any out there to be had.
> >
> > (I have a senior project student who wanted to try some Silicon
Evolution
> > experiments and an architecture which won't blow up with a random
bit-stream
> > and lets you work backwards to a design is kind of useful.)
> >
> > Thanks,
> > Peter
> > --
> > Dr Peter Sutton
> > Department of Computer Science and Electrical Engineering
> > The University of Queensland
>


Article: 21313
Subject: Re: Virtex DLL inoperability
From: David Gilchrist <david.gilchrist@NOSPAM.com>
Date: Thu, 16 Mar 2000 14:04:24 +0000
Links: << >>  << T >>  << A >>
> I have recently experienced some problem with DLLs locking on a
> development board from VCC.  The output clock appears to be very >jittery

>Steve, do you have the latest Service Pack (which is SP4).
>
>Xilinx had a DLL problem in Service Pack 3 (or 2? I dont recall).
>
>Marco

It turned out to be a problem with the place and route tool (Service
Pack 3 surprisingly enough).  The P & R tool was corrupting the bits
during BitGen. When this was updated the problem magically disappeared.

I suppose that'll teach me to pay more attention to previous postings!

Cheers

DG
Article: 21314
Subject: Actel Design with A42MX36 Help
From: Andrew batchelor <andrew.batchelor@gecm.com>
Date: Thu, 16 Mar 2000 14:28:11 +0000
Links: << >>  << T >>  << A >>
Dear All

I am a hardware engineer down in Rochester, and I am having great
problems fitting a design to a 42MX36. The problem is that I would like
my design to run at 55 MHz across the full mil temp range. There is one
section of an 8 bit bus which I cannot get to go fast enough. Has anyone
got any ideas on how to improve the fitting performance, or how I could
increase the speed of the system. Also does any one know what type of
algorithm they use to place and route, say Genetic Algorithm or some
other process for optimization?

Andy

Article: 21315
Subject: Re: Xilinx 6200 devices?
From: Bingfeng Mei <bennet@imec.be>
Date: Thu, 16 Mar 2000 16:31:42 +0100
Links: << >>  << T >>  << A >>
Where can I find information about JBit? I searched the Xilinx's website, and
got some pieces of message. But they are so simple and out-of-date.
Daryl Bradley wrote:

> You can now do evolution with the Virtex
> If you get hold of Jbits for Virtex you can do all the evolutionary
> processes in JAVA  - and make sure the bit streams are valid before they are
> downloaded.
>
> Peter Alfke <palfke@earthlink.net> wrote in message
> news:38D08376.95DFB62C@earthlink.net...
> > Sorry, Xilinx is sold out. I tried previously and could not dig up any
> parts.
> > And I have a bit of clout...
> > Peter Alfke
> > ===============================
> > Peter Sutton wrote:
> >
> > > Does anyone know if XC6200 series devices can be obtained anywhere
> anymore?
> > > The Xilinx University Program told me no, I'm just wondering if there
> are
> > > any out there to be had.
> > >
> > > (I have a senior project student who wanted to try some Silicon
> Evolution
> > > experiments and an architecture which won't blow up with a random
> bit-stream
> > > and lets you work backwards to a design is kind of useful.)
> > >
> > > Thanks,
> > > Peter
> > > --
> > > Dr Peter Sutton
> > > Department of Computer Science and Electrical Engineering
> > > The University of Queensland
> >

Article: 21316
Subject: Atmel A29 Series Software Erase
From: jodoan@my-deja.com
Date: Thu, 16 Mar 2000 16:08:45 GMT
Links: << >>  << T >>  << A >>
I currently have a few Wyse Winterm 2315SE's which incorporate the
Atmel AT29C020 12JC EEPROM.  My question is this:  we flashed the chip
with Citrix ICA 2.80 client and would like to flash these back to
2.70.  For some reason the image will not take.  I would like to start
with a clean slate.  I checked out Atmel's website and they say the
AT29 series chips are software erase only using a 6 byte software
algorithm.  However, I am not a programmer nor do I know enough about
how these chips really work to ask someone to create that program for
me.  I was wondering if anyone has encountered this problem before and
if they knew where I could possibly get the software to erase this
chip.  Or possibly knew anything about the jumpers on the Winterm that
will erase the software.  Or even if they knew if these are somehow
electronically eraseable.  Please respond to jdoan@acs.roadway.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21317
Subject: Xilinx configuration current
From: Peter <peterc@hmgcc.gov.uk>
Date: Thu, 16 Mar 2000 16:17:26 +0000
Links: << >>  << T >>  << A >>
Has anyone got an idea of what current to expect when a 4010E Xilinx
begins configuration?

Using a watchdog IC to reset the Xilinx I am experiencing an increase of
150mA when the device begins configuration (this is while the PROGRAM
input is low in master serial mode). 

I can't find any of the dedicated pins that are driving as outputs in
conflict with external inputs (the address pins are not outputs in
master serial mode are they? - I can't find that for sure in the
databook but seem to be weak pull-ups). At this point the Xilinx should
be clearing it's memory so an increase might be expected, but 150mA
seems a lot. Has anyone else noticed this and can confirm that this is
expected, or can someone confirm that this is excessive?

The increase also occurs in slave serial mode if PROGRAM is taken low.

Anyone any ideas that I may not have explored?
-- 
Peter Crighton
Article: 21318
Subject: Is there a Xilink PCI or ISA demo board with external connector?
From: "Gary Watson" <gary@nexsan.sex>
Date: Thu, 16 Mar 2000 16:17:54 -0000
Links: << >>  << T >>  << A >>
I'm looking for a Xilinx (will settle for Altera) demo board which plugs
into a ISA or PCI slot, but where all the remaining I/O pins are brought out
to a connector leading outside the PC chassis.  The board would only need
the one chip on it, I figure, with the PC bus hooked up directly to the
FPGA.  Don't think I need any RAM or other glue logic.

If I can't find one, I'm going to make one myself.  Anybody else want one?
I was going to use a part in the 20,000 to 40,000 gate region, like the 4000
series.  I'll probably include A/D inputs on all external pins since this
would improve it for my intended project.

My purpose is twofold: (a) to learn how to use the Xilinx FPGA software, and
(b) to use this gizmo to test SCSI backplane electronics including Low
Voltage Differential terminators.   (Parenthetical quesiton -- does anybody
know of the LVDS I/O pads in the Xilinx are close enough to the SCSI LVD
specification for crude testing purposes?  SCSI uses an asymmetric variant
of LVDS.)

--

Gary Watson
gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
http://www.nexsan.com





Article: 21319
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: Kevin Dale Kirmse <kirmse@netaxs.com>
Date: Thu, 16 Mar 2000 11:22:17 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Kevin Dale Kirmse wrote:
>
> > Some of the larger parts in the Xilinx CoolRunner CPLD family are SRAM based.
> > Their internal structure looks to be more like an array of PALs than the more
> > complex internals of FPGA's
> >
>
> CoolRunners are CPLDs because they have a PAL-derived logic and interconnect
> structure. They store their configuration in on-chip EEPROM and are thus
> non-volatile, just like all other CPLDs. Very consistent.
>
> Most modern CPLDs, although they are EEPROM or Flash-based, transfer some of the
> configuration bits from the EEPROM area internally into latches, distributed all
> over the chip.
> The largest CPLD manufacturer strangely never admits this (why?), but it is common
> practice. XC9500 never made a secret out of it ( why should we?) Coolrunner just
> uses shadow SRAM cells for all configuration.
> IMHO this is the wave of the future.
>
> Peter Alfke, Xilinx Applications

I brought the subject up because the original statement had been

"All modern CPLDs are now EEPROM or Flash-based and thus
in-system-programmable."

The XCR3320 and XCR3360 appear to lack the Nonvolatile
configuration of the smaller CoolRunner parts.

---------------------------------------------------------------------
| Dr. Kevin Dale Kirmse, PhD EE
| Portable System Design, High Speed Serial Links
| FPGA Design, Video Hardware, Graphics Hardware
|
| King of Prussia, PA 19406
| kirmse@netaxs.com
---------------------------------------------------------------------


Article: 21320
Subject: Re: Xilinx configuration current
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 16 Mar 2000 12:55:03 -0500
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> Has anyone got an idea of what current to expect when a 4010E Xilinx
> begins configuration?
> 
> Using a watchdog IC to reset the Xilinx I am experiencing an increase of
> 150mA when the device begins configuration (this is while the PROGRAM
> input is low in master serial mode).
> 
> I can't find any of the dedicated pins that are driving as outputs in
> conflict with external inputs (the address pins are not outputs in
> master serial mode are they? - I can't find that for sure in the
> databook but seem to be weak pull-ups). At this point the Xilinx should
> be clearing it's memory so an increase might be expected, but 150mA
> seems a lot. Has anyone else noticed this and can confirm that this is
> expected, or can someone confirm that this is excessive?
> 
> The increase also occurs in slave serial mode if PROGRAM is taken low.
> 
> Anyone any ideas that I may not have explored?
> --
> Peter Crighton

I have not dragged the data book out, but I seem to remember that the
configuration clearing does start when you pull -PRGM low. Then when you
release -PRGM to a high, the FPGA finishes the current config clear
cycle and then does one more. The address lines are not active in Master
Serial mode. 

I can't tell you if 150 mA is normal or not, I don't think I have ever
measured it. I know that FPGAs in general do take a bit of power as Vcc
ramps. At least I know that in the Lucent parts. They give you a
specific caution about power supplies that can't provide enough current
as the power comes up. If you don't have enough juice as Vcc crosses a
threshold, the parts can go into la la land. I don't know for sure if
the Xilinx parts work the same way. 

But if you are reprogramming via a watchdog, the power up is not the
problem. Isn't there anything on this in the data book? I would expect
this number to be documented. But then I guess it can depend on the
mode. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21321
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 16 Mar 2000 10:08:00 -0800
Links: << >>  << T >>  << A >>


Kevin Dale Kirmse wrote:

>
> The XCR3320 and XCR3360 appear to lack the Nonvolatile
> configuration of the smaller CoolRunner parts.
>

Yes. Any broad-brush statement seems to have an exception:

The (Philips-originated, now Xilinx ) high-end CPLDs with 320 and 960 mrocells are
indeed SRAM-based only, no EEPROM on-board.

The correct part numbers are XCR3320 and XCR3960 ( Xilinx CoolRunner 3volt 960
macrocells)

Peter Alfke, Xilinx Applications

Article: 21322
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 16 Mar 2000 18:58:59 GMT
Links: << >>  << T >>  << A >>
I can't say I entirely agree with you on the distinctions between FPGAs and
CPLDs.  First, while many FPGAs are SRAM based, that is not a defining
quality.  For example, Actel and Quicklogic FPGAs are both antifuse
one-time-programmables.  I think perhaps what you were trying to say is that
you though FPGAs used small look-up tables to implement the logic.  While it is
true that many FPGAs use look-up tables (LUTs) as the logic resource (Xilinx
Altera 10K, Lucent Atmel40K for example), but there are may examples of FPGAs
that use a gate structure instead...Atmel 6K, Quicklogic, Actel all come to
mind.

The distinction is a structure issue though.  First let's define PLDs, as the
definition of CPLDs falls out of that.  PLDs refer to programmmable devices
that have a fairly wide and-or array (sometimes with extra features) feeding
the outputs either directly or through flip-flops.  These are differentiated
from CPLDs in that the and-or array is complete so that all inputs are
available to each product term.  You can imagine that the switch matrix gets
pretty big quickly.  Older devices programmed the switch matrix by blowing
fuses to break connections.  More modern devices use eprom or eeprom, and a few
use sram cells to control pass transistor switches.  The volatility or
construction of the switches is not a defining attribute.

A CPLD is an integration of several PLD like structures onto a single chip.
SInce a complete switch matrix is too big, the chip is partitioned into a
number of 'megacells' each of which is essentially a PLD.  THose are
interconnected by a relatively sparse switch matrix.  This leads conceptually
to a structure where the logic surrounds a switch fabric.  Both the CPLD and
PLD have a relatively small number of flip flops compared to the combinatorial
logic, and both are well suited to logic with wide fanins.   PLDs typically
have less than 2 dozen flip flops.  CPLDs may have several hundred in the
larger devices.  Often the flip-flops in these devices are associated with I/O
pins.

An FPGA is generally considered to have smaller logic cells distributed as
islands in the switch fabric.   The cells tend to have smaller combinatorial
functions, so the ratio of flip-flops to logic is much higher.  FPGAs have
anywhere from around 100 to over 10,000 flip-flops.

David Frith wrote:

> JaeYong Kim <jaelong@lge.co.kr> wrote in message
> news:006ucssuqv358olp893qesagof13ar5oue@4ax.com...
> > What is the difference between FPGA, PLD, CPLD ?
> > they are all programmable chip. what is different ?
> >
>
> FPGA - Field Programmable Gate Array - uses SRAM to achieve simple logic
> functions and then interconnects these simple logic functions to generate
> much more complex functions. A 4 bit SRAM memory would need 2 address lines
> and one data line. If the address:data stored was
> 00:0
> 01:0
> 10:0
> 11:1
> the function being mimicked would be a 2 input AND. Similarly if the
> address:data stored was
> 00:0
> 01:1
> 10:1
> 11:1
> a 2 input OR would be realised. Cascade several of these basic cells, and
> larger functions can be realised. Add some registers as well and it is
> possible to pipeline data changes and form synchronous state machines etc.
> The Xilinx Virtex and Spartan devices and Altera Flex devices are examples
> of FPGAs.
>
> PLD - Programmable Logic Devices - use arrays of AND gates followed by OR
> gates. For example the 22V10 device has many wide input AND gates for up to
> 22 inputs. The output of these AND gates can be selectively routed to wide
> input OR gates, so if a logic function can be described in AND/OR notation,
> it could be implemented in a PLD. They can also contain registers.
>
> CPLD - Complex Programmable Logic Devices - connect several PLD arrays as
> described above together by a switch matrix allowing even larger logic
> functions to be realised. Lattice ISP devices and Vantis MACH devices are
> examples of CPLDs.
>
> Hope That Helps (HTH)
>
> David

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21323
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: gerald coe <devantech@devantech.demon.co.uk>
Date: Thu, 16 Mar 2000 20:33:52 +0000
Links: << >>  << T >>  << A >>
In article <38D082CD.78BD60FD@earthlink.net>, Peter Alfke
<palfke@earthlink.net> writes
>CoolRunners are CPLDs because they have a PAL-derived logic and interconnect
>structure. They store their configuration in on-chip EEPROM and are thus
>non-volatile, just like all other CPLDs. Very consistent.
>
>Most modern CPLDs, although they are EEPROM or Flash-based, transfer some of the
>configuration bits from the EEPROM area internally into latches, distributed all
>over the chip.
>The largest CPLD manufacturer strangely never admits this (why?), but it is 
>common
>practice. XC9500 never made a secret out of it ( why should we?) Coolrunner just
>uses shadow SRAM cells for all configuration.
>IMHO this is the wave of the future.
>
>Peter Alfke, Xilinx Applications
>
>

Is there any chance of future FPGA's having on-chip configuration
EEPROM/Flash? IMHO, this would be a great plus, especially if it powered
down after configuration.
   
-- 
Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031,
Gerald Coe      | .demon.co.uk    | 68302, 64180, 80C188EB cpu modules. 
http://www.devantech.demon.co.uk  | Full custom uP control systems designed.
Article: 21324
Subject: Re: Xilinx configuration current
From: Greg Neff <gregneff@my-deja.com>
Date: Thu, 16 Mar 2000 20:46:10 GMT
Links: << >>  << T >>  << A >>
In article <38D10916.7265@hmgcc.gov.uk>,
peterc@hmgcc.gov.uk wrote:
> Has anyone got an idea of what current to expect when a 4010E Xilinx
> begins configuration?
>
> Using a watchdog IC to reset the Xilinx I am experiencing an increase
of
> 150mA when the device begins configuration (this is while the PROGRAM
> input is low in master serial mode).
>
> I can't find any of the dedicated pins that are driving as outputs in
> conflict with external inputs (the address pins are not outputs in
> master serial mode are they? - I can't find that for sure in the
> databook but seem to be weak pull-ups). At this point the Xilinx
should
> be clearing it's memory so an increase might be expected, but 150mA
> seems a lot. Has anyone else noticed this and can confirm that this is
> expected, or can someone confirm that this is excessive?
>
> The increase also occurs in slave serial mode if PROGRAM is taken low.
>
> Anyone any ideas that I may not have explored?
> --
> Peter Crighton
>

We have seen the same thing.  I suppose that during initialization and
configuration you can think of the FPGA as an N-bit shift register,
with N being the number of configuration bits.  While PROGRAM is low,
the FPGA is repetitively clearing all of these configuration latches.
The data sheet says that the clear process uses the internal
oscillator, so the clear process must be synchronous.  If my hypothesis
is correct, this would be the equivalent of clocking N latches at the
CCLK rate, for the length of time that PROGRAM is low, plus the
configuration time.  Clocking a few hundred thousand latches at the
CCLK rate will definitely warm things up.

It doesn't look like the FPGA will use an external CCLK while PROGRAM
is low.  Otherwise, you could slow down CCLK (using slave serial mode
as you said) to reduce current consumption during initialization.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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