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andrew_f66@my-deja.com escribió: > > I'm a student doing my final year project. My > task is to build a sinusoidal PWM generator on an > FPGA to control an induction motor. I have been > told I have to digitally compare a sine wave with > the triangular modulating wave to produce the > PWM. My problem is how to generate the digital > values for the sine wave. > > Someone suggested programming an EEPROM with sine > wave values, but this doesn't seem very flexible > to me. Can anyone think of a better way of > generating the Sine wave (Or anything else > helpful?) > > Sent via Deja.com http://www.deja.com/ > Before you buy. Hi, You can use the sine wave table as suggested, but maybe a 64 word table for 0º to 90º is not too much for the FPGA (just 2 CLB/bit), and you compute the other angles based on it. Surely the induction motor will not see the (low) resolution you use. Cheers, Santiago.Article: 26501
On Wed, 18 Oct 2000 10:21:36 +0200, Marc Reinert <reinert@tu-harburg.de> wrote: >Has anybody a good solution to connect a ADC (e. g. AD9054A 200Ms / I've >got a free sample:-) to a Virtex-E FPGA. > >I'm sorry, I've no concept of the analog part of my circuit. Do I have >to put a amplifier etc. in front of my analog input. > >Has anybody a made a similar design? > >I'll be happy if anybody has some useful hints - thank U > >Marc > What is this a Homework assignment ? If you can't look at the datasheet and assorted app notes and figure it out for yourself. You deserve to fail Return Email Address is: ralphwat dot home at excite dot comArticle: 26502
Thank You, really good example circuit. I'll see if it'll help me to devise good ideas. Furthermore I hope it was not a to big strain for You. Marc Newsbrowser schrieb: > What is this a Homework assignment ? > > If you can't look at the datasheet and assorted app notes and figure > it out for yourself. You deserve to fail > > Return Email Address is: > ralphwat dot home at excite dot comArticle: 26503
Xilinx has a cute little app note on how to make a sigma/delta DAC on a Virtex. Has anyone tried using this with a small comparitor circuit to make a low sample rate ADC? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 26504
Ray Andraka a écrit : > > They do pull up outside the part, but they are too weak to be > considered a reliable pullup for additional pins tied to the net. Use > an external pull-up if you have other components on the net. (the > Virtex pull up value is in the 100's of K ohms). That's what I thought a moment later Besides, the current must be sourced by the FPGA if another driver is low. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.IPricot.com/Article: 26505
I'd like to implement the fastest possible binary counter in a Spartan II. Is the counter produced by coregen the fastest possible, or is there a way to improve on what coregen comes up with? Has anyone been able to buy a Spartan II device? FindChips.com doesn't find anything for XC2S. Paul SmithArticle: 26506
eml@riverside-machines.com.NOSPAM wrote: > On Sat, 14 Oct 2000 11:12:09 +0100, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > > >Jonas Thor wrote: > > > >> Hello! > >> > >> I have a follow up question. Do you know of any 3.3V <-> 5V integrated > >> translaters around? I can do the translation with a few discrete > >> componentents but I rather use a IC. Any hints??? > >> > >> / Jonas > >> > > > >The best way is to use parts generically called ``QuickSwitch'' from the > >company that first made them [now owned by IDT]. These are basically a bunch > >of pass transistors that have the characteristic that the resistance > >increases as the voltage on the driving size approaches the device's VCC. In > >effect they clamp the output side to about VCC - 0.7. For our 3.3V conversion > >we power the 5V parts from a 3.9V supply. You can now get 3.3V versions which > >we are about to use in the same way to get LVTTL <-> SSTL2 conversion. > > > >These parts have the huge advantage that they add almost no delay - about > >250ps or so - in the transition range of 0 -> 3.0V where Ron stays at about > >10R. > > > >The best place to look for this stuff is probably Pericom's web site. > > Also, the additional power supply is easier than it might seem. You > can just use a diode to drop your 5V to ~4.3V, and power your > QuickSwitch off that. I prefer an active diode, ie. a transistor and a > resistor. You can get 8-bit bidirectional switching with just a > transistor, a resistor, and something cheap like a QS3244. > > Evan ... or a resistor + 3.9V Zener. The resistor needs to be quite a low value - say 47R - since cheap low voltage Zeners seem to require a couple of 10's of mA to keep Zenering. NB I've actually run the 5V QS parts quite happily from the 3.3V supply but, since there's no mention of VCC(min) in the data sheet we don't ship it like this.Article: 26507
Fastest is going to depend on how the counter is used, as well as the width of the counter. If the counter is free running, for example, you can get really fast by pipelining the carry, but it will cost you dearly in latency and area (Coregen won't do that). What kind of speeds are you looking at? width? counter controls (loadable, resets, etc)? Paul Smith wrote: > > I'd like to implement the fastest possible binary counter in a Spartan > II. Is the counter produced by coregen the fastest possible, or is > there a way to improve on what coregen comes up with? > > Has anyone been able to buy a Spartan II device? FindChips.com doesn't > find anything for XC2S. Yep. Try Nu Horizons or Insight. We got them from one of the two (not sure which now). We got XC2S50-5FG256 > > Paul Smith -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26508
Sorry about being off topic, but I know alot of the regulers here have
experience with VHDL.
I'm trying to figure out a cool way to resize buses in low level
modules, but am running into a brain block on how to do it.
Basically, I want to pass a generic that defines the length of a count,
and have the required bus widths automatically figured out for me.
In the example below, I want to pass a maximum count length of 600
(SLOT_MAX), and have the output bus SLOT automatically change to
accomodate the max length. Currently, I'm doing what is shown, passing
two generics. I'd rather not have to pass two, because then I have to
make sure that wherever the two are eventually defined (like in my
package) that they must manually entered correctly.
Any nifty tricks, or things that I should have known anyway?
Thanks,
John
entity VSLOTNUM3 is
generic(SLOT_MAX: integer := 600; -- Number of slots to be
tracked.
SLOT_WIDTH: integer := 10); -- Max number of bits in slot
value vector.
port (
CLK: in STD_LOGIC; -- Clock input
CE: in STD_LOGIC; -- Clock enable
CLR: in STD_LOGIC; -- Synchronous reset
SLOT: out STD_LOGIC_VECTOR (SLOT_WIDTH - 1 downto 0) --
Current time slot number
);
end VSLOTNUM3;
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 26509Hi, Someone know how to do a 2's complement multiplier with adders and others ?? How i can simulate with Xilinx FPGA soft, i don't understand the book, because i'm not english ?? I can't do it !! Thx SEB -- ***************************** Seb@stien.bizland.com *****************************Article: 26510
Dies ist eine mehrteilige Nachricht im MIME-Format. --------------DB1F27E003E9808CFF86ACE4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dear XILINX users, for my evaluation board I want to use the download cable with the USB port on a PC Client with two USB ports. Therefore I want to enable the USB interface in NT. Does anybody give me a hint were to find a USB driver? Does anybody have experience? Or should I do not even think of it? --------------DB1F27E003E9808CFF86ACE4 Content-Type: text/x-vcard; charset=us-ascii; name="juergen.otterbach.vcf" Content-Transfer-Encoding: 7bit Content-Description: Visitenkarte für Juergen Otterbach Content-Disposition: attachment; filename="juergen.otterbach.vcf" begin:vcard n:;Juergen Otterbach x-mozilla-html:FALSE version:2.1 email;internet:juergen.otterbach@t-online.de x-mozilla-cpt:;65535 fn:Juergen Otterbach end:vcard --------------DB1F27E003E9808CFF86ACE4--Article: 26511
create a Log2 function to count bits. It is a very useful function, which belongs in a package where you can get at it for all your designs. To make it kosher for synthesizers, the easiest way to do the Log2 is to keep dividing by zero until the quotient is zero. COunt the iterations to get your Log. p25486@my-deja.com wrote: > > Sorry about being off topic, but I know alot of the regulers here have > experience with VHDL. > > I'm trying to figure out a cool way to resize buses in low level > modules, but am running into a brain block on how to do it. > > Basically, I want to pass a generic that defines the length of a count, > and have the required bus widths automatically figured out for me. > > In the example below, I want to pass a maximum count length of 600 > (SLOT_MAX), and have the output bus SLOT automatically change to > accomodate the max length. Currently, I'm doing what is shown, passing > two generics. I'd rather not have to pass two, because then I have to > make sure that wherever the two are eventually defined (like in my > package) that they must manually entered correctly. > > Any nifty tricks, or things that I should have known anyway? > > Thanks, > > John > > entity VSLOTNUM3 is > generic(SLOT_MAX: integer := 600; -- Number of slots to be > tracked. > SLOT_WIDTH: integer := 10); -- Max number of bits in slot > value vector. > port ( > CLK: in STD_LOGIC; -- Clock input > CE: in STD_LOGIC; -- Clock enable > CLR: in STD_LOGIC; -- Synchronous reset > SLOT: out STD_LOGIC_VECTOR (SLOT_WIDTH - 1 downto 0) -- > Current time slot number > ); > > end VSLOTNUM3; > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26512
I have a discussion on multipliers for FPGAs on my website. You should find the information you are looking for there. Seb C wrote: > > Hi, > > Someone know how to do a 2's complement multiplier with adders and others ?? > > How i can simulate with Xilinx FPGA soft, i don't understand the book, > because i'm not english ?? I can't do it !! > > Thx > > SEB > > -- > ***************************** > Seb@stien.bizland.com > > ***************************** -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26513
USB is not supported in NT. If you find a way to do it, please share it as there are lots of us using NT. For an NT box, you'll have to use either an old xchecker, a parallel III cable, or the Multilinx with the parallel port connection. Juergen Otterbach wrote: > > Dear XILINX users, > for my evaluation board I want to use the download cable with the USB > port on a PC Client with two USB ports. Therefore I want to enable the > USB interface in NT. Does anybody give me a hint were to find a USB > driver? Does anybody have experience? Or should I do not even think of > it? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26514
You could take a look at the ATC17C512A on Atmel's site: http://www.atmel.com/atmel/products/select22.htm I've used smaller parts from them and they seem to work fine for Xilinx configuration. regards, tom Rascal wrote: > > giuseppe ha scritto nel messaggio <8sjfla$k8q$1@fe2.cs.interbusiness.it>... > : > :A manufacturer of serial PROM (or Eprom or EEprom) 17C512 DIP 8pin, usable > :to configure FPGA similar to Xilinx XC17c512LPD8C but 5V not 3.3V. > : > I, too, have searched for something like that a few moths ago. Presently > there seem to be no devices equivalent to Xilinx serial PROMs. -- Tom Burgess -- Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 26515
"peter" <peter.brandt@softhome.net> writes:
> And what about the Alliance toolset ? Synplify as precompiler, perfect
> (synplify does support scripting) but I would like to script the total flow.
It's possible with Alliance. I'm running Alliance under Solaris and
I'm running the various tools from a Tcl script. I haven't tried it
under NT, but it should work.
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 26516Just checked again and Atmel has PDIP packages only up to 256K - beyond that they only offer PLCC packages - sorry. Tom Burgess wrote: > > You could take a look at the ATC17C512A on Atmel's site: > http://www.atmel.com/atmel/products/select22.htm > I've used smaller parts from them and they seem > to work fine for Xilinx configuration. > > regards, tom > > Rascal wrote: > > > > giuseppe ha scritto nel messaggio <8sjfla$k8q$1@fe2.cs.interbusiness.it>... > > : > > :A manufacturer of serial PROM (or Eprom or EEprom) 17C512 DIP 8pin, usable > > :to configure FPGA similar to Xilinx XC17c512LPD8C but 5V not 3.3V. > > : > > I, too, have searched for something like that a few moths ago. Presently > > there seem to be no devices equivalent to Xilinx serial PROMs. > -- Tom Burgess Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 26517
> As an asic designer, I used altera components for prototyping (realtime > functional verification of subblocks) in the past. Currently (new job), we > are using the Xilinx environment. > With the Altera (quartus) tool, I was able to completely script (tcl) the > synthesis flow. Just run a few scripts (like synopsys) to do the job. No > interactive stuff, no display stuff ! Automatisation and batch runs, a real > need in a good design flow ! > But how about scripting in the foundation toolset ? Is it not possible ? > And what about the Alliance toolset ? Synplify as precompiler, perfect > (synplify does support scripting) but I would like to script the total flow. > > So, after desparately surfing the Xilinx website, is there anybody who knows > how to do scripting with the Xilinx tools ? We have a document on using makefiles to run Foundation at: http://www.xess.com/manuals/fndmake.pdf. Foundation also includes a new tool called xflow that is supposed to let you do this as well. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 26518
This is a multi-part message in MIME format.
--------------30802F542B8914A23CAC4176
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hello Peter,
There is a command-line command called xflow which will take an EDIF file
and run it through the the Xilinx tools including bitstream creation and
simulation file creation. Xflow is availible in Foundation, Alliance and ISE
packages. You can run this command from a TCL script in Synplfy (or FPGA
Express or Leonardo or Modelsim or any TCL interface) if you wish using the
"exec" command, you can run it from a batch/shell script, or just type it on the
command-line. You can run it with all default settings or customize the varoius
switches and design flow. It is pretty simple to use and learn. I find this
much easier to use than the TCL interface with Quartus and I am sure you will as
well once you get to know it a bit.
Complete documentation on xflow can be found at:
http://toolbox.xilinx.com/docsan/3_1i/data/common/dev/chap22/dev22000.htm
Hope this works for you.
-- Brian
peter wrote:
> Hi,
>
> As an asic designer, I used altera components for prototyping (realtime
> functional verification of subblocks) in the past. Currently (new job), we
> are using the Xilinx environment.
> With the Altera (quartus) tool, I was able to completely script (tcl) the
> synthesis flow. Just run a few scripts (like synopsys) to do the job. No
> interactive stuff, no display stuff ! Automatisation and batch runs, a real
> need in a good design flow !
> But how about scripting in the foundation toolset ? Is it not possible ?
> And what about the Alliance toolset ? Synplify as precompiler, perfect
> (synplify does support scripting) but I would like to script the total flow.
>
> So, after desparately surfing the Xilinx website, is there anybody who knows
> how to do scripting with the Xilinx tools ?
>
> regards,
>
> Peter
--------------30802F542B8914A23CAC4176
Content-Type: text/x-vcard; charset=us-ascii;
name="brian.philofsky.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brian Philofsky
Content-Disposition: attachment;
filename="brian.philofsky.vcf"
begin:vcard
n:Philofsky;Brian
tel;work:1-800-255-7778
x-mozilla-html:TRUE
url:http://www.xilinx.com
org:Xilinx, Inc.;Software Marketing
adr:;;2300 55th Street;Boulder;CO;80301;USA
version:2.1
email;internet:brianp@xilinx.com
title:Sr. Technical Marketing Engineer
fn:Brian Philofsky
end:vcard
--------------30802F542B8914A23CAC4176--
Article: 26519email resumes to: jobs4u@techie.com Project Description: Our client is looking for FPGA(Field Programmable Gate Array) designers to work on a major effort to become the embedded technology supplier of choice for the world’s leading telecommunications and networking companies. The project is part of the effort to utilize FPGA designers to help develop a new line of CPU boards, communication interfaces such as T1/E1 spans or fast serial ports) and protocol subsystems that can be sold off the shelf to customers so that their internal engineers and designers can utilize these platforms that will be used to develop chips to be used in mobile phones and telecommunications equipment. Day-to-Day Responsibilities: Consultants or FPGA Designers (Field Programmable Gate Array) will be involved with designing Programmable Logic Chips, otherwise known as PLD’s. These PLD’s make up a high density field of gates called FPGA Architectures. The FPGA designers will be involved with designing a “gate array” which is an unfinished chip with electronic components that have not yet been connected. The designer will complete the chip by designing and adhering the top metal layers which provide interconnecting pathways. Once these chips are designed, then they will be turned over to manufacturing for mass production. These chips will make up final products such as CPU boards, communication interfaces, and protocol subsystems that will be used in the telecommunications industry. There are a total of 9 groups for that have anywhere from 4 to 14 FPGA designers and Hardware Engineers that are working on the 3 major products for different customers. Submitted candidates will be placed in groups that need the most help. This is a cross functional project environment. Candidates will always work under a principal engineer. FPGA designers will track their performance and product development with Microsoft Project that will be reported to the head engineer. Essential Skills: Power PC PCI Hardware and Software VHDL Embedded Hardware Design 3 years experience in the industry Plus Skills: View Logic (Schematic Capture Product) Simulation Experience (Signal Quality or Timing Simulation experience) UNIX Experience Telecom Experience (T1/E1 Interfaces) Edwin Matos Resource Manager-National DivisionArticle: 26520
Ray Andraka <ray@andraka.com> writes:
> create a Log2 function to count bits. It is a very useful function, which
> belongs in a package where you can get at it for all your designs. To make it
> kosher for synthesizers, the easiest way to do the Log2 is to keep dividing by
> zero until the quotient is zero. COunt the iterations to get your Log.
Make that a "divide by two", and the answer will be a finite number of bits,
which fits in an FPGA easier! (Sorry, Ray, couldn't resist.)
Here's the log2 function I wrote, if you want it.
--------------------------------------------------------------------------------------------------
-- Base 2 log of Integer
--------------------------------------------------------------------------------------------------
function log2 ( num : integer) return integer is
variable diviser : integer; -- Divided to form result
variable acc : integer; -- accumulates result
begin
diviser := num;
acc := 0;
LogLoop : while (diviser >= 2) loop
diviser := diviser / 2;
acc := acc + 1;
end loop LogLoop;
return acc;
end function log2;
-Kent
Article: 26521Gotta love then divide by zeros. How else are we supposed to get an impulse function anyway :-) Anyway,here's mine: function Log2( input:integer ) return integer is variable temp,log:integer; begin temp:=input; log:=0; while (temp /= 0) loop temp:=temp/2; log:=log+1; end loop; return log; end;-- function log2; Kent Orthner wrote: > > Ray Andraka <ray@andraka.com> writes: > > create a Log2 function to count bits. It is a very useful function, which > > belongs in a package where you can get at it for all your designs. To make it > > kosher for synthesizers, the easiest way to do the Log2 is to keep dividing by > > zero until the quotient is zero. COunt the iterations to get your Log. > > Make that a "divide by two", and the answer will be a finite number of bits, > which fits in an FPGA easier! (Sorry, Ray, couldn't resist.) > > Here's the log2 function I wrote, if you want it. > > -------------------------------------------------------------------------------------------------- > -- Base 2 log of Integer > -------------------------------------------------------------------------------------------------- > function log2 ( num : integer) return integer is > variable diviser : integer; -- Divided to form result > variable acc : integer; -- accumulates result > > begin > diviser := num; > acc := 0; > LogLoop : while (diviser >= 2) loop > diviser := diviser / 2; > acc := acc + 1; > end loop LogLoop; > return acc; > end function log2; > > -Kent -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26522
Ray Andraka wrote: > The area constraints in 3.1 do work reasonably well with a hierarchical design. > As for the naming of stuff, the part that does not keep the same name from run > to run on the synthesizer is the inferred combinatorial logic. Flip-flops tend > to keep the names (I label everything) if you label your processes. If you > follow good high speed FPGA design so that your logic is mostly 1 level, then > you can get away with floorplanning the flip-flops and leaving the luts off. There are differences in the types of designs we do. I have found that I both need to put multiple levels of logic between flip-flops, and that at the speeds I've done designs (up to 133 MHz), that I can put multiple levels of logic between flip-flops with correct placement. When using multiple levels of logic, I have in the past hand mapped logic into entities and decorate these with the correct magic to produce FMAPs. These FMAPs have stable names, and can be floorplanned. Amplify gets almost as good of results, and is much easier and faster. Other than getting $$ from management. > Hierarchy is the > biggest help for reuse, rapid design and floorplanning. The big designs tend to > be made up of the same smaller pieces as the small designs, so it is very rare > that I have to start a floorplan from scratch. One thing I'd like to see in Amplify is hierarchical design. It would be nice on some designs to be able to floorplan an entity, and then step multiple copies of that entity across a FPGA. Or to floorplan an entity and move that to a different design. > One last thing, I run into people from time to time that tell me that you can't > do million + gate designs this way (using Rlocs and fmaps). The proof is in the > pudding, though. It is a quite successful flow for me. I figure I've done well > over 10 million Virtex gates in the last 8 months, the majority of those are > being clocked over 100 MHz and every one of them is in a -4 (slow) part. Yes, > all of those designs have been floorplanned, and all but one have RLOCs and > FMAPs embedded in the code. I am impressed. However, not all design gates are the same. Some fairly large designs are completely definable on a single page, and some smaller designs need hundreds of pages to define them. I seem to get the second type. For your design style, I don't think that Amplify would help you much. For me, it does. -- Phil HaysArticle: 26523
Aloha!
I started douing som testruns on the hc11rtl.vhd. I have found a few
gotchas:
(1) My synthesis tool didn't like the alias declaration of the mode bits (se
earlier post). I fixed this by creating a mode signal and doing a concurrent
assignment to it.
(2) Around row 1050, mode is used in the process control. mode is however
not in the sensitivity list for the process [1].
(3) During mapping to the target technology [2], the synthesis tool found
*lots* of timing loops. I will redo it and check a bit more thorough.
"S. Ramirez" wrote:
> Scott,
> Is there a list of errata for this core?
> -Simon Ramirez, Consultant
> Synchronous Design, Inc.
Notes:
-------
[1] Question: Are aliases to signals included in the sensitivity list
implicitly included in the sensitivity list? Tried to fathom the chapter
about alias in the LRM, but couldn't find/grasp if they are or not. If they
are, then problem (2) is due to the elimination of the alias declaration. If
not, there is a problem in the code.
[2] A modern DSM-technology. Let's see if we can get the HC11 to 250 MHz
shall we? ;-)
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning
---------------- Ericsson Microwave Systems AB -----------------
Joachim Strömbergson http://www.ericsson.se/microwave
ASIC System on Silicon engineer, nice to CUTE animals.
* Opinions above, expressed or implicit, are strictly personal *
------------- Spamfodder: regeringen@regeringen.se -------------
Article: 26524> Yep. Try Nu Horizons or Insight. We got them from one of the two (not sure > which now). We got XC2S50-5FG256 We've got our XC2S100-TQ144 from Insight....... H.
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